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Searched refs:zero_reg (Results 1 – 25 of 49) sorted by relevance

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/external/libvpx/libvpx/vpx_dsp/x86/
Dvariance_impl_avx2.c43 __m256i zero_reg = _mm256_set1_epi16(0); in vpx_get16x16var_avx2() local
61 src_expand_low = _mm256_unpacklo_epi8(src, zero_reg); in vpx_get16x16var_avx2()
62 src_expand_high = _mm256_unpackhi_epi8(src, zero_reg); in vpx_get16x16var_avx2()
64 ref_expand_low = _mm256_unpacklo_epi8(ref, zero_reg); in vpx_get16x16var_avx2()
65 ref_expand_high = _mm256_unpackhi_epi8(ref, zero_reg); in vpx_get16x16var_avx2()
105 _mm_unpacklo_epi16(_mm256_castsi256_si128(zero_reg), sum_res); in vpx_get16x16var_avx2()
107 _mm_unpackhi_epi16(_mm256_castsi256_si128(zero_reg), sum_res); in vpx_get16x16var_avx2()
117 _mm_unpacklo_epi32(madd_res, _mm256_castsi256_si128(zero_reg)); in vpx_get16x16var_avx2()
119 _mm_unpackhi_epi32(madd_res, _mm256_castsi256_si128(zero_reg)); in vpx_get16x16var_avx2()
124 _mm_unpacklo_epi32(expand_sum, _mm256_castsi256_si128(zero_reg)); in vpx_get16x16var_avx2()
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/external/v8/src/crankshaft/mips64/
Dlithium-codegen-mips64.cc778 __ Branch(&no_deopt, ne, a1, Operand(zero_reg)); in DeoptimizeIf()
951 __ Branch(&dividend_is_not_negative, ge, dividend, Operand(zero_reg)); in DoModByPowerOf2I()
953 __ dsubu(dividend, zero_reg, dividend); in DoModByPowerOf2I()
957 Operand(zero_reg)); in DoModByPowerOf2I()
960 __ dsubu(dividend, zero_reg, dividend); in DoModByPowerOf2I()
988 __ Branch(&remainder_not_zero, ne, result, Operand(zero_reg)); in DoModByConstI()
990 Operand(zero_reg)); in DoModByConstI()
1010 Operand(zero_reg)); in DoModI()
1024 __ mov(result_reg, zero_reg); in DoModI()
1030 __ Branch(&done, ge, left_reg, Operand(zero_reg)); in DoModI()
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Dlithium-codegen-mips64.h232 Register src1 = zero_reg,
233 const Operand& src2 = Operand(zero_reg));
236 Register src1 = zero_reg,
237 const Operand& src2 = Operand(zero_reg));
/external/v8/src/crankshaft/mips/
Dlithium-codegen-mips.cc790 __ Branch(&no_deopt, ne, a1, Operand(zero_reg)); in DeoptimizeIf()
962 __ Branch(&dividend_is_not_negative, ge, dividend, Operand(zero_reg)); in DoModByPowerOf2I()
964 __ subu(dividend, zero_reg, dividend); in DoModByPowerOf2I()
968 Operand(zero_reg)); in DoModByPowerOf2I()
971 __ subu(dividend, zero_reg, dividend); in DoModByPowerOf2I()
999 __ Branch(&remainder_not_zero, ne, result, Operand(zero_reg)); in DoModByConstI()
1001 Operand(zero_reg)); in DoModByConstI()
1021 Operand(zero_reg)); in DoModI()
1035 __ mov(result_reg, zero_reg); in DoModI()
1041 __ Branch(&done, ge, left_reg, Operand(zero_reg)); in DoModI()
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Dlithium-codegen-mips.h230 Register src1 = zero_reg,
231 const Operand& src2 = Operand(zero_reg));
234 Register src1 = zero_reg,
235 const Operand& src2 = Operand(zero_reg));
/external/v8/src/mips64/
Dassembler-mips64.cc133 zero_reg, in ToRegister()
605 Register nop_rt_reg = (type == 0) ? zero_reg : at; in IsNop()
607 rd == static_cast<uint32_t>(ToNumber(zero_reg)) && in IsNop()
1249 beq(zero_reg, zero_reg, offset); in b()
1254 bgezal(zero_reg, offset); in bal()
1286 DCHECK(!(rt.is(zero_reg))); in bgezc()
1293 DCHECK(!(rs.is(zero_reg))); in bgeuc()
1294 DCHECK(!(rt.is(zero_reg))); in bgeuc()
1302 DCHECK(!(rs.is(zero_reg))); in bgec()
1303 DCHECK(!(rt.is(zero_reg))); in bgec()
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Dcode-stubs-mips64.cc109 __ ctc1(zero_reg, FCSR); in Generate()
127 __ Branch(&error, ne, scratch, Operand(zero_reg)); in Generate()
151 __ Movz(result_reg, zero_reg, scratch); in Generate()
152 __ Branch(&done, eq, scratch, Operand(zero_reg)); in Generate()
161 __ Branch(&normal_exponent, le, result_reg, Operand(zero_reg)); in Generate()
162 __ mov(result_reg, zero_reg); in Generate()
179 __ mov(input_high, zero_reg); in Generate()
198 __ Branch(&pos_shift, ge, scratch, Operand(zero_reg)); in Generate()
201 __ Subu(scratch, zero_reg, scratch); in Generate()
214 __ Subu(result_reg, zero_reg, input_high); in Generate()
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Dmacro-assembler-mips64.cc238 Branch(&ok, eq, t8, Operand(zero_reg)); in RecordWriteField()
306 Branch(&ok, eq, at, Operand(zero_reg)); in RecordWriteForMap()
500 Branch(&done, ne, t8, Operand(zero_reg)); in RememberedSetHelper()
503 Ret(ne, t8, Operand(zero_reg)); in RememberedSetHelper()
536 nor(scratch, reg0, zero_reg); in GetNumberHash()
1521 daddiu(rd, zero_reg, (j.imm64_ & kImm16Mask)); in LiLower32BitHelper()
1523 ori(rd, zero_reg, (j.imm64_ & kImm16Mask)); in LiLower32BitHelper()
1569 ori(rd, zero_reg, (j.imm64_ >> 16) & kImm16Mask); in li()
1907 Branch(&msb_clear, ge, rs, Operand(zero_reg)); in Cvt_d_ul()
1958 Branch(&positive, ge, rs, Operand(zero_reg)); in Cvt_s_ul()
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Dcodegen-mips64.cc70 __ bne(a6, zero_reg, &lastb); in CreateMemCopyUint8Function()
79 __ bne(t8, zero_reg, &unaligned); in CreateMemCopyUint8Function()
80 __ subu(a3, zero_reg, a0); // In delay slot. in CreateMemCopyUint8Function()
83 __ beq(a3, zero_reg, &aligned); // Already aligned. in CreateMemCopyUint8Function()
133 __ Branch(USE_DELAY_SLOT, &skip_pref, gt, v1, Operand(zero_reg)); in CreateMemCopyUint8Function()
227 __ Branch(&leave, le, a2, Operand(zero_reg)); in CreateMemCopyUint8Function()
246 __ beq(a3, zero_reg, &ua_chk16w); in CreateMemCopyUint8Function()
299 __ Branch(USE_DELAY_SLOT, &ua_skip_pref, gt, v1, Operand(zero_reg)); in CreateMemCopyUint8Function()
335 __ Branch(USE_DELAY_SLOT, &ua_skip_pref, gt, v1, Operand(zero_reg)); in CreateMemCopyUint8Function()
534 __ beq(a2, zero_reg, &leave); in CreateMemCopyUint8Function()
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Dcode-stubs-mips64.h111 masm->instr_at_put(pos, BNE | (zero_reg.code() << kRsShift) | in PatchBranchIntoNop()
112 (zero_reg.code() << kRtShift) | (offset & kImm16Mask)); in PatchBranchIntoNop()
118 masm->instr_at_put(pos, BEQ | (zero_reg.code() << kRsShift) | in PatchNopIntoBranch()
119 (zero_reg.code() << kRtShift) | (offset & kImm16Mask)); in PatchNopIntoBranch()
Dmacro-assembler-mips64.h206 #define COND_ARGS Condition cond = al, Register rs = zero_reg, \
207 const Operand& rt = Operand(zero_reg), BranchDelaySlot bd = PROTECT
227 Register rs = zero_reg, const Operand& rt = Operand(zero_reg)) {
555 rt == static_cast<uint32_t>(ToNumber(zero_reg)) && in GetCodeMarker()
556 rs == static_cast<uint32_t>(ToNumber(zero_reg))); in GetCodeMarker()
725 void mov(Register rd, Register rt) { or_(rd, rt, zero_reg); } in mov()
1431 Branch(label, lt, overflow_check, Operand(zero_reg), bd);
1437 Branch(label, ge, overflow_check, Operand(zero_reg), bd);
1441 Ret(lt, overflow_check, Operand(zero_reg), bd);
1445 Ret(ge, overflow_check, Operand(zero_reg), bd);
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/external/v8/src/mips/
Dmacro-assembler-mips.cc222 Branch(&ok, eq, t8, Operand(zero_reg)); in RecordWriteField()
290 Branch(&ok, eq, at, Operand(zero_reg)); in RecordWriteForMap()
483 Branch(&done, ne, t8, Operand(zero_reg)); in RememberedSetHelper()
486 Ret(ne, t8, Operand(zero_reg)); in RememberedSetHelper()
518 nor(scratch, reg0, zero_reg); in GetNumberHash()
993 subu(at, zero_reg, rt.rm()); in Ror()
1012 lw(zero_reg, rs); in Pref()
1077 or_(tmp, zero_reg, tmp2); in ByteSwapSigned()
1091 or_(dest, tmp, zero_reg); in ByteSwapSigned()
1331 addiu(rd, zero_reg, j.imm32_); in li()
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Dassembler-mips.cc155 zero_reg, in ToRegister()
634 Register nop_rt_reg = (type == 0) ? zero_reg : at; in IsNop()
636 rd == static_cast<uint32_t>(ToNumber(zero_reg)) && in IsNop()
1263 beq(zero_reg, zero_reg, offset); in b()
1268 bgezal(zero_reg, offset); in bal()
1300 DCHECK(!(rt.is(zero_reg))); in bgezc()
1307 DCHECK(!(rs.is(zero_reg))); in bgeuc()
1308 DCHECK(!(rt.is(zero_reg))); in bgeuc()
1316 DCHECK(!(rs.is(zero_reg))); in bgec()
1317 DCHECK(!(rt.is(zero_reg))); in bgec()
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Dcode-stubs-mips.cc111 __ ctc1(zero_reg, FCSR); in Generate()
129 __ Branch(&error, ne, scratch, Operand(zero_reg)); in Generate()
153 __ Movz(result_reg, zero_reg, scratch); in Generate()
154 __ Branch(&done, eq, scratch, Operand(zero_reg)); in Generate()
163 __ Branch(&normal_exponent, le, result_reg, Operand(zero_reg)); in Generate()
164 __ mov(result_reg, zero_reg); in Generate()
181 __ mov(input_high, zero_reg); in Generate()
200 __ Branch(&pos_shift, ge, scratch, Operand(zero_reg)); in Generate()
203 __ Subu(scratch, zero_reg, scratch); in Generate()
216 __ Subu(result_reg, zero_reg, input_high); in Generate()
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Dcodegen-mips.cc70 __ bne(t2, zero_reg, &lastb); in CreateMemCopyUint8Function()
79 __ bne(t8, zero_reg, &unaligned); in CreateMemCopyUint8Function()
80 __ subu(a3, zero_reg, a0); // In delay slot. in CreateMemCopyUint8Function()
83 __ beq(a3, zero_reg, &aligned); // Already aligned. in CreateMemCopyUint8Function()
132 __ Branch(USE_DELAY_SLOT, &skip_pref, gt, v1, Operand(zero_reg)); in CreateMemCopyUint8Function()
226 __ Branch(&leave, le, a2, Operand(zero_reg)); in CreateMemCopyUint8Function()
245 __ beq(a3, zero_reg, &ua_chk16w); in CreateMemCopyUint8Function()
298 __ Branch(USE_DELAY_SLOT, &ua_skip_pref, gt, v1, Operand(zero_reg)); in CreateMemCopyUint8Function()
333 __ Branch(USE_DELAY_SLOT, &ua_skip_pref, gt, v1, Operand(zero_reg)); in CreateMemCopyUint8Function()
532 __ beq(a2, zero_reg, &leave); in CreateMemCopyUint8Function()
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Dcode-stubs-mips.h110 masm->instr_at_put(pos, BNE | (zero_reg.code() << kRsShift) | in PatchBranchIntoNop()
111 (zero_reg.code() << kRtShift) | (offset & kImm16Mask)); in PatchBranchIntoNop()
117 masm->instr_at_put(pos, BEQ | (zero_reg.code() << kRsShift) | in PatchNopIntoBranch()
118 (zero_reg.code() << kRtShift) | (offset & kImm16Mask)); in PatchNopIntoBranch()
/external/v8/src/regexp/mips64/
Dregexp-macro-assembler-mips64.cc263 __ Branch(&fallthrough, eq, a1, Operand(zero_reg)); in CheckNotBackReferenceIgnoreCase()
272 BranchOrBacktrack(on_no_match, gt, t1, Operand(zero_reg)); in CheckNotBackReferenceIgnoreCase()
365 __ mov(a3, zero_reg); in CheckNotBackReferenceIgnoreCase()
385 BranchOrBacktrack(on_no_match, eq, v0, Operand(zero_reg)); in CheckNotBackReferenceIgnoreCase()
412 __ Branch(&fallthrough, eq, a1, Operand(zero_reg)); in CheckNotBackReference()
421 BranchOrBacktrack(on_no_match, gt, t1, Operand(zero_reg)); in CheckNotBackReference()
471 Operand rhs = (c == 0) ? Operand(zero_reg) : Operand(c); in CheckCharacterAfterAnd()
480 Operand rhs = (c == 0) ? Operand(zero_reg) : Operand(c); in CheckNotCharacterAfterAnd()
529 BranchOrBacktrack(on_bit_set, ne, a0, Operand(zero_reg)); in CheckBitInTable()
609 BranchOrBacktrack(on_no_match, eq, a0, Operand(zero_reg)); in CheckSpecialCharacterClass()
[all …]
/external/v8/src/regexp/mips/
Dregexp-macro-assembler-mips.cc227 __ Branch(&fallthrough, eq, a1, Operand(zero_reg)); in CheckNotBackReferenceIgnoreCase()
236 BranchOrBacktrack(on_no_match, gt, t5, Operand(zero_reg)); in CheckNotBackReferenceIgnoreCase()
329 __ mov(a3, zero_reg); in CheckNotBackReferenceIgnoreCase()
349 BranchOrBacktrack(on_no_match, eq, v0, Operand(zero_reg)); in CheckNotBackReferenceIgnoreCase()
376 __ Branch(&fallthrough, le, a1, Operand(zero_reg)); in CheckNotBackReference()
385 BranchOrBacktrack(on_no_match, gt, t5, Operand(zero_reg)); in CheckNotBackReference()
441 Operand rhs = (c == 0) ? Operand(zero_reg) : Operand(c); in CheckCharacterAfterAnd()
450 Operand rhs = (c == 0) ? Operand(zero_reg) : Operand(c); in CheckNotCharacterAfterAnd()
499 BranchOrBacktrack(on_bit_set, ne, a0, Operand(zero_reg)); in CheckBitInTable()
579 BranchOrBacktrack(on_no_match, eq, a0, Operand(zero_reg)); in CheckSpecialCharacterClass()
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/external/v8/src/builtins/mips64/
Dbuiltins-mips64.cc80 Operand(zero_reg)); in Generate_InternalArrayCode()
109 Operand(zero_reg)); in Generate_ArrayCode()
148 __ Branch(&done_loop, lt, a3, Operand(zero_reg)); in Generate_MathMaxMin()
242 __ Branch(USE_DELAY_SLOT, &no_arguments, eq, a0, Operand(zero_reg)); in Generate_NumberConstructor()
290 __ Branch(USE_DELAY_SLOT, &no_arguments, eq, a0, Operand(zero_reg)); in Generate_NumberConstructor_ConstructStub()
365 __ Branch(USE_DELAY_SLOT, &no_arguments, eq, a0, Operand(zero_reg)); in Generate_StringConstructor()
380 __ Branch(&symbol_descriptive_string, eq, t1, Operand(zero_reg)); in Generate_StringConstructor()
381 __ Branch(&to_string, gt, t1, Operand(zero_reg)); in Generate_StringConstructor()
440 __ Branch(USE_DELAY_SLOT, &no_arguments, eq, a0, Operand(zero_reg)); in Generate_StringConstructor_ConstructStub()
456 __ Branch(&done_convert, eq, t1, Operand(zero_reg)); in Generate_StringConstructor_ConstructStub()
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/external/v8/src/builtins/mips/
Dbuiltins-mips.cc80 Operand(zero_reg)); in Generate_InternalArrayCode()
109 Operand(zero_reg)); in Generate_ArrayCode()
148 __ Branch(&done_loop, lt, a3, Operand(zero_reg)); in Generate_MathMaxMin()
244 __ Branch(USE_DELAY_SLOT, &no_arguments, eq, a0, Operand(zero_reg)); in Generate_NumberConstructor()
292 __ Branch(USE_DELAY_SLOT, &no_arguments, eq, a0, Operand(zero_reg)); in Generate_NumberConstructor_ConstructStub()
366 __ Branch(USE_DELAY_SLOT, &no_arguments, eq, a0, Operand(zero_reg)); in Generate_StringConstructor()
381 __ Branch(&symbol_descriptive_string, eq, t1, Operand(zero_reg)); in Generate_StringConstructor()
382 __ Branch(&to_string, gt, t1, Operand(zero_reg)); in Generate_StringConstructor()
441 __ Branch(USE_DELAY_SLOT, &no_arguments, eq, a0, Operand(zero_reg)); in Generate_StringConstructor_ConstructStub()
457 __ Branch(&done_convert, eq, t1, Operand(zero_reg)); in Generate_StringConstructor_ConstructStub()
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/external/v8/src/compiler/mips64/
Dcode-generator-mips64.cc59 return zero_reg; in InputOrZeroRegister()
99 return Operand(zero_reg); in InputImmediate()
181 void Generate() final { __ mov(result_, zero_reg); } in Generate()
468 __ Branch(USE_DELAY_SLOT, ool->entry(), eq, at, Operand(zero_reg)); \
494 __ Branch(USE_DELAY_SLOT, ool->entry(), eq, at, Operand(zero_reg)); \
965 __ Nor(i.OutputRegister(), i.InputRegister(0), zero_reg); in AssembleArchInstruction()
976 __ Nor(i.OutputRegister(), i.InputRegister(0), zero_reg); in AssembleArchInstruction()
1004 __ Branch(&skip_for_zero, eq, i.InputRegister(0), Operand(zero_reg)); in AssembleArchInstruction()
1006 __ Subu(reg2, zero_reg, i.InputRegister(0)); in AssembleArchInstruction()
1024 __ Branch(&skip_for_zero, eq, i.InputRegister(0), Operand(zero_reg)); in AssembleArchInstruction()
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/external/v8/src/compiler/mips/
Dcode-generator-mips.cc60 return zero_reg; in InputOrZeroRegister()
99 return Operand(zero_reg); in InputImmediate()
181 void Generate() final { __ mov(result_, zero_reg); } in Generate()
453 __ Branch(USE_DELAY_SLOT, ool->entry(), eq, at, Operand(zero_reg)); \
480 __ Branch(USE_DELAY_SLOT, ool->entry(), eq, at, Operand(zero_reg)); \
888 __ Nor(i.OutputRegister(), i.InputRegister(0), zero_reg); in AssembleArchInstruction()
903 __ Branch(&skip_for_zero, eq, i.InputRegister(0), Operand(zero_reg)); in AssembleArchInstruction()
905 __ Subu(reg2, zero_reg, i.InputRegister(0)); in AssembleArchInstruction()
1027 __ Ins(i.OutputRegister(), zero_reg, i.InputInt8(1), i.InputInt8(2)); in AssembleArchInstruction()
1383 __ Movz(i.OutputRegister(), zero_reg, kScratchReg); in AssembleArchInstruction()
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/external/v8/src/ic/mips64/
Dic-mips64.cc61 __ Branch(miss, ne, at, Operand(zero_reg)); in GenerateDictionaryLoad()
108 __ Branch(miss, ne, at, Operand(zero_reg)); in GenerateDictionaryStore()
385 __ Branch(&slow, ne, a4, Operand(zero_reg)); in GenerateMegamorphic()
561 Assembler::GetRt(instr) == static_cast<uint32_t>(zero_reg.code()); in HasInlinedSmiCode()
574 Assembler::GetRt(instr) == static_cast<uint32_t>(zero_reg.code()))) { in PatchInlinedSmiCode()
/external/v8/src/ic/mips/
Dic-mips.cc61 __ Branch(miss, ne, at, Operand(zero_reg)); in GenerateDictionaryLoad()
109 __ Branch(miss, ne, at, Operand(zero_reg)); in GenerateDictionaryStore()
380 __ Branch(&slow, ne, t0, Operand(zero_reg)); in GenerateMegamorphic()
560 Assembler::GetRt(instr) == static_cast<uint32_t>(zero_reg.code()); in HasInlinedSmiCode()
573 Assembler::GetRt(instr) == static_cast<uint32_t>(zero_reg.code()))) { in PatchInlinedSmiCode()
/external/v8/src/full-codegen/mips/
Dfull-codegen-mips.cc62 __ BranchShort(target, eq, at, Operand(zero_reg)); in EmitJumpIfNotSmi()
73 __ BranchShort(target, ne, at, Operand(zero_reg)); in EmitJumpIfSmi()
80 __ andi(zero_reg, reg, delta_to_patch_site % kImm16Mask); in EmitPatchInfo()
182 __ Branch(&loop_header, ne, a2, Operand(zero_reg)); in Generate()
372 __ mov(v0, zero_reg); in ClearAccumulator()
411 __ slt(at, a3, zero_reg); in EmitBackEdgeBookkeeping()
412 __ beq(at, zero_reg, &ok); in EmitBackEdgeBookkeeping()
441 __ Branch(&ok, ge, a3, Operand(zero_reg)); in EmitProfilingCounterHandlingForReturnSequence()
964 __ Branch(&next_test, ne, v0, Operand(zero_reg)); in VisitSwitchStatement()
1263 __ Branch(done, ne, at, Operand(zero_reg)); in EmitDynamicLookupFastCase()
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