| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 28 class MCInstrDesc; variable
243 const MCInstrDesc &MCID) { in BuildMI()
250 const MCInstrDesc &MCID, unsigned DestReg) { in BuildMI()
260 const DebugLoc &DL, const MCInstrDesc &MCID, in BuildMI()
276 const DebugLoc &DL, const MCInstrDesc &MCID, in BuildMI()
285 const DebugLoc &DL, const MCInstrDesc &MCID, in BuildMI()
295 const DebugLoc &DL, const MCInstrDesc &MCID, in BuildMI()
306 const MCInstrDesc &MCID) { in BuildMI()
316 const MCInstrDesc &MCID) { in BuildMI()
325 const MCInstrDesc &MCID) { in BuildMI()
[all …]
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| D | DFAPacketizer.h | 36 class MCInstrDesc; variable
104 bool canReserveResources(const llvm::MCInstrDesc *MID);
108 void reserveResources(const llvm::MCInstrDesc *MID);
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| /external/llvm/lib/MC/ |
| D | MCInstrDesc.cpp | 22 bool MCInstrDesc::getDeprecatedInfo(MCInst &MI, const MCSubtargetInfo &STI, in getDeprecatedInfo()
33 bool MCInstrDesc::mayAffectControlFlow(const MCInst &MI, in mayAffectControlFlow()
54 bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg, in hasImplicitDefOfPhysReg()
63 bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg, in hasDefOfPhysReg()
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| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| D | MCInstrInfo.h | 27 const MCInstrDesc *Desc; // Raw array to allow static init'n
33 void InitMCInstrInfo(const MCInstrDesc *D, unsigned NO) { in InitMCInstrInfo()
43 const MCInstrDesc &get(unsigned Opcode) const { in get()
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 25 class MCInstrDesc; variable
183 const MCInstrDesc &MCID) { in BuildMI()
192 const MCInstrDesc &MCID, in BuildMI()
205 const MCInstrDesc &MCID, in BuildMI()
219 const MCInstrDesc &MCID) { in BuildMI()
231 const MCInstrDesc &MCID) { in BuildMI()
241 const MCInstrDesc &MCID, in BuildMI()
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| D | MachineInstr.h | 61 const MCInstrDesc *MCID; // Instruction descriptor.
103 explicit MachineInstr(const MCInstrDesc &MCID, bool NoImp = false);
108 MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &MCID);
113 explicit MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl,
120 const MCInstrDesc &MCID);
191 const MCInstrDesc &getDesc() const { return *MCID; }
532 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
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| /external/llvm/include/llvm/MC/ |
| D | MCInstrInfo.h | 25 const MCInstrDesc *Desc; // Raw array to allow static init'n
33 void InitMCInstrInfo(const MCInstrDesc *D, const unsigned *NI, const char *ND, in InitMCInstrInfo()
45 const MCInstrDesc &get(unsigned Opcode) const { in get()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.h | 25 class MCInstrDesc; variable
52 const MCInstrDesc &II,
66 const MCInstrDesc *II,
76 const MCInstrDesc *II,
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| D | InstrEmitter.cpp | 115 const MCInstrDesc &II = TII->get(User->getMachineOpcode()); in EmitCopyFromReg()
188 const MCInstrDesc &II, in CreateVirtualRegisters()
275 const MCInstrDesc *II, in AddRegisterOperand()
285 const MCInstrDesc &MCID = MI->getDesc(); in AddRegisterOperand()
341 const MCInstrDesc *II, in AddOperand()
573 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); in EmitRegSequence()
614 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); in EmitDbgValue()
685 const MCInstrDesc &II = TII->get(Opc); in EmitMachineNode()
714 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); in EmitMachineNode()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.h | 26 class MCInstrDesc; variable
53 const MCInstrDesc &II,
68 const MCInstrDesc *II,
79 const MCInstrDesc *II,
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCHazardRecognizers.cpp | 31 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isLoadAfterStore()
41 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); in isLoadAfterStore()
57 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isBCTRAfterSet()
67 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); in isBCTRAfterSet()
87 bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID, in mustComeFirst()
149 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in ShouldPreferAnother()
177 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction()
285 const MCInstrDesc &MCID = DAG.TII->get(Opcode); in GetInstrType()
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| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.h | 100 const MCInstrDesc& getBrCond(SystemZCC::CondCodes CC) const;
101 const MCInstrDesc& getLongDispOpc(unsigned Opc) const;
103 const MCInstrDesc& getMemoryInstr(unsigned Opc, int64_t Offset = 0) const {
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 307 const MCInstrDesc &DefMCID,
311 const MCInstrDesc &DefMCID,
315 const MCInstrDesc &UseMCID,
319 const MCInstrDesc &UseMCID,
323 const MCInstrDesc &DefMCID,
325 const MCInstrDesc &UseMCID,
330 const MCInstrDesc &DefMCID, unsigned DefAdj,
333 const MCInstrDesc &UseMCID, unsigned UseAdj) const;
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| D | ARMHazardRecognizer.cpp | 22 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
43 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType()
46 const MCInstrDesc &LastMCID = LastMI->getDesc(); in getHazardType()
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| D | MLxExpansionPass.cpp | 187 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
287 const MCInstrDesc &MCID1 = TII->get(MulOpc); in ExpandFPMLxInstruction()
288 const MCInstrDesc &MCID2 = TII->get(AddSubOpc); in ExpandFPMLxInstruction()
344 const MCInstrDesc &MCID = MI->getDesc(); in ExpandFPMLxInstructions()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 223 const MCInstrDesc &DefMCID,
227 const MCInstrDesc &DefMCID,
231 const MCInstrDesc &UseMCID,
235 const MCInstrDesc &UseMCID,
239 const MCInstrDesc &DefMCID,
241 const MCInstrDesc &UseMCID,
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| D | ARMHazardRecognizer.cpp | 22 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
46 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType()
49 const MCInstrDesc &LastMCID = LastMI->getDesc(); in getHazardType()
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| D | ARMCodeEmitter.cpp | 99 const MCInstrDesc &MCID,
105 const MCInstrDesc &MCID) const;
450 const MCInstrDesc &MCID = MI.getDesc(); in getMachineOpValue()
765 const MCInstrDesc &MCID = MI.getDesc(); in emitLEApcrelJTInstruction()
920 const MCInstrDesc &MCID, in getMachineSoRegOpValue()
990 const MCInstrDesc &MCID) const { in getAddrModeSBit()
1002 const MCInstrDesc &MCID = MI.getDesc(); in emitDataProcessingInstruction()
1100 const MCInstrDesc &MCID = MI.getDesc(); in emitLoadStoreInstruction()
1178 const MCInstrDesc &MCID = MI.getDesc(); in emitMiscLoadStoreInstruction()
1263 const MCInstrDesc &MCID = MI.getDesc(); in emitLoadStoreMultipleInstruction()
[all …]
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| D | MLxExpansionPass.cpp | 140 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
221 const MCInstrDesc &MCID1 = TII->get(MulOpc); in ExpandFPMLxInstruction()
222 const MCInstrDesc &MCID2 = TII->get(AddSubOpc); in ExpandFPMLxInstruction()
276 const MCInstrDesc &MCID = MI->getDesc(); in ExpandFPMLxInstructions()
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsExpandPseudo.cpp | 64 const MCInstrDesc& MCid = I->getDesc(); in runOnMachineBasicBlock()
90 const MCInstrDesc& Mtc1Tdd = TII->get(Mips::MTC1); in ExpandBuildPairF64()
106 const MCInstrDesc& Mfc1Tdd = TII->get(Mips::MFC1); in ExpandExtractElementF64()
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| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | SIMCCodeEmitter.cpp | 41 bool isSrcOperand(const MCInstrDesc &Desc, unsigned OpNo) const;
78 bool SIMCCodeEmitter::isSrcOperand(const MCInstrDesc &Desc, in isSrcOperand()
196 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
281 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in getMachineOpValue()
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| /external/llvm/lib/CodeGen/ |
| D | DFAPacketizer.cpp | 119 bool DFAPacketizer::canReserveResources(const llvm::MCInstrDesc *MID) { in canReserveResources()
130 void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) { in reserveResources()
143 const llvm::MCInstrDesc &MID = MI.getDesc(); in canReserveResources()
151 const llvm::MCInstrDesc &MID = MI.getDesc(); in reserveResources()
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| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| D | PTXInstrInfo.cpp | 58 const MCInstrDesc &MCID = get(map[i].opcode); in copyPhysReg()
80 const MCInstrDesc &MCID = get(map[i].opcode); in copyRegToReg()
189 const MCInstrDesc &desc1 = instLast1.getDesc(); in AnalyzeBranch()
195 const MCInstrDesc &desc2 = IsSizeOne ? desc1 : instLast2.getDesc(); in AnalyzeBranch()
344 const MCInstrDesc &desc = inst.getDesc(); in IsAnyKindOfBranch()
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeDelaySlotFiller.cpp | 112 MCInstrDesc desc = candidate->getDesc(); in delayHasHazard()
186 MCInstrDesc brdesc = (--candidate)->getDesc(); in isDelayFiller()
214 MCInstrDesc desc = I->getDesc(); in findDelayInstr()
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| /external/swiftshader/third_party/LLVM/lib/Target/ |
| D | TargetInstrInfo.cpp | 31 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, in getRegClass()
133 const MCInstrDesc &MCID = MI->getDesc(); in isUnpredicatedTerminator()
|