| /external/llvm/test/CodeGen/AArch64/ |
| D | divrem.ll | 3 ; SDIVREM/UDIVREM DAG nodes are generated but expanded when lowering and
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUISelLowering.cpp | 40 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); in AMDGPUTargetLowering()
96 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG); in LowerOperation()
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 198 SDIVREM, UDIVREM, enumerator
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 204 SDIVREM, UDIVREM, enumerator
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| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinISelLowering.cpp | 87 setOperationAction(ISD::UDIVREM, MVT::i16, Expand); in BlackfinTargetLowering()
88 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in BlackfinTargetLowering()
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| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 154 setOperationAction(ISD::UDIVREM, MVT::i8, Expand); in MSP430TargetLowering()
160 setOperationAction(ISD::UDIVREM, MVT::i16, Expand); in MSP430TargetLowering()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 187 case ISD::UDIVREM: return "udivrem"; in getOperationName()
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| D | LegalizeVectorOps.cpp | 270 case ISD::UDIVREM: in LegalizeOp()
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| D | LegalizeIntegerTypes.cpp | 2634 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) { in ExpandIntRes_UDIV()
2635 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops); in ExpandIntRes_UDIV()
2660 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) { in ExpandIntRes_UREM()
2661 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops); in ExpandIntRes_UREM()
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| D | LegalizeDAG.cpp | 3235 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; in ExpandNode()
3254 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; in ExpandNode()
3967 case ISD::UDIVREM: in ConvertNodeToLibcall()
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| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUISelLowering.cpp | 185 setOperationAction(ISD::UDIVREM, MVT::i8, Expand); in SPUTargetLowering()
191 setOperationAction(ISD::UDIVREM, MVT::i16, Expand); in SPUTargetLowering()
197 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in SPUTargetLowering()
203 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in SPUTargetLowering()
209 setOperationAction(ISD::UDIVREM, MVT::i128, Expand); in SPUTargetLowering()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 147 setOperationAction(ISD::UDIVREM, MVT::i8, Expand); in MSP430TargetLowering()
153 setOperationAction(ISD::UDIVREM, MVT::i16, Expand); in MSP430TargetLowering()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 98 ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, in WebAssemblyTargetLowering()
|
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZISelDAGToDAG.cpp | 683 case ISD::UDIVREM: { in Select()
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| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 81 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in BPFTargetLowering()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 301 setOperationAction(ISD::UDIVREM, VT, Custom); in AMDGPUTargetLowering()
386 setOperationAction(ISD::UDIVREM, VT, Expand); in AMDGPUTargetLowering()
710 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG); in LowerOperation()
1359 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), in LowerUDIVREM64()
1571 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS); in LowerSDIVREM()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 130 setOperationAction(ISD::UDIVREM, MVT::i64, Custom); in MipsSETargetLowering()
137 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); in MipsSETargetLowering()
167 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in MipsSETargetLowering()
214 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in MipsSETargetLowering()
371 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true, in LowerOperation()
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeISelLowering.cpp | 104 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in MBlazeTargetLowering()
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 220 setTargetDAGCombine(ISD::UDIVREM); in MipsTargetLowering()
649 case ISD::UDIVREM: in PerformDAGCombine()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 3450 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; in ExpandNode()
3478 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; in ExpandNode()
3513 case ISD::UDIVREM: in ExpandNode()
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiISelLowering.cpp | 95 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in LanaiTargetLowering()
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| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 718 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in SparcTargetLowering()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 818 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); in ARMTargetLowering()
820 setOperationAction(ISD::UDIVREM, MVT::i64, Custom); in ARMTargetLowering()
823 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in ARMTargetLowering()
7219 case ISD::UDIVREM: return LowerDivRem(Op, DAG); in LowerOperation()
7254 case ISD::UDIVREM: in ReplaceNodeResults()
12009 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM || in getDivRemLibcall()
12027 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM || in getDivRemArgList()
12051 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && in LowerDivRem()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1879 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR, in HexagonTargetLowering()
1937 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::ADDC, in HexagonTargetLowering()
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 329 def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>;
|