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Searched refs:fbits (Results 1 – 24 of 24) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrVFP.td800 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
801 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits",
809 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
810 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits",
818 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
819 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits",
827 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
828 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits",
836 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
837 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits",
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrVFP.td78 // The VCVT to/from fixed-point instructions encode the 'fbits' operand
80 // source. It's encoded as "Size - fbits" where Size is the size of the
81 // fixed-point representation (32 or 16) and fbits is the value appearing
1554 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1555 IIC_fpCVTHI, "vcvt", ".s16.f16\t$dst, $a, $fbits", []>,
1559 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1560 IIC_fpCVTHI, "vcvt", ".u16.f16\t$dst, $a, $fbits", []>,
1564 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1565 IIC_fpCVTHI, "vcvt", ".s32.f16\t$dst, $a, $fbits", []>,
1569 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
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DARMInstrFormats.td1977 bits<5> fbits;
1980 let Inst{5} = fbits{0};
1981 let Inst{3-0} = fbits{4-1};
/external/v8/src/arm64/
Dsimulator-arm64.cc2344 int fbits = 64 - instr->FPScale(); in VisitFPFixedPointConvert() local
2352 set_dreg(dst, FixedToDouble(xreg(src), fbits, round)); in VisitFPFixedPointConvert()
2355 set_dreg(dst, FixedToDouble(wreg(src), fbits, round)); in VisitFPFixedPointConvert()
2358 set_dreg(dst, UFixedToDouble(xreg(src), fbits, round)); in VisitFPFixedPointConvert()
2362 UFixedToDouble(reg<uint32_t>(src), fbits, round)); in VisitFPFixedPointConvert()
2366 set_sreg(dst, FixedToFloat(xreg(src), fbits, round)); in VisitFPFixedPointConvert()
2369 set_sreg(dst, FixedToFloat(wreg(src), fbits, round)); in VisitFPFixedPointConvert()
2372 set_sreg(dst, UFixedToFloat(xreg(src), fbits, round)); in VisitFPFixedPointConvert()
2376 UFixedToFloat(reg<uint32_t>(src), fbits, round)); in VisitFPFixedPointConvert()
2716 double Simulator::FixedToDouble(int64_t src, int fbits, FPRounding round) { in FixedToDouble() argument
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Dsimulator-arm64.h715 double FixedToDouble(int64_t src, int fbits, FPRounding round_mode);
716 double UFixedToDouble(uint64_t src, int fbits, FPRounding round_mode);
717 float FixedToFloat(int64_t src, int fbits, FPRounding round_mode);
718 float UFixedToFloat(uint64_t src, int fbits, FPRounding round_mode);
Dmacro-assembler-arm64-inl.h1083 unsigned fbits) { in Scvtf() argument
1085 scvtf(fd, rn, fbits); in Scvtf()
1187 unsigned fbits) { in Ucvtf() argument
1189 ucvtf(fd, rn, fbits); in Ucvtf()
Dassembler-arm64.cc2096 unsigned fbits) { in scvtf() argument
2097 if (fbits == 0) { in scvtf()
2100 Emit(SF(rn) | FPType(fd) | SCVTF_fixed | FPScale(64 - fbits) | Rn(rn) | in scvtf()
2108 unsigned fbits) { in ucvtf() argument
2109 if (fbits == 0) { in ucvtf()
2112 Emit(SF(rn) | FPType(fd) | UCVTF_fixed | FPScale(64 - fbits) | Rn(rn) | in ucvtf()
Dassembler-arm64.h1651 void scvtf(const FPRegister& fd, const Register& rn, unsigned fbits = 0);
1654 void ucvtf(const FPRegister& fd, const Register& rn, unsigned fbits = 0);
Dmacro-assembler-arm64.h522 unsigned fbits = 0);
557 unsigned fbits = 0);
/external/vixl/src/aarch64/
Dassembler-aarch64.cc2369 void Assembler::fcvtzs(const Register& rd, const VRegister& vn, int fbits) { in NEON_FP2REGMISC_FCVT_LIST()
2371 VIXL_ASSERT((fbits >= 0) && (fbits <= rd.GetSizeInBits())); in NEON_FP2REGMISC_FCVT_LIST()
2372 if (fbits == 0) { in NEON_FP2REGMISC_FCVT_LIST()
2375 Emit(SF(rd) | FPType(vn) | FCVTZS_fixed | FPScale(64 - fbits) | Rn(vn) | in NEON_FP2REGMISC_FCVT_LIST()
2381 void Assembler::fcvtzs(const VRegister& vd, const VRegister& vn, int fbits) { in fcvtzs() argument
2382 VIXL_ASSERT(fbits >= 0); in fcvtzs()
2383 if (fbits == 0) { in fcvtzs()
2387 NEONShiftRightImmediate(vd, vn, fbits, NEON_FCVTZS_imm); in fcvtzs()
2392 void Assembler::fcvtzu(const Register& rd, const VRegister& vn, int fbits) { in fcvtzu() argument
2394 VIXL_ASSERT((fbits >= 0) && (fbits <= rd.GetSizeInBits())); in fcvtzu()
[all …]
Dlogic-aarch64.cc86 double Simulator::FixedToDouble(int64_t src, int fbits, FPRounding round) { in FixedToDouble() argument
88 return UFixedToDouble(src, fbits, round); in FixedToDouble()
90 return -UFixedToDouble(src, fbits, round); in FixedToDouble()
92 return -UFixedToDouble(-src, fbits, round); in FixedToDouble()
97 double Simulator::UFixedToDouble(uint64_t src, int fbits, FPRounding round) { in UFixedToDouble() argument
107 const int64_t exponent = highest_significant_bit - fbits; in UFixedToDouble()
113 float Simulator::FixedToFloat(int64_t src, int fbits, FPRounding round) { in FixedToFloat() argument
115 return UFixedToFloat(src, fbits, round); in FixedToFloat()
117 return -UFixedToFloat(src, fbits, round); in FixedToFloat()
119 return -UFixedToFloat(-src, fbits, round); in FixedToFloat()
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Dmacro-assembler-aarch64.h1270 void Fcvtzs(const Register& rd, const VRegister& vn, int fbits = 0) {
1274 fcvtzs(rd, vn, fbits);
1276 void Fcvtzu(const Register& rd, const VRegister& vn, int fbits = 0) {
1280 fcvtzu(rd, vn, fbits);
1772 void Scvtf(const VRegister& vd, const Register& rn, int fbits = 0) {
1776 scvtf(vd, rn, fbits);
2034 void Ucvtf(const VRegister& vd, const Register& rn, int fbits = 0) {
2038 ucvtf(vd, rn, fbits);
2660 void Scvtf(const VRegister& vd, const VRegister& vn, int fbits = 0) {
2663 scvtf(vd, vn, fbits);
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Dsimulator-aarch64.cc2435 int fbits = 64 - instr->GetFPScale(); in VisitFPFixedPointConvert() local
2443 WriteDRegister(dst, FixedToDouble(ReadXRegister(src), fbits, round)); in VisitFPFixedPointConvert()
2446 WriteDRegister(dst, FixedToDouble(ReadWRegister(src), fbits, round)); in VisitFPFixedPointConvert()
2449 WriteDRegister(dst, UFixedToDouble(ReadXRegister(src), fbits, round)); in VisitFPFixedPointConvert()
2454 fbits, in VisitFPFixedPointConvert()
2459 WriteSRegister(dst, FixedToFloat(ReadXRegister(src), fbits, round)); in VisitFPFixedPointConvert()
2462 WriteSRegister(dst, FixedToFloat(ReadWRegister(src), fbits, round)); in VisitFPFixedPointConvert()
2465 WriteSRegister(dst, UFixedToFloat(ReadXRegister(src), fbits, round)); in VisitFPFixedPointConvert()
2470 fbits, in VisitFPFixedPointConvert()
2476 FPToInt64(ReadDRegister(src) * std::pow(2.0, fbits), in VisitFPFixedPointConvert()
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Dsimulator-aarch64.h2471 int fbits,
2476 int fbits,
2843 int fbits = 0);
2848 int fbits = 0);
2918 R FPToFixed(T op, int fbits, bool is_signed, FPRounding rounding);
2931 double FixedToDouble(int64_t src, int fbits, FPRounding round_mode);
2932 double UFixedToDouble(uint64_t src, int fbits, FPRounding round_mode);
2933 float FixedToFloat(int64_t src, int fbits, FPRounding round_mode);
2934 float UFixedToFloat(uint64_t src, int fbits, FPRounding round_mode);
Dassembler-aarch64.h1480 void fcvtzs(const Register& rd, const VRegister& vn, int fbits = 0);
1483 void fcvtzu(const Register& rd, const VRegister& vn, int fbits = 0);
1486 void fcvtzs(const VRegister& vd, const VRegister& vn, int fbits = 0);
1489 void fcvtzu(const VRegister& vd, const VRegister& vn, int fbits = 0);
1504 void scvtf(const VRegister& fd, const Register& rn, int fbits = 0);
1507 void ucvtf(const VRegister& fd, const Register& rn, int fbits = 0);
1510 void scvtf(const VRegister& fd, const VRegister& vn, int fbits = 0);
1513 void ucvtf(const VRegister& fd, const VRegister& vn, int fbits = 0);
/external/vixl/test/aarch64/
Dtest-simulator-aarch64.cc156 int fbits);
159 int fbits);
899 for (unsigned fbits = 0; fbits <= d_size; ++fbits) { in TestFPToFixed_Helper() local
902 (masm.*helper)(rd, fn, fbits); in TestFPToFixed_Helper()
1186 for (unsigned fbits = 0; fbits <= d_bits; ++fbits, d++) { in TestFPToFixedS() local
1194 fbits, in TestFPToFixedS()
1197 fbits); in TestFPToFixedS()
1261 for (unsigned fbits = 0; fbits <= d_bits; ++fbits, d++) { in TestFPToFixedU() local
1269 fbits, in TestFPToFixedU()
1272 fbits); in TestFPToFixedU()
Dtest-assembler-aarch64.cc12828 for (int fbits = 1; fbits <= 32; fbits++) { in TestUScvtfHelper() local
12829 __ Scvtf(d0, x10, fbits); in TestUScvtfHelper()
12830 __ Ucvtf(d1, x10, fbits); in TestUScvtfHelper()
12831 __ Scvtf(d2, w11, fbits); in TestUScvtfHelper()
12832 __ Ucvtf(d3, w11, fbits); in TestUScvtfHelper()
12833 __ Str(d0, MemOperand(x0, fbits * kDRegSizeInBytes)); in TestUScvtfHelper()
12834 __ Str(d1, MemOperand(x1, fbits * kDRegSizeInBytes)); in TestUScvtfHelper()
12835 __ Str(d2, MemOperand(x2, fbits * kDRegSizeInBytes)); in TestUScvtfHelper()
12836 __ Str(d3, MemOperand(x3, fbits * kDRegSizeInBytes)); in TestUScvtfHelper()
12841 for (int fbits = 33; fbits <= 64; fbits++) { in TestUScvtfHelper() local
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/external/valgrind/VEX/priv/
Dguest_arm64_toIR.c9389 UInt fbits = 0; in dis_AdvSIMD_scalar_shift_by_imm() local
9390 Bool ok = getLaneInfo_IMMH_IMMB(&fbits, &size, immh, immb); in dis_AdvSIMD_scalar_shift_by_imm()
9397 vassert(fbits >= 1 && fbits <= (isD ? 64 : 32)); in dis_AdvSIMD_scalar_shift_by_imm()
9398 Double scale = two_to_the_minus(fbits); in dis_AdvSIMD_scalar_shift_by_imm()
9419 ch, dd, ch, nn, fbits); in dis_AdvSIMD_scalar_shift_by_imm()
9427 UInt fbits = 0; in dis_AdvSIMD_scalar_shift_by_imm() local
9428 Bool ok = getLaneInfo_IMMH_IMMB(&fbits, &size, immh, immb); in dis_AdvSIMD_scalar_shift_by_imm()
9435 vassert(fbits >= 1 && fbits <= (isD ? 64 : 32)); in dis_AdvSIMD_scalar_shift_by_imm()
9436 Double scale = two_to_the_plus(fbits); in dis_AdvSIMD_scalar_shift_by_imm()
9458 ch, dd, ch, nn, fbits); in dis_AdvSIMD_scalar_shift_by_imm()
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/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md2046 void fcvtzs(const Register& rd, const VRegister& vn, int fbits = 0)
2053 void fcvtzs(const VRegister& vd, const VRegister& vn, int fbits = 0)
2060 void fcvtzu(const Register& rd, const VRegister& vn, int fbits = 0)
2067 void fcvtzu(const VRegister& vd, const VRegister& vn, int fbits = 0)
3060 void scvtf(const VRegister& fd, const Register& rn, int fbits = 0)
3067 void scvtf(const VRegister& fd, const VRegister& vn, int fbits = 0)
4150 void ucvtf(const VRegister& fd, const Register& rn, int fbits = 0)
4157 void ucvtf(const VRegister& fd, const VRegister& vn, int fbits = 0)
/external/vixl/src/aarch32/
Dassembler-aarch32.cc15126 int32_t fbits) { in vcvt() argument
15134 if (encoded_dt.IsValid() && (fbits >= 1) && (fbits <= 32)) { in vcvt()
15136 uint32_t fbits_ = 64 - fbits; in vcvt()
15146 (((dt2.Is(S16) || dt2.Is(U16)) && (fbits <= 16)) || in vcvt()
15147 ((dt2.Is(S32) || dt2.Is(U32)) && (fbits >= 1) && (fbits <= 32)))) { in vcvt()
15152 uint32_t fbits_ = offset - fbits; in vcvt()
15162 (((dt1.Is(S16) || dt1.Is(U16)) && (fbits <= 16)) || in vcvt()
15163 ((dt1.Is(S32) || dt1.Is(U32)) && (fbits >= 1) && (fbits <= 32)))) { in vcvt()
15168 uint32_t fbits_ = offset - fbits; in vcvt()
15178 if (encoded_dt.IsValid() && (fbits >= 1) && (fbits <= 32)) { in vcvt()
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Dassembler-aarch32.h400 int32_t fbits);
406 int32_t fbits);
412 int32_t fbits);
4159 int32_t fbits);
4161 DataType dt1, DataType dt2, DRegister rd, DRegister rm, int32_t fbits) { in vcvt() argument
4162 vcvt(al, dt1, dt2, rd, rm, fbits); in vcvt()
4170 int32_t fbits);
4172 DataType dt1, DataType dt2, QRegister rd, QRegister rm, int32_t fbits) { in vcvt() argument
4173 vcvt(al, dt1, dt2, rd, rm, fbits); in vcvt()
4181 int32_t fbits);
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Ddisasm-aarch32.h1562 int32_t fbits);
1569 int32_t fbits);
1576 int32_t fbits);
Ddisasm-aarch32.cc4462 int32_t fbits) { in vcvt() argument
4466 << "#" << fbits; in vcvt()
4474 int32_t fbits) { in vcvt() argument
4478 << "#" << fbits; in vcvt()
4486 int32_t fbits) { in vcvt() argument
4490 << "#" << fbits; in vcvt()
24041 uint32_t fbits = in DecodeT32() local
24050 fbits); in DecodeT32()
24129 uint32_t fbits = in DecodeT32() local
24138 fbits); in DecodeT32()
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Dmacro-assembler-aarch32.h6406 int32_t fbits) { in Vcvt() argument
6413 vcvt(cond, dt1, dt2, rd, rm, fbits); in Vcvt()
6416 DataType dt1, DataType dt2, DRegister rd, DRegister rm, int32_t fbits) { in Vcvt() argument
6417 Vcvt(al, dt1, dt2, rd, rm, fbits); in Vcvt()
6425 int32_t fbits) { in Vcvt() argument
6432 vcvt(cond, dt1, dt2, rd, rm, fbits); in Vcvt()
6435 DataType dt1, DataType dt2, QRegister rd, QRegister rm, int32_t fbits) { in Vcvt() argument
6436 Vcvt(al, dt1, dt2, rd, rm, fbits); in Vcvt()
6444 int32_t fbits) { in Vcvt() argument
6451 vcvt(cond, dt1, dt2, rd, rm, fbits); in Vcvt()
[all …]