1/* 2 * This file was generated automatically by gen-mterp.py for 'arm64'. 3 * 4 * --> DO NOT EDIT <-- 5 */ 6 7/* File: arm64/header.S */ 8/* 9 * Copyright (C) 2016 The Android Open Source Project 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); 12 * you may not use this file except in compliance with the License. 13 * You may obtain a copy of the License at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an "AS IS" BASIS, 19 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 */ 23 24/* 25 Art assembly interpreter notes: 26 27 First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't 28 handle invoke, allows higher-level code to create frame & shadow frame. 29 30 Once that's working, support direct entry code & eliminate shadow frame (and 31 excess locals allocation. 32 33 Some (hopefully) temporary ugliness. We'll treat xFP as pointing to the 34 base of the vreg array within the shadow frame. Access the other fields, 35 dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue 36 the shadow frame mechanism of double-storing object references - via xFP & 37 number_of_vregs_. 38 39 */ 40 41/* 42ARM64 Runtime register usage conventions. 43 44 r0 : w0 is 32-bit return register and x0 is 64-bit. 45 r0-r7 : Argument registers. 46 r8-r15 : Caller save registers (used as temporary registers). 47 r16-r17: Also known as ip0-ip1, respectively. Used as scratch registers by 48 the linker, by the trampolines and other stubs (the backend uses 49 these as temporary registers). 50 r18 : Caller save register (used as temporary register). 51 r19 : Pointer to thread-local storage. 52 r20-r29: Callee save registers. 53 r30 : (lr) is reserved (the link register). 54 rsp : (sp) is reserved (the stack pointer). 55 rzr : (zr) is reserved (the zero register). 56 57 Floating-point registers 58 v0-v31 59 60 v0 : s0 is return register for singles (32-bit) and d0 for doubles (64-bit). 61 This is analogous to the C/C++ (hard-float) calling convention. 62 v0-v7 : Floating-point argument registers in both Dalvik and C/C++ conventions. 63 Also used as temporary and codegen scratch registers. 64 65 v0-v7 and v16-v31 : trashed across C calls. 66 v8-v15 : bottom 64-bits preserved across C calls (d8-d15 are preserved). 67 68 v16-v31: Used as codegen temp/scratch. 69 v8-v15 : Can be used for promotion. 70 71 Must maintain 16-byte stack alignment. 72 73Mterp notes: 74 75The following registers have fixed assignments: 76 77 reg nick purpose 78 x20 xPC interpreted program counter, used for fetching instructions 79 x21 xFP interpreted frame pointer, used for accessing locals and args 80 x22 xSELF self (Thread) pointer 81 x23 xINST first 16-bit code unit of current instruction 82 x24 xIBASE interpreted instruction base pointer, used for computed goto 83 x25 xREFS base of object references in shadow frame (ideally, we'll get rid of this later). 84 x26 wPROFILE jit profile hotness countdown 85 x16 ip scratch reg 86 x17 ip2 scratch reg (used by macros) 87 88Macros are provided for common operations. They MUST NOT alter unspecified registers or condition 89codes. 90*/ 91 92/* 93 * This is a #include, not a %include, because we want the C pre-processor 94 * to expand the macros into assembler assignment statements. 95 */ 96#include "asm_support.h" 97 98#define MTERP_PROFILE_BRANCHES 1 99#define MTERP_LOGGING 0 100 101/* During bringup, we'll use the shadow frame model instead of xFP */ 102/* single-purpose registers, given names for clarity */ 103#define xPC x20 104#define xFP x21 105#define xSELF x22 106#define xINST x23 107#define wINST w23 108#define xIBASE x24 109#define xREFS x25 110#define wPROFILE w26 111#define xPROFILE x26 112#define ip x16 113#define ip2 x17 114 115/* 116 * Instead of holding a pointer to the shadow frame, we keep xFP at the base of the vregs. So, 117 * to access other shadow frame fields, we need to use a backwards offset. Define those here. 118 */ 119#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) 120#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) 121#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) 122#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) 123#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) 124#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) 125#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) 126#define OFF_FP_CODE_ITEM OFF_FP(SHADOWFRAME_CODE_ITEM_OFFSET) 127#define OFF_FP_SHADOWFRAME OFF_FP(0) 128 129/* 130 * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must 131 * be done *before* something throws. 132 * 133 * It's okay to do this more than once. 134 * 135 * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped 136 * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction 137 * offset into the code_items_[] array. For effiency, we will "export" the 138 * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC 139 * to convert to a dex pc when needed. 140 */ 141.macro EXPORT_PC 142 str xPC, [xFP, #OFF_FP_DEX_PC_PTR] 143.endm 144 145/* 146 * Fetch the next instruction from xPC into wINST. Does not advance xPC. 147 */ 148.macro FETCH_INST 149 ldrh wINST, [xPC] 150.endm 151 152/* 153 * Fetch the next instruction from the specified offset. Advances xPC 154 * to point to the next instruction. "_count" is in 16-bit code units. 155 * 156 * Because of the limited size of immediate constants on ARM, this is only 157 * suitable for small forward movements (i.e. don't try to implement "goto" 158 * with this). 159 * 160 * This must come AFTER anything that can throw an exception, or the 161 * exception catch may miss. (This also implies that it must come after 162 * EXPORT_PC.) 163 */ 164.macro FETCH_ADVANCE_INST count 165 ldrh wINST, [xPC, #((\count)*2)]! 166.endm 167 168/* 169 * The operation performed here is similar to FETCH_ADVANCE_INST, except the 170 * src and dest registers are parameterized (not hard-wired to xPC and xINST). 171 */ 172.macro PREFETCH_ADVANCE_INST dreg, sreg, count 173 ldrh \dreg, [\sreg, #((\count)*2)]! 174.endm 175 176/* 177 * Similar to FETCH_ADVANCE_INST, but does not update xPC. Used to load 178 * xINST ahead of possible exception point. Be sure to manually advance xPC 179 * later. 180 */ 181.macro PREFETCH_INST count 182 ldrh wINST, [xPC, #((\count)*2)] 183.endm 184 185/* Advance xPC by some number of code units. */ 186.macro ADVANCE count 187 add xPC, xPC, #((\count)*2) 188.endm 189 190/* 191 * Fetch the next instruction from an offset specified by _reg and advance xPC. 192 * xPC to point to the next instruction. "_reg" must specify the distance 193 * in bytes, *not* 16-bit code units, and may be a signed value. Must not set flags. 194 * 195 */ 196.macro FETCH_ADVANCE_INST_RB reg 197 add xPC, xPC, \reg, sxtw 198 ldrh wINST, [xPC] 199.endm 200 201/* 202 * Fetch a half-word code unit from an offset past the current PC. The 203 * "_count" value is in 16-bit code units. Does not advance xPC. 204 * 205 * The "_S" variant works the same but treats the value as signed. 206 */ 207.macro FETCH reg, count 208 ldrh \reg, [xPC, #((\count)*2)] 209.endm 210 211.macro FETCH_S reg, count 212 ldrsh \reg, [xPC, #((\count)*2)] 213.endm 214 215/* 216 * Fetch one byte from an offset past the current PC. Pass in the same 217 * "_count" as you would for FETCH, and an additional 0/1 indicating which 218 * byte of the halfword you want (lo/hi). 219 */ 220.macro FETCH_B reg, count, byte 221 ldrb \reg, [xPC, #((\count)*2+(\byte))] 222.endm 223 224/* 225 * Put the instruction's opcode field into the specified register. 226 */ 227.macro GET_INST_OPCODE reg 228 and \reg, xINST, #255 229.endm 230 231/* 232 * Put the prefetched instruction's opcode field into the specified register. 233 */ 234.macro GET_PREFETCHED_OPCODE oreg, ireg 235 and \oreg, \ireg, #255 236.endm 237 238/* 239 * Begin executing the opcode in _reg. Clobbers reg 240 */ 241 242.macro GOTO_OPCODE reg 243 add \reg, xIBASE, \reg, lsl #7 244 br \reg 245.endm 246.macro GOTO_OPCODE_BASE base,reg 247 add \reg, \base, \reg, lsl #7 248 br \reg 249.endm 250 251/* 252 * Get/set the 32-bit value from a Dalvik register. 253 */ 254.macro GET_VREG reg, vreg 255 ldr \reg, [xFP, \vreg, uxtw #2] 256.endm 257.macro SET_VREG reg, vreg 258 str \reg, [xFP, \vreg, uxtw #2] 259 str wzr, [xREFS, \vreg, uxtw #2] 260.endm 261.macro SET_VREG_OBJECT reg, vreg, tmpreg 262 str \reg, [xFP, \vreg, uxtw #2] 263 str \reg, [xREFS, \vreg, uxtw #2] 264.endm 265 266/* 267 * Get/set the 64-bit value from a Dalvik register. 268 * TUNING: can we do better here? 269 */ 270.macro GET_VREG_WIDE reg, vreg 271 add ip2, xFP, \vreg, lsl #2 272 ldr \reg, [ip2] 273.endm 274.macro SET_VREG_WIDE reg, vreg 275 add ip2, xFP, \vreg, lsl #2 276 str \reg, [ip2] 277 add ip2, xREFS, \vreg, lsl #2 278 str xzr, [ip2] 279.endm 280 281/* 282 * Get the 32-bit value from a Dalvik register and sign-extend to 64-bit. 283 * Used to avoid an extra instruction in int-to-long. 284 */ 285.macro GET_VREG_S reg, vreg 286 ldrsw \reg, [xFP, \vreg, uxtw #2] 287.endm 288 289/* 290 * Convert a virtual register index into an address. 291 */ 292.macro VREG_INDEX_TO_ADDR reg, vreg 293 add \reg, xFP, \vreg, lsl #2 /* WARNING: handle shadow frame vreg zero if store */ 294.endm 295 296/* 297 * Refresh handler table. 298 */ 299.macro REFRESH_IBASE 300 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] 301.endm 302 303/* 304 * Save two registers to the stack. 305 */ 306.macro SAVE_TWO_REGS reg1, reg2, offset 307 stp \reg1, \reg2, [sp, #(\offset)] 308 .cfi_rel_offset \reg1, (\offset) 309 .cfi_rel_offset \reg2, (\offset) + 8 310.endm 311 312/* 313 * Restore two registers from the stack. 314 */ 315.macro RESTORE_TWO_REGS reg1, reg2, offset 316 ldp \reg1, \reg2, [sp, #(\offset)] 317 .cfi_restore \reg1 318 .cfi_restore \reg2 319.endm 320 321/* 322 * Increase frame size and save two registers to the bottom of the stack. 323 */ 324.macro SAVE_TWO_REGS_INCREASE_FRAME reg1, reg2, frame_adjustment 325 stp \reg1, \reg2, [sp, #-(\frame_adjustment)]! 326 .cfi_adjust_cfa_offset (\frame_adjustment) 327 .cfi_rel_offset \reg1, 0 328 .cfi_rel_offset \reg2, 8 329.endm 330 331/* 332 * Restore two registers from the bottom of the stack and decrease frame size. 333 */ 334.macro RESTORE_TWO_REGS_DECREASE_FRAME reg1, reg2, frame_adjustment 335 ldp \reg1, \reg2, [sp], #(\frame_adjustment) 336 .cfi_restore \reg1 337 .cfi_restore \reg2 338 .cfi_adjust_cfa_offset -(\frame_adjustment) 339.endm 340 341/* File: arm64/entry.S */ 342/* 343 * Copyright (C) 2016 The Android Open Source Project 344 * 345 * Licensed under the Apache License, Version 2.0 (the "License"); 346 * you may not use this file except in compliance with the License. 347 * You may obtain a copy of the License at 348 * 349 * http://www.apache.org/licenses/LICENSE-2.0 350 * 351 * Unless required by applicable law or agreed to in writing, software 352 * distributed under the License is distributed on an "AS IS" BASIS, 353 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 354 * See the License for the specific language governing permissions and 355 * limitations under the License. 356 */ 357 358 .text 359 360/* 361 * Interpreter entry point. 362 * On entry: 363 * x0 Thread* self/ 364 * x1 code_item 365 * x2 ShadowFrame 366 * x3 JValue* result_register 367 * 368 */ 369 .global ExecuteMterpImpl 370 .type ExecuteMterpImpl, %function 371 .balign 16 372 373ExecuteMterpImpl: 374 .cfi_startproc 375 SAVE_TWO_REGS_INCREASE_FRAME xPROFILE, x27, 80 376 SAVE_TWO_REGS xIBASE, xREFS, 16 377 SAVE_TWO_REGS xSELF, xINST, 32 378 SAVE_TWO_REGS xPC, xFP, 48 379 SAVE_TWO_REGS fp, lr, 64 380 add fp, sp, #64 381 382 /* Remember the return register */ 383 str x3, [x2, #SHADOWFRAME_RESULT_REGISTER_OFFSET] 384 385 /* Remember the code_item */ 386 str x1, [x2, #SHADOWFRAME_CODE_ITEM_OFFSET] 387 388 /* set up "named" registers */ 389 mov xSELF, x0 390 ldr w0, [x2, #SHADOWFRAME_NUMBER_OF_VREGS_OFFSET] 391 add xFP, x2, #SHADOWFRAME_VREGS_OFFSET // point to vregs. 392 add xREFS, xFP, w0, lsl #2 // point to reference array in shadow frame 393 ldr w0, [x2, #SHADOWFRAME_DEX_PC_OFFSET] // Get starting dex_pc. 394 add xPC, x1, #CODEITEM_INSNS_OFFSET // Point to base of insns[] 395 add xPC, xPC, w0, lsl #1 // Create direct pointer to 1st dex opcode 396 EXPORT_PC 397 398 /* Starting ibase */ 399 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] 400 401 /* Set up for backwards branches & osr profiling */ 402 ldr x0, [xFP, #OFF_FP_METHOD] 403 add x1, xFP, #OFF_FP_SHADOWFRAME 404 bl MterpSetUpHotnessCountdown 405 mov wPROFILE, w0 // Starting hotness countdown to xPROFILE 406 407 /* start executing the instruction at rPC */ 408 FETCH_INST // load wINST from rPC 409 GET_INST_OPCODE ip // extract opcode from wINST 410 GOTO_OPCODE ip // jump to next instruction 411 /* NOTE: no fallthrough */ 412 413 414 .global artMterpAsmInstructionStart 415 .type artMterpAsmInstructionStart, %function 416artMterpAsmInstructionStart = .L_op_nop 417 .text 418 419/* ------------------------------ */ 420 .balign 128 421.L_op_nop: /* 0x00 */ 422/* File: arm64/op_nop.S */ 423 FETCH_ADVANCE_INST 1 // advance to next instr, load rINST 424 GET_INST_OPCODE ip // ip<- opcode from rINST 425 GOTO_OPCODE ip // execute it 426 427/* ------------------------------ */ 428 .balign 128 429.L_op_move: /* 0x01 */ 430/* File: arm64/op_move.S */ 431 /* for move, move-object, long-to-int */ 432 /* op vA, vB */ 433 lsr w1, wINST, #12 // x1<- B from 15:12 434 ubfx w0, wINST, #8, #4 // x0<- A from 11:8 435 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 436 GET_VREG w2, w1 // x2<- fp[B] 437 GET_INST_OPCODE ip // ip<- opcode from wINST 438 .if 0 439 SET_VREG_OBJECT w2, w0 // fp[A]<- x2 440 .else 441 SET_VREG w2, w0 // fp[A]<- x2 442 .endif 443 GOTO_OPCODE ip // execute next instruction 444 445/* ------------------------------ */ 446 .balign 128 447.L_op_move_from16: /* 0x02 */ 448/* File: arm64/op_move_from16.S */ 449 /* for: move/from16, move-object/from16 */ 450 /* op vAA, vBBBB */ 451 FETCH w1, 1 // r1<- BBBB 452 lsr w0, wINST, #8 // r0<- AA 453 FETCH_ADVANCE_INST 2 // advance rPC, load wINST 454 GET_VREG w2, w1 // r2<- fp[BBBB] 455 GET_INST_OPCODE ip // extract opcode from wINST 456 .if 0 457 SET_VREG_OBJECT w2, w0 // fp[AA]<- r2 458 .else 459 SET_VREG w2, w0 // fp[AA]<- r2 460 .endif 461 GOTO_OPCODE ip // jump to next instruction 462 463/* ------------------------------ */ 464 .balign 128 465.L_op_move_16: /* 0x03 */ 466/* File: arm64/op_move_16.S */ 467 /* for: move/16, move-object/16 */ 468 /* op vAAAA, vBBBB */ 469 FETCH w1, 2 // w1<- BBBB 470 FETCH w0, 1 // w0<- AAAA 471 FETCH_ADVANCE_INST 3 // advance xPC, load xINST 472 GET_VREG w2, w1 // w2<- fp[BBBB] 473 GET_INST_OPCODE ip // extract opcode from xINST 474 .if 0 475 SET_VREG_OBJECT w2, w0 // fp[AAAA]<- w2 476 .else 477 SET_VREG w2, w0 // fp[AAAA]<- w2 478 .endif 479 GOTO_OPCODE ip // jump to next instruction 480 481/* ------------------------------ */ 482 .balign 128 483.L_op_move_wide: /* 0x04 */ 484/* File: arm64/op_move_wide.S */ 485 /* move-wide vA, vB */ 486 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 487 lsr w3, wINST, #12 // w3<- B 488 ubfx w2, wINST, #8, #4 // w2<- A 489 GET_VREG_WIDE x3, w3 490 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 491 GET_INST_OPCODE ip // extract opcode from wINST 492 SET_VREG_WIDE x3, w2 493 GOTO_OPCODE ip // jump to next instruction 494 495/* ------------------------------ */ 496 .balign 128 497.L_op_move_wide_from16: /* 0x05 */ 498/* File: arm64/op_move_wide_from16.S */ 499 /* move-wide/from16 vAA, vBBBB */ 500 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 501 FETCH w3, 1 // w3<- BBBB 502 lsr w2, wINST, #8 // w2<- AA 503 GET_VREG_WIDE x3, w3 504 FETCH_ADVANCE_INST 2 // advance rPC, load wINST 505 GET_INST_OPCODE ip // extract opcode from wINST 506 SET_VREG_WIDE x3, w2 507 GOTO_OPCODE ip // jump to next instruction 508 509/* ------------------------------ */ 510 .balign 128 511.L_op_move_wide_16: /* 0x06 */ 512/* File: arm64/op_move_wide_16.S */ 513 /* move-wide/16 vAAAA, vBBBB */ 514 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 515 FETCH w3, 2 // w3<- BBBB 516 FETCH w2, 1 // w2<- AAAA 517 GET_VREG_WIDE x3, w3 518 FETCH_ADVANCE_INST 3 // advance rPC, load rINST 519 SET_VREG_WIDE x3, w2 520 GET_INST_OPCODE ip // extract opcode from rINST 521 GOTO_OPCODE ip // jump to next instruction 522 523/* ------------------------------ */ 524 .balign 128 525.L_op_move_object: /* 0x07 */ 526/* File: arm64/op_move_object.S */ 527/* File: arm64/op_move.S */ 528 /* for move, move-object, long-to-int */ 529 /* op vA, vB */ 530 lsr w1, wINST, #12 // x1<- B from 15:12 531 ubfx w0, wINST, #8, #4 // x0<- A from 11:8 532 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 533 GET_VREG w2, w1 // x2<- fp[B] 534 GET_INST_OPCODE ip // ip<- opcode from wINST 535 .if 1 536 SET_VREG_OBJECT w2, w0 // fp[A]<- x2 537 .else 538 SET_VREG w2, w0 // fp[A]<- x2 539 .endif 540 GOTO_OPCODE ip // execute next instruction 541 542 543/* ------------------------------ */ 544 .balign 128 545.L_op_move_object_from16: /* 0x08 */ 546/* File: arm64/op_move_object_from16.S */ 547/* File: arm64/op_move_from16.S */ 548 /* for: move/from16, move-object/from16 */ 549 /* op vAA, vBBBB */ 550 FETCH w1, 1 // r1<- BBBB 551 lsr w0, wINST, #8 // r0<- AA 552 FETCH_ADVANCE_INST 2 // advance rPC, load wINST 553 GET_VREG w2, w1 // r2<- fp[BBBB] 554 GET_INST_OPCODE ip // extract opcode from wINST 555 .if 1 556 SET_VREG_OBJECT w2, w0 // fp[AA]<- r2 557 .else 558 SET_VREG w2, w0 // fp[AA]<- r2 559 .endif 560 GOTO_OPCODE ip // jump to next instruction 561 562 563/* ------------------------------ */ 564 .balign 128 565.L_op_move_object_16: /* 0x09 */ 566/* File: arm64/op_move_object_16.S */ 567/* File: arm64/op_move_16.S */ 568 /* for: move/16, move-object/16 */ 569 /* op vAAAA, vBBBB */ 570 FETCH w1, 2 // w1<- BBBB 571 FETCH w0, 1 // w0<- AAAA 572 FETCH_ADVANCE_INST 3 // advance xPC, load xINST 573 GET_VREG w2, w1 // w2<- fp[BBBB] 574 GET_INST_OPCODE ip // extract opcode from xINST 575 .if 1 576 SET_VREG_OBJECT w2, w0 // fp[AAAA]<- w2 577 .else 578 SET_VREG w2, w0 // fp[AAAA]<- w2 579 .endif 580 GOTO_OPCODE ip // jump to next instruction 581 582 583/* ------------------------------ */ 584 .balign 128 585.L_op_move_result: /* 0x0a */ 586/* File: arm64/op_move_result.S */ 587 /* for: move-result, move-result-object */ 588 /* op vAA */ 589 lsr w2, wINST, #8 // r2<- AA 590 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 591 ldr x0, [xFP, #OFF_FP_RESULT_REGISTER] // get pointer to result JType. 592 ldr w0, [x0] // r0 <- result.i. 593 GET_INST_OPCODE ip // extract opcode from wINST 594 .if 0 595 SET_VREG_OBJECT w0, w2, w1 // fp[AA]<- r0 596 .else 597 SET_VREG w0, w2 // fp[AA]<- r0 598 .endif 599 GOTO_OPCODE ip // jump to next instruction 600 601/* ------------------------------ */ 602 .balign 128 603.L_op_move_result_wide: /* 0x0b */ 604/* File: arm64/op_move_result_wide.S */ 605 /* for: move-result-wide */ 606 /* op vAA */ 607 lsr w2, wINST, #8 // r2<- AA 608 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 609 ldr x0, [xFP, #OFF_FP_RESULT_REGISTER] // get pointer to result JType. 610 ldr x0, [x0] // r0 <- result.i. 611 GET_INST_OPCODE ip // extract opcode from wINST 612 SET_VREG_WIDE x0, x2 // fp[AA]<- r0 613 GOTO_OPCODE ip // jump to next instruction 614 615/* ------------------------------ */ 616 .balign 128 617.L_op_move_result_object: /* 0x0c */ 618/* File: arm64/op_move_result_object.S */ 619/* File: arm64/op_move_result.S */ 620 /* for: move-result, move-result-object */ 621 /* op vAA */ 622 lsr w2, wINST, #8 // r2<- AA 623 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 624 ldr x0, [xFP, #OFF_FP_RESULT_REGISTER] // get pointer to result JType. 625 ldr w0, [x0] // r0 <- result.i. 626 GET_INST_OPCODE ip // extract opcode from wINST 627 .if 1 628 SET_VREG_OBJECT w0, w2, w1 // fp[AA]<- r0 629 .else 630 SET_VREG w0, w2 // fp[AA]<- r0 631 .endif 632 GOTO_OPCODE ip // jump to next instruction 633 634 635/* ------------------------------ */ 636 .balign 128 637.L_op_move_exception: /* 0x0d */ 638/* File: arm64/op_move_exception.S */ 639 /* move-exception vAA */ 640 lsr w2, wINST, #8 // w2<- AA 641 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 642 mov x1, #0 // w1<- 0 643 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 644 SET_VREG_OBJECT w3, w2 // fp[AA]<- exception obj 645 GET_INST_OPCODE ip // extract opcode from rINST 646 str x1, [xSELF, #THREAD_EXCEPTION_OFFSET] // clear exception 647 GOTO_OPCODE ip // jump to next instruction 648 649/* ------------------------------ */ 650 .balign 128 651.L_op_return_void: /* 0x0e */ 652/* File: arm64/op_return_void.S */ 653 .extern MterpThreadFenceForConstructor 654 bl MterpThreadFenceForConstructor 655 ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] 656 mov x0, xSELF 657 ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 658 b.ne .Lop_return_void_check 659.Lop_return_void_return: 660 mov x0, #0 661 b MterpReturn 662.Lop_return_void_check: 663 bl MterpSuspendCheck // (self) 664 b .Lop_return_void_return 665 666/* ------------------------------ */ 667 .balign 128 668.L_op_return: /* 0x0f */ 669/* File: arm64/op_return.S */ 670 /* 671 * Return a 32-bit value. 672 * 673 * for: return, return-object 674 */ 675 /* op vAA */ 676 .extern MterpThreadFenceForConstructor 677 bl MterpThreadFenceForConstructor 678 ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] 679 mov x0, xSELF 680 ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 681 b.ne .Lop_return_check 682.Lop_return_return: 683 lsr w2, wINST, #8 // r2<- AA 684 GET_VREG w0, w2 // r0<- vAA 685 b MterpReturn 686.Lop_return_check: 687 bl MterpSuspendCheck // (self) 688 b .Lop_return_return 689 690/* ------------------------------ */ 691 .balign 128 692.L_op_return_wide: /* 0x10 */ 693/* File: arm64/op_return_wide.S */ 694 /* 695 * Return a 64-bit value. 696 */ 697 /* return-wide vAA */ 698 /* op vAA */ 699 .extern MterpThreadFenceForConstructor 700 bl MterpThreadFenceForConstructor 701 ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] 702 mov x0, xSELF 703 ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 704 b.ne .Lop_return_wide_check 705.Lop_return_wide_return: 706 lsr w2, wINST, #8 // w2<- AA 707 GET_VREG_WIDE x0, w2 // x0<- vAA 708 b MterpReturn 709.Lop_return_wide_check: 710 bl MterpSuspendCheck // (self) 711 b .Lop_return_wide_return 712 713/* ------------------------------ */ 714 .balign 128 715.L_op_return_object: /* 0x11 */ 716/* File: arm64/op_return_object.S */ 717/* File: arm64/op_return.S */ 718 /* 719 * Return a 32-bit value. 720 * 721 * for: return, return-object 722 */ 723 /* op vAA */ 724 .extern MterpThreadFenceForConstructor 725 bl MterpThreadFenceForConstructor 726 ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] 727 mov x0, xSELF 728 ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 729 b.ne .Lop_return_object_check 730.Lop_return_object_return: 731 lsr w2, wINST, #8 // r2<- AA 732 GET_VREG w0, w2 // r0<- vAA 733 b MterpReturn 734.Lop_return_object_check: 735 bl MterpSuspendCheck // (self) 736 b .Lop_return_object_return 737 738 739/* ------------------------------ */ 740 .balign 128 741.L_op_const_4: /* 0x12 */ 742/* File: arm64/op_const_4.S */ 743 /* const/4 vA, #+B */ 744 sbfx w1, wINST, #12, #4 // w1<- sssssssB 745 ubfx w0, wINST, #8, #4 // w0<- A 746 FETCH_ADVANCE_INST 1 // advance xPC, load wINST 747 GET_INST_OPCODE ip // ip<- opcode from xINST 748 SET_VREG w1, w0 // fp[A]<- w1 749 GOTO_OPCODE ip // execute next instruction 750 751/* ------------------------------ */ 752 .balign 128 753.L_op_const_16: /* 0x13 */ 754/* File: arm64/op_const_16.S */ 755 /* const/16 vAA, #+BBBB */ 756 FETCH_S w0, 1 // w0<- ssssBBBB (sign-extended) 757 lsr w3, wINST, #8 // w3<- AA 758 FETCH_ADVANCE_INST 2 // advance xPC, load wINST 759 SET_VREG w0, w3 // vAA<- w0 760 GET_INST_OPCODE ip // extract opcode from wINST 761 GOTO_OPCODE ip // jump to next instruction 762 763/* ------------------------------ */ 764 .balign 128 765.L_op_const: /* 0x14 */ 766/* File: arm64/op_const.S */ 767 /* const vAA, #+BBBBbbbb */ 768 lsr w3, wINST, #8 // w3<- AA 769 FETCH w0, 1 // w0<- bbbb (low 770 FETCH w1, 2 // w1<- BBBB (high 771 FETCH_ADVANCE_INST 3 // advance rPC, load wINST 772 orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb 773 GET_INST_OPCODE ip // extract opcode from wINST 774 SET_VREG w0, w3 // vAA<- w0 775 GOTO_OPCODE ip // jump to next instruction 776 777/* ------------------------------ */ 778 .balign 128 779.L_op_const_high16: /* 0x15 */ 780/* File: arm64/op_const_high16.S */ 781 /* const/high16 vAA, #+BBBB0000 */ 782 FETCH w0, 1 // r0<- 0000BBBB (zero-extended) 783 lsr w3, wINST, #8 // r3<- AA 784 lsl w0, w0, #16 // r0<- BBBB0000 785 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 786 SET_VREG w0, w3 // vAA<- r0 787 GET_INST_OPCODE ip // extract opcode from rINST 788 GOTO_OPCODE ip // jump to next instruction 789 790/* ------------------------------ */ 791 .balign 128 792.L_op_const_wide_16: /* 0x16 */ 793/* File: arm64/op_const_wide_16.S */ 794 /* const-wide/16 vAA, #+BBBB */ 795 FETCH_S x0, 1 // x0<- ssssssssssssBBBB (sign-extended) 796 lsr w3, wINST, #8 // w3<- AA 797 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 798 GET_INST_OPCODE ip // extract opcode from rINST 799 SET_VREG_WIDE x0, w3 800 GOTO_OPCODE ip // jump to next instruction 801 802/* ------------------------------ */ 803 .balign 128 804.L_op_const_wide_32: /* 0x17 */ 805/* File: arm64/op_const_wide_32.S */ 806 /* const-wide/32 vAA, #+BBBBbbbb */ 807 FETCH w0, 1 // x0<- 000000000000bbbb (low) 808 lsr w3, wINST, #8 // w3<- AA 809 FETCH_S x2, 2 // x2<- ssssssssssssBBBB (high) 810 FETCH_ADVANCE_INST 3 // advance rPC, load wINST 811 GET_INST_OPCODE ip // extract opcode from wINST 812 orr x0, x0, x2, lsl #16 // x0<- ssssssssBBBBbbbb 813 SET_VREG_WIDE x0, w3 814 GOTO_OPCODE ip // jump to next instruction 815 816/* ------------------------------ */ 817 .balign 128 818.L_op_const_wide: /* 0x18 */ 819/* File: arm64/op_const_wide.S */ 820 /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ 821 FETCH w0, 1 // w0<- bbbb (low) 822 FETCH w1, 2 // w1<- BBBB (low middle) 823 FETCH w2, 3 // w2<- hhhh (high middle) 824 FETCH w3, 4 // w3<- HHHH (high) 825 lsr w4, wINST, #8 // r4<- AA 826 FETCH_ADVANCE_INST 5 // advance rPC, load wINST 827 GET_INST_OPCODE ip // extract opcode from wINST 828 orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb 829 orr x0, x0, x2, lsl #32 // w0<- hhhhBBBBbbbb 830 orr x0, x0, x3, lsl #48 // w0<- HHHHhhhhBBBBbbbb 831 SET_VREG_WIDE x0, w4 832 GOTO_OPCODE ip // jump to next instruction 833 834/* ------------------------------ */ 835 .balign 128 836.L_op_const_wide_high16: /* 0x19 */ 837/* File: arm64/op_const_wide_high16.S */ 838 /* const-wide/high16 vAA, #+BBBB000000000000 */ 839 FETCH w0, 1 // w0<- 0000BBBB (zero-extended) 840 lsr w1, wINST, #8 // w1<- AA 841 FETCH_ADVANCE_INST 2 // advance rPC, load wINST 842 lsl x0, x0, #48 843 SET_VREG_WIDE x0, w1 844 GET_INST_OPCODE ip // extract opcode from wINST 845 GOTO_OPCODE ip // jump to next instruction 846 847/* ------------------------------ */ 848 .balign 128 849.L_op_const_string: /* 0x1a */ 850/* File: arm64/op_const_string.S */ 851 /* const/string vAA, String//BBBB */ 852 EXPORT_PC 853 FETCH w0, 1 // w0<- BBBB 854 lsr w1, wINST, #8 // w1<- AA 855 add x2, xFP, #OFF_FP_SHADOWFRAME 856 mov x3, xSELF 857 bl MterpConstString // (index, tgt_reg, shadow_frame, self) 858 PREFETCH_INST 2 // load rINST 859 cbnz w0, MterpPossibleException // let reference interpreter deal with it. 860 ADVANCE 2 // advance rPC 861 GET_INST_OPCODE ip // extract opcode from rINST 862 GOTO_OPCODE ip // jump to next instruction 863 864/* ------------------------------ */ 865 .balign 128 866.L_op_const_string_jumbo: /* 0x1b */ 867/* File: arm64/op_const_string_jumbo.S */ 868 /* const/string vAA, String//BBBBBBBB */ 869 EXPORT_PC 870 FETCH w0, 1 // w0<- bbbb (low 871 FETCH w2, 2 // w2<- BBBB (high 872 lsr w1, wINST, #8 // w1<- AA 873 orr w0, w0, w2, lsl #16 // w1<- BBBBbbbb 874 add x2, xFP, #OFF_FP_SHADOWFRAME 875 mov x3, xSELF 876 bl MterpConstString // (index, tgt_reg, shadow_frame, self) 877 PREFETCH_INST 3 // advance rPC 878 cbnz w0, MterpPossibleException // let reference interpreter deal with it. 879 ADVANCE 3 // advance rPC 880 GET_INST_OPCODE ip // extract opcode from rINST 881 GOTO_OPCODE ip // jump to next instruction 882 883/* ------------------------------ */ 884 .balign 128 885.L_op_const_class: /* 0x1c */ 886/* File: arm64/op_const_class.S */ 887 /* const/class vAA, Class//BBBB */ 888 EXPORT_PC 889 FETCH w0, 1 // w0<- BBBB 890 lsr w1, wINST, #8 // w1<- AA 891 add x2, xFP, #OFF_FP_SHADOWFRAME 892 mov x3, xSELF 893 bl MterpConstClass // (index, tgt_reg, shadow_frame, self) 894 PREFETCH_INST 2 895 cbnz w0, MterpPossibleException 896 ADVANCE 2 897 GET_INST_OPCODE ip // extract opcode from rINST 898 GOTO_OPCODE ip // jump to next instruction 899 900/* ------------------------------ */ 901 .balign 128 902.L_op_monitor_enter: /* 0x1d */ 903/* File: arm64/op_monitor_enter.S */ 904 /* 905 * Synchronize on an object. 906 */ 907 /* monitor-enter vAA */ 908 EXPORT_PC 909 lsr w2, wINST, #8 // w2<- AA 910 GET_VREG w0, w2 // w0<- vAA (object) 911 mov x1, xSELF // w1<- self 912 bl artLockObjectFromCode 913 cbnz w0, MterpException 914 FETCH_ADVANCE_INST 1 915 GET_INST_OPCODE ip // extract opcode from rINST 916 GOTO_OPCODE ip // jump to next instruction 917 918/* ------------------------------ */ 919 .balign 128 920.L_op_monitor_exit: /* 0x1e */ 921/* File: arm64/op_monitor_exit.S */ 922 /* 923 * Unlock an object. 924 * 925 * Exceptions that occur when unlocking a monitor need to appear as 926 * if they happened at the following instruction. See the Dalvik 927 * instruction spec. 928 */ 929 /* monitor-exit vAA */ 930 EXPORT_PC 931 lsr w2, wINST, #8 // w2<- AA 932 GET_VREG w0, w2 // w0<- vAA (object) 933 mov x1, xSELF // w0<- self 934 bl artUnlockObjectFromCode // w0<- success for unlock(self, obj) 935 cbnz w0, MterpException 936 FETCH_ADVANCE_INST 1 // before throw: advance rPC, load rINST 937 GET_INST_OPCODE ip // extract opcode from rINST 938 GOTO_OPCODE ip // jump to next instruction 939 940/* ------------------------------ */ 941 .balign 128 942.L_op_check_cast: /* 0x1f */ 943/* File: arm64/op_check_cast.S */ 944 /* 945 * Check to see if a cast from one class to another is allowed. 946 */ 947 /* check-cast vAA, class//BBBB */ 948 EXPORT_PC 949 FETCH w0, 1 // w0<- BBBB 950 lsr w1, wINST, #8 // w1<- AA 951 VREG_INDEX_TO_ADDR x1, w1 // w1<- &object 952 ldr x2, [xFP, #OFF_FP_METHOD] // w2<- method 953 mov x3, xSELF // w3<- self 954 bl MterpCheckCast // (index, &obj, method, self) 955 PREFETCH_INST 2 956 cbnz w0, MterpPossibleException 957 ADVANCE 2 958 GET_INST_OPCODE ip // extract opcode from rINST 959 GOTO_OPCODE ip // jump to next instruction 960 961/* ------------------------------ */ 962 .balign 128 963.L_op_instance_of: /* 0x20 */ 964/* File: arm64/op_instance_of.S */ 965 /* 966 * Check to see if an object reference is an instance of a class. 967 * 968 * Most common situation is a non-null object, being compared against 969 * an already-resolved class. 970 */ 971 /* instance-of vA, vB, class//CCCC */ 972 EXPORT_PC 973 FETCH w0, 1 // w0<- CCCC 974 lsr w1, wINST, #12 // w1<- B 975 VREG_INDEX_TO_ADDR x1, w1 // w1<- &object 976 ldr x2, [xFP, #OFF_FP_METHOD] // w2<- method 977 mov x3, xSELF // w3<- self 978 bl MterpInstanceOf // (index, &obj, method, self) 979 ldr x1, [xSELF, #THREAD_EXCEPTION_OFFSET] 980 ubfx w2, wINST, #8, #4 // w2<- A 981 PREFETCH_INST 2 982 cbnz x1, MterpException 983 ADVANCE 2 // advance rPC 984 SET_VREG w0, w2 // vA<- w0 985 GET_INST_OPCODE ip // extract opcode from rINST 986 GOTO_OPCODE ip // jump to next instruction 987 988/* ------------------------------ */ 989 .balign 128 990.L_op_array_length: /* 0x21 */ 991/* File: arm64/op_array_length.S */ 992 /* 993 * Return the length of an array. 994 */ 995 lsr w1, wINST, #12 // w1<- B 996 ubfx w2, wINST, #8, #4 // w2<- A 997 GET_VREG w0, w1 // w0<- vB (object ref) 998 cbz w0, common_errNullObject // yup, fail 999 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 1000 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- array length 1001 GET_INST_OPCODE ip // extract opcode from rINST 1002 SET_VREG w3, w2 // vB<- length 1003 GOTO_OPCODE ip // jump to next instruction 1004 1005/* ------------------------------ */ 1006 .balign 128 1007.L_op_new_instance: /* 0x22 */ 1008/* File: arm64/op_new_instance.S */ 1009 /* 1010 * Create a new instance of a class. 1011 */ 1012 /* new-instance vAA, class//BBBB */ 1013 EXPORT_PC 1014 add x0, xFP, #OFF_FP_SHADOWFRAME 1015 mov x1, xSELF 1016 mov w2, wINST 1017 bl MterpNewInstance // (shadow_frame, self, inst_data) 1018 cbz w0, MterpPossibleException 1019 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 1020 GET_INST_OPCODE ip // extract opcode from rINST 1021 GOTO_OPCODE ip // jump to next instruction 1022 1023/* ------------------------------ */ 1024 .balign 128 1025.L_op_new_array: /* 0x23 */ 1026/* File: arm64/op_new_array.S */ 1027 /* 1028 * Allocate an array of objects, specified with the array class 1029 * and a count. 1030 * 1031 * The verifier guarantees that this is an array class, so we don't 1032 * check for it here. 1033 */ 1034 /* new-array vA, vB, class//CCCC */ 1035 EXPORT_PC 1036 add x0, xFP, #OFF_FP_SHADOWFRAME 1037 mov x1, xPC 1038 mov w2, wINST 1039 mov x3, xSELF 1040 bl MterpNewArray 1041 cbz w0, MterpPossibleException 1042 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 1043 GET_INST_OPCODE ip // extract opcode from rINST 1044 GOTO_OPCODE ip // jump to next instruction 1045 1046/* ------------------------------ */ 1047 .balign 128 1048.L_op_filled_new_array: /* 0x24 */ 1049/* File: arm64/op_filled_new_array.S */ 1050 /* 1051 * Create a new array with elements filled from registers. 1052 * 1053 * for: filled-new-array, filled-new-array/range 1054 */ 1055 /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */ 1056 /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */ 1057 .extern MterpFilledNewArray 1058 EXPORT_PC 1059 add x0, xFP, #OFF_FP_SHADOWFRAME 1060 mov x1, xPC 1061 mov x2, xSELF 1062 bl MterpFilledNewArray 1063 cbz w0, MterpPossibleException 1064 FETCH_ADVANCE_INST 3 // advance rPC, load rINST 1065 GET_INST_OPCODE ip // extract opcode from rINST 1066 GOTO_OPCODE ip // jump to next instruction 1067 1068/* ------------------------------ */ 1069 .balign 128 1070.L_op_filled_new_array_range: /* 0x25 */ 1071/* File: arm64/op_filled_new_array_range.S */ 1072/* File: arm64/op_filled_new_array.S */ 1073 /* 1074 * Create a new array with elements filled from registers. 1075 * 1076 * for: filled-new-array, filled-new-array/range 1077 */ 1078 /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */ 1079 /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */ 1080 .extern MterpFilledNewArrayRange 1081 EXPORT_PC 1082 add x0, xFP, #OFF_FP_SHADOWFRAME 1083 mov x1, xPC 1084 mov x2, xSELF 1085 bl MterpFilledNewArrayRange 1086 cbz w0, MterpPossibleException 1087 FETCH_ADVANCE_INST 3 // advance rPC, load rINST 1088 GET_INST_OPCODE ip // extract opcode from rINST 1089 GOTO_OPCODE ip // jump to next instruction 1090 1091 1092/* ------------------------------ */ 1093 .balign 128 1094.L_op_fill_array_data: /* 0x26 */ 1095/* File: arm64/op_fill_array_data.S */ 1096 /* fill-array-data vAA, +BBBBBBBB */ 1097 EXPORT_PC 1098 FETCH w0, 1 // x0<- 000000000000bbbb (lo) 1099 FETCH_S x1, 2 // x1<- ssssssssssssBBBB (hi) 1100 lsr w3, wINST, #8 // w3<- AA 1101 orr x1, x0, x1, lsl #16 // x1<- ssssssssBBBBbbbb 1102 GET_VREG w0, w3 // w0<- vAA (array object) 1103 add x1, xPC, x1, lsl #1 // x1<- PC + ssssssssBBBBbbbb*2 (array data off.) 1104 bl MterpFillArrayData // (obj, payload) 1105 cbz w0, MterpPossibleException // exception? 1106 FETCH_ADVANCE_INST 3 // advance rPC, load rINST 1107 GET_INST_OPCODE ip // extract opcode from rINST 1108 GOTO_OPCODE ip // jump to next instruction 1109 1110/* ------------------------------ */ 1111 .balign 128 1112.L_op_throw: /* 0x27 */ 1113/* File: arm64/op_throw.S */ 1114 /* 1115 * Throw an exception object in the current thread. 1116 */ 1117 /* throw vAA */ 1118 EXPORT_PC 1119 lsr w2, wINST, #8 // r2<- AA 1120 GET_VREG w1, w2 // r1<- vAA (exception object) 1121 cbz w1, common_errNullObject 1122 str x1, [xSELF, #THREAD_EXCEPTION_OFFSET] // thread->exception<- obj 1123 b MterpException 1124 1125/* ------------------------------ */ 1126 .balign 128 1127.L_op_goto: /* 0x28 */ 1128/* File: arm64/op_goto.S */ 1129 /* 1130 * Unconditional branch, 8-bit offset. 1131 * 1132 * The branch distance is a signed code-unit offset, which we need to 1133 * double to get a byte offset. 1134 */ 1135 /* goto +AA */ 1136 sbfx wINST, wINST, #8, #8 // wINST<- ssssssAA (sign-extended) 1137 b MterpCommonTakenBranchNoFlags 1138 1139/* ------------------------------ */ 1140 .balign 128 1141.L_op_goto_16: /* 0x29 */ 1142/* File: arm64/op_goto_16.S */ 1143 /* 1144 * Unconditional branch, 16-bit offset. 1145 * 1146 * The branch distance is a signed code-unit offset, which we need to 1147 * double to get a byte offset. 1148 */ 1149 /* goto/16 +AAAA */ 1150 FETCH_S wINST, 1 // wINST<- ssssAAAA (sign-extended) 1151 b MterpCommonTakenBranchNoFlags 1152 1153/* ------------------------------ */ 1154 .balign 128 1155.L_op_goto_32: /* 0x2a */ 1156/* File: arm64/op_goto_32.S */ 1157 /* 1158 * Unconditional branch, 32-bit offset. 1159 * 1160 * The branch distance is a signed code-unit offset, which we need to 1161 * double to get a byte offset. 1162 * 1163 * Unlike most opcodes, this one is allowed to branch to itself, so 1164 * our "backward branch" test must be "<=0" instead of "<0". Because 1165 * we need the V bit set, we'll use an adds to convert from Dalvik 1166 * offset to byte offset. 1167 */ 1168 /* goto/32 +AAAAAAAA */ 1169 FETCH w0, 1 // w0<- aaaa (lo) 1170 FETCH w1, 2 // w1<- AAAA (hi) 1171 orr wINST, w0, w1, lsl #16 // wINST<- AAAAaaaa 1172 b MterpCommonTakenBranchNoFlags 1173 1174/* ------------------------------ */ 1175 .balign 128 1176.L_op_packed_switch: /* 0x2b */ 1177/* File: arm64/op_packed_switch.S */ 1178 /* 1179 * Handle a packed-switch or sparse-switch instruction. In both cases 1180 * we decode it and hand it off to a helper function. 1181 * 1182 * We don't really expect backward branches in a switch statement, but 1183 * they're perfectly legal, so we check for them here. 1184 * 1185 * for: packed-switch, sparse-switch 1186 */ 1187 /* op vAA, +BBBB */ 1188 FETCH w0, 1 // x0<- 000000000000bbbb (lo) 1189 FETCH_S x1, 2 // x1<- ssssssssssssBBBB (hi) 1190 lsr w3, wINST, #8 // w3<- AA 1191 orr x0, x0, x1, lsl #16 // x0<- ssssssssBBBBbbbb 1192 GET_VREG w1, w3 // w1<- vAA 1193 add x0, xPC, x0, lsl #1 // x0<- PC + ssssssssBBBBbbbb*2 1194 bl MterpDoPackedSwitch // w0<- code-unit branch offset 1195 sxtw xINST, w0 1196 b MterpCommonTakenBranchNoFlags 1197 1198/* ------------------------------ */ 1199 .balign 128 1200.L_op_sparse_switch: /* 0x2c */ 1201/* File: arm64/op_sparse_switch.S */ 1202/* File: arm64/op_packed_switch.S */ 1203 /* 1204 * Handle a packed-switch or sparse-switch instruction. In both cases 1205 * we decode it and hand it off to a helper function. 1206 * 1207 * We don't really expect backward branches in a switch statement, but 1208 * they're perfectly legal, so we check for them here. 1209 * 1210 * for: packed-switch, sparse-switch 1211 */ 1212 /* op vAA, +BBBB */ 1213 FETCH w0, 1 // x0<- 000000000000bbbb (lo) 1214 FETCH_S x1, 2 // x1<- ssssssssssssBBBB (hi) 1215 lsr w3, wINST, #8 // w3<- AA 1216 orr x0, x0, x1, lsl #16 // x0<- ssssssssBBBBbbbb 1217 GET_VREG w1, w3 // w1<- vAA 1218 add x0, xPC, x0, lsl #1 // x0<- PC + ssssssssBBBBbbbb*2 1219 bl MterpDoSparseSwitch // w0<- code-unit branch offset 1220 sxtw xINST, w0 1221 b MterpCommonTakenBranchNoFlags 1222 1223 1224/* ------------------------------ */ 1225 .balign 128 1226.L_op_cmpl_float: /* 0x2d */ 1227/* File: arm64/op_cmpl_float.S */ 1228/* File: arm64/fcmp.S */ 1229 /* 1230 * Compare two floating-point values. Puts 0, 1, or -1 into the 1231 * destination register based on the results of the comparison. 1232 */ 1233 /* op vAA, vBB, vCC */ 1234 FETCH w0, 1 // w0<- CCBB 1235 lsr w4, wINST, #8 // w4<- AA 1236 and w2, w0, #255 // w2<- BB 1237 lsr w3, w0, #8 // w3<- CC 1238 GET_VREG s1, w2 1239 GET_VREG s2, w3 1240 fcmp s1, s2 1241 cset w0, ne 1242 cneg w0, w0, lt 1243 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 1244 GET_INST_OPCODE ip // extract opcode from rINST 1245 SET_VREG w0, w4 // vAA<- w0 1246 GOTO_OPCODE ip // jump to next instruction 1247 1248 1249/* ------------------------------ */ 1250 .balign 128 1251.L_op_cmpg_float: /* 0x2e */ 1252/* File: arm64/op_cmpg_float.S */ 1253/* File: arm64/fcmp.S */ 1254 /* 1255 * Compare two floating-point values. Puts 0, 1, or -1 into the 1256 * destination register based on the results of the comparison. 1257 */ 1258 /* op vAA, vBB, vCC */ 1259 FETCH w0, 1 // w0<- CCBB 1260 lsr w4, wINST, #8 // w4<- AA 1261 and w2, w0, #255 // w2<- BB 1262 lsr w3, w0, #8 // w3<- CC 1263 GET_VREG s1, w2 1264 GET_VREG s2, w3 1265 fcmp s1, s2 1266 cset w0, ne 1267 cneg w0, w0, cc 1268 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 1269 GET_INST_OPCODE ip // extract opcode from rINST 1270 SET_VREG w0, w4 // vAA<- w0 1271 GOTO_OPCODE ip // jump to next instruction 1272 1273 1274/* ------------------------------ */ 1275 .balign 128 1276.L_op_cmpl_double: /* 0x2f */ 1277/* File: arm64/op_cmpl_double.S */ 1278/* File: arm64/fcmp.S */ 1279 /* 1280 * Compare two floating-point values. Puts 0, 1, or -1 into the 1281 * destination register based on the results of the comparison. 1282 */ 1283 /* op vAA, vBB, vCC */ 1284 FETCH w0, 1 // w0<- CCBB 1285 lsr w4, wINST, #8 // w4<- AA 1286 and w2, w0, #255 // w2<- BB 1287 lsr w3, w0, #8 // w3<- CC 1288 GET_VREG_WIDE d1, w2 1289 GET_VREG_WIDE d2, w3 1290 fcmp d1, d2 1291 cset w0, ne 1292 cneg w0, w0, lt 1293 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 1294 GET_INST_OPCODE ip // extract opcode from rINST 1295 SET_VREG w0, w4 // vAA<- w0 1296 GOTO_OPCODE ip // jump to next instruction 1297 1298 1299/* ------------------------------ */ 1300 .balign 128 1301.L_op_cmpg_double: /* 0x30 */ 1302/* File: arm64/op_cmpg_double.S */ 1303/* File: arm64/fcmp.S */ 1304 /* 1305 * Compare two floating-point values. Puts 0, 1, or -1 into the 1306 * destination register based on the results of the comparison. 1307 */ 1308 /* op vAA, vBB, vCC */ 1309 FETCH w0, 1 // w0<- CCBB 1310 lsr w4, wINST, #8 // w4<- AA 1311 and w2, w0, #255 // w2<- BB 1312 lsr w3, w0, #8 // w3<- CC 1313 GET_VREG_WIDE d1, w2 1314 GET_VREG_WIDE d2, w3 1315 fcmp d1, d2 1316 cset w0, ne 1317 cneg w0, w0, cc 1318 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 1319 GET_INST_OPCODE ip // extract opcode from rINST 1320 SET_VREG w0, w4 // vAA<- w0 1321 GOTO_OPCODE ip // jump to next instruction 1322 1323 1324/* ------------------------------ */ 1325 .balign 128 1326.L_op_cmp_long: /* 0x31 */ 1327/* File: arm64/op_cmp_long.S */ 1328 FETCH w0, 1 // w0<- CCBB 1329 lsr w4, wINST, #8 // w4<- AA 1330 and w2, w0, #255 // w2<- BB 1331 lsr w3, w0, #8 // w3<- CC 1332 GET_VREG_WIDE x1, w2 1333 GET_VREG_WIDE x2, w3 1334 cmp x1, x2 1335 cset w0, ne 1336 cneg w0, w0, lt 1337 FETCH_ADVANCE_INST 2 // advance rPC, load wINST 1338 SET_VREG w0, w4 1339 GET_INST_OPCODE ip // extract opcode from wINST 1340 GOTO_OPCODE ip // jump to next instruction 1341 1342/* ------------------------------ */ 1343 .balign 128 1344.L_op_if_eq: /* 0x32 */ 1345/* File: arm64/op_if_eq.S */ 1346/* File: arm64/bincmp.S */ 1347 /* 1348 * Generic two-operand compare-and-branch operation. Provide a "condition" 1349 * fragment that specifies the comparison to perform. 1350 * 1351 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1352 */ 1353 /* if-cmp vA, vB, +CCCC */ 1354 lsr w1, wINST, #12 // w1<- B 1355 ubfx w0, wINST, #8, #4 // w0<- A 1356 GET_VREG w3, w1 // w3<- vB 1357 GET_VREG w2, w0 // w2<- vA 1358 FETCH_S wINST, 1 // wINST<- branch offset, in code units 1359 cmp w2, w3 // compare (vA, vB) 1360 b.eq MterpCommonTakenBranchNoFlags 1361 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 1362 b.eq .L_check_not_taken_osr 1363 FETCH_ADVANCE_INST 2 1364 GET_INST_OPCODE ip // extract opcode from wINST 1365 GOTO_OPCODE ip // jump to next instruction 1366 1367 1368/* ------------------------------ */ 1369 .balign 128 1370.L_op_if_ne: /* 0x33 */ 1371/* File: arm64/op_if_ne.S */ 1372/* File: arm64/bincmp.S */ 1373 /* 1374 * Generic two-operand compare-and-branch operation. Provide a "condition" 1375 * fragment that specifies the comparison to perform. 1376 * 1377 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1378 */ 1379 /* if-cmp vA, vB, +CCCC */ 1380 lsr w1, wINST, #12 // w1<- B 1381 ubfx w0, wINST, #8, #4 // w0<- A 1382 GET_VREG w3, w1 // w3<- vB 1383 GET_VREG w2, w0 // w2<- vA 1384 FETCH_S wINST, 1 // wINST<- branch offset, in code units 1385 cmp w2, w3 // compare (vA, vB) 1386 b.ne MterpCommonTakenBranchNoFlags 1387 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 1388 b.eq .L_check_not_taken_osr 1389 FETCH_ADVANCE_INST 2 1390 GET_INST_OPCODE ip // extract opcode from wINST 1391 GOTO_OPCODE ip // jump to next instruction 1392 1393 1394/* ------------------------------ */ 1395 .balign 128 1396.L_op_if_lt: /* 0x34 */ 1397/* File: arm64/op_if_lt.S */ 1398/* File: arm64/bincmp.S */ 1399 /* 1400 * Generic two-operand compare-and-branch operation. Provide a "condition" 1401 * fragment that specifies the comparison to perform. 1402 * 1403 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1404 */ 1405 /* if-cmp vA, vB, +CCCC */ 1406 lsr w1, wINST, #12 // w1<- B 1407 ubfx w0, wINST, #8, #4 // w0<- A 1408 GET_VREG w3, w1 // w3<- vB 1409 GET_VREG w2, w0 // w2<- vA 1410 FETCH_S wINST, 1 // wINST<- branch offset, in code units 1411 cmp w2, w3 // compare (vA, vB) 1412 b.lt MterpCommonTakenBranchNoFlags 1413 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 1414 b.eq .L_check_not_taken_osr 1415 FETCH_ADVANCE_INST 2 1416 GET_INST_OPCODE ip // extract opcode from wINST 1417 GOTO_OPCODE ip // jump to next instruction 1418 1419 1420/* ------------------------------ */ 1421 .balign 128 1422.L_op_if_ge: /* 0x35 */ 1423/* File: arm64/op_if_ge.S */ 1424/* File: arm64/bincmp.S */ 1425 /* 1426 * Generic two-operand compare-and-branch operation. Provide a "condition" 1427 * fragment that specifies the comparison to perform. 1428 * 1429 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1430 */ 1431 /* if-cmp vA, vB, +CCCC */ 1432 lsr w1, wINST, #12 // w1<- B 1433 ubfx w0, wINST, #8, #4 // w0<- A 1434 GET_VREG w3, w1 // w3<- vB 1435 GET_VREG w2, w0 // w2<- vA 1436 FETCH_S wINST, 1 // wINST<- branch offset, in code units 1437 cmp w2, w3 // compare (vA, vB) 1438 b.ge MterpCommonTakenBranchNoFlags 1439 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 1440 b.eq .L_check_not_taken_osr 1441 FETCH_ADVANCE_INST 2 1442 GET_INST_OPCODE ip // extract opcode from wINST 1443 GOTO_OPCODE ip // jump to next instruction 1444 1445 1446/* ------------------------------ */ 1447 .balign 128 1448.L_op_if_gt: /* 0x36 */ 1449/* File: arm64/op_if_gt.S */ 1450/* File: arm64/bincmp.S */ 1451 /* 1452 * Generic two-operand compare-and-branch operation. Provide a "condition" 1453 * fragment that specifies the comparison to perform. 1454 * 1455 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1456 */ 1457 /* if-cmp vA, vB, +CCCC */ 1458 lsr w1, wINST, #12 // w1<- B 1459 ubfx w0, wINST, #8, #4 // w0<- A 1460 GET_VREG w3, w1 // w3<- vB 1461 GET_VREG w2, w0 // w2<- vA 1462 FETCH_S wINST, 1 // wINST<- branch offset, in code units 1463 cmp w2, w3 // compare (vA, vB) 1464 b.gt MterpCommonTakenBranchNoFlags 1465 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 1466 b.eq .L_check_not_taken_osr 1467 FETCH_ADVANCE_INST 2 1468 GET_INST_OPCODE ip // extract opcode from wINST 1469 GOTO_OPCODE ip // jump to next instruction 1470 1471 1472/* ------------------------------ */ 1473 .balign 128 1474.L_op_if_le: /* 0x37 */ 1475/* File: arm64/op_if_le.S */ 1476/* File: arm64/bincmp.S */ 1477 /* 1478 * Generic two-operand compare-and-branch operation. Provide a "condition" 1479 * fragment that specifies the comparison to perform. 1480 * 1481 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1482 */ 1483 /* if-cmp vA, vB, +CCCC */ 1484 lsr w1, wINST, #12 // w1<- B 1485 ubfx w0, wINST, #8, #4 // w0<- A 1486 GET_VREG w3, w1 // w3<- vB 1487 GET_VREG w2, w0 // w2<- vA 1488 FETCH_S wINST, 1 // wINST<- branch offset, in code units 1489 cmp w2, w3 // compare (vA, vB) 1490 b.le MterpCommonTakenBranchNoFlags 1491 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 1492 b.eq .L_check_not_taken_osr 1493 FETCH_ADVANCE_INST 2 1494 GET_INST_OPCODE ip // extract opcode from wINST 1495 GOTO_OPCODE ip // jump to next instruction 1496 1497 1498/* ------------------------------ */ 1499 .balign 128 1500.L_op_if_eqz: /* 0x38 */ 1501/* File: arm64/op_if_eqz.S */ 1502/* File: arm64/zcmp.S */ 1503 /* 1504 * Generic one-operand compare-and-branch operation. Provide a "condition" 1505 * fragment that specifies the comparison to perform. 1506 * 1507 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1508 */ 1509 /* if-cmp vAA, +BBBB */ 1510 lsr w0, wINST, #8 // w0<- AA 1511 GET_VREG w2, w0 // w2<- vAA 1512 FETCH_S wINST, 1 // w1<- branch offset, in code units 1513 .if 0 1514 cmp w2, #0 // compare (vA, 0) 1515 .endif 1516 cbz w2, MterpCommonTakenBranchNoFlags 1517 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 1518 b.eq .L_check_not_taken_osr 1519 FETCH_ADVANCE_INST 2 1520 GET_INST_OPCODE ip // extract opcode from wINST 1521 GOTO_OPCODE ip // jump to next instruction 1522 1523 1524/* ------------------------------ */ 1525 .balign 128 1526.L_op_if_nez: /* 0x39 */ 1527/* File: arm64/op_if_nez.S */ 1528/* File: arm64/zcmp.S */ 1529 /* 1530 * Generic one-operand compare-and-branch operation. Provide a "condition" 1531 * fragment that specifies the comparison to perform. 1532 * 1533 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1534 */ 1535 /* if-cmp vAA, +BBBB */ 1536 lsr w0, wINST, #8 // w0<- AA 1537 GET_VREG w2, w0 // w2<- vAA 1538 FETCH_S wINST, 1 // w1<- branch offset, in code units 1539 .if 0 1540 cmp w2, #0 // compare (vA, 0) 1541 .endif 1542 cbnz w2, MterpCommonTakenBranchNoFlags 1543 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 1544 b.eq .L_check_not_taken_osr 1545 FETCH_ADVANCE_INST 2 1546 GET_INST_OPCODE ip // extract opcode from wINST 1547 GOTO_OPCODE ip // jump to next instruction 1548 1549 1550/* ------------------------------ */ 1551 .balign 128 1552.L_op_if_ltz: /* 0x3a */ 1553/* File: arm64/op_if_ltz.S */ 1554/* File: arm64/zcmp.S */ 1555 /* 1556 * Generic one-operand compare-and-branch operation. Provide a "condition" 1557 * fragment that specifies the comparison to perform. 1558 * 1559 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1560 */ 1561 /* if-cmp vAA, +BBBB */ 1562 lsr w0, wINST, #8 // w0<- AA 1563 GET_VREG w2, w0 // w2<- vAA 1564 FETCH_S wINST, 1 // w1<- branch offset, in code units 1565 .if 0 1566 cmp w2, #0 // compare (vA, 0) 1567 .endif 1568 tbnz w2, #31, MterpCommonTakenBranchNoFlags 1569 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 1570 b.eq .L_check_not_taken_osr 1571 FETCH_ADVANCE_INST 2 1572 GET_INST_OPCODE ip // extract opcode from wINST 1573 GOTO_OPCODE ip // jump to next instruction 1574 1575 1576/* ------------------------------ */ 1577 .balign 128 1578.L_op_if_gez: /* 0x3b */ 1579/* File: arm64/op_if_gez.S */ 1580/* File: arm64/zcmp.S */ 1581 /* 1582 * Generic one-operand compare-and-branch operation. Provide a "condition" 1583 * fragment that specifies the comparison to perform. 1584 * 1585 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1586 */ 1587 /* if-cmp vAA, +BBBB */ 1588 lsr w0, wINST, #8 // w0<- AA 1589 GET_VREG w2, w0 // w2<- vAA 1590 FETCH_S wINST, 1 // w1<- branch offset, in code units 1591 .if 0 1592 cmp w2, #0 // compare (vA, 0) 1593 .endif 1594 tbz w2, #31, MterpCommonTakenBranchNoFlags 1595 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 1596 b.eq .L_check_not_taken_osr 1597 FETCH_ADVANCE_INST 2 1598 GET_INST_OPCODE ip // extract opcode from wINST 1599 GOTO_OPCODE ip // jump to next instruction 1600 1601 1602/* ------------------------------ */ 1603 .balign 128 1604.L_op_if_gtz: /* 0x3c */ 1605/* File: arm64/op_if_gtz.S */ 1606/* File: arm64/zcmp.S */ 1607 /* 1608 * Generic one-operand compare-and-branch operation. Provide a "condition" 1609 * fragment that specifies the comparison to perform. 1610 * 1611 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1612 */ 1613 /* if-cmp vAA, +BBBB */ 1614 lsr w0, wINST, #8 // w0<- AA 1615 GET_VREG w2, w0 // w2<- vAA 1616 FETCH_S wINST, 1 // w1<- branch offset, in code units 1617 .if 1 1618 cmp w2, #0 // compare (vA, 0) 1619 .endif 1620 b.gt MterpCommonTakenBranchNoFlags 1621 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 1622 b.eq .L_check_not_taken_osr 1623 FETCH_ADVANCE_INST 2 1624 GET_INST_OPCODE ip // extract opcode from wINST 1625 GOTO_OPCODE ip // jump to next instruction 1626 1627 1628/* ------------------------------ */ 1629 .balign 128 1630.L_op_if_lez: /* 0x3d */ 1631/* File: arm64/op_if_lez.S */ 1632/* File: arm64/zcmp.S */ 1633 /* 1634 * Generic one-operand compare-and-branch operation. Provide a "condition" 1635 * fragment that specifies the comparison to perform. 1636 * 1637 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1638 */ 1639 /* if-cmp vAA, +BBBB */ 1640 lsr w0, wINST, #8 // w0<- AA 1641 GET_VREG w2, w0 // w2<- vAA 1642 FETCH_S wINST, 1 // w1<- branch offset, in code units 1643 .if 1 1644 cmp w2, #0 // compare (vA, 0) 1645 .endif 1646 b.le MterpCommonTakenBranchNoFlags 1647 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 1648 b.eq .L_check_not_taken_osr 1649 FETCH_ADVANCE_INST 2 1650 GET_INST_OPCODE ip // extract opcode from wINST 1651 GOTO_OPCODE ip // jump to next instruction 1652 1653 1654/* ------------------------------ */ 1655 .balign 128 1656.L_op_unused_3e: /* 0x3e */ 1657/* File: arm64/op_unused_3e.S */ 1658/* File: arm64/unused.S */ 1659/* 1660 * Bail to reference interpreter to throw. 1661 */ 1662 b MterpFallback 1663 1664 1665/* ------------------------------ */ 1666 .balign 128 1667.L_op_unused_3f: /* 0x3f */ 1668/* File: arm64/op_unused_3f.S */ 1669/* File: arm64/unused.S */ 1670/* 1671 * Bail to reference interpreter to throw. 1672 */ 1673 b MterpFallback 1674 1675 1676/* ------------------------------ */ 1677 .balign 128 1678.L_op_unused_40: /* 0x40 */ 1679/* File: arm64/op_unused_40.S */ 1680/* File: arm64/unused.S */ 1681/* 1682 * Bail to reference interpreter to throw. 1683 */ 1684 b MterpFallback 1685 1686 1687/* ------------------------------ */ 1688 .balign 128 1689.L_op_unused_41: /* 0x41 */ 1690/* File: arm64/op_unused_41.S */ 1691/* File: arm64/unused.S */ 1692/* 1693 * Bail to reference interpreter to throw. 1694 */ 1695 b MterpFallback 1696 1697 1698/* ------------------------------ */ 1699 .balign 128 1700.L_op_unused_42: /* 0x42 */ 1701/* File: arm64/op_unused_42.S */ 1702/* File: arm64/unused.S */ 1703/* 1704 * Bail to reference interpreter to throw. 1705 */ 1706 b MterpFallback 1707 1708 1709/* ------------------------------ */ 1710 .balign 128 1711.L_op_unused_43: /* 0x43 */ 1712/* File: arm64/op_unused_43.S */ 1713/* File: arm64/unused.S */ 1714/* 1715 * Bail to reference interpreter to throw. 1716 */ 1717 b MterpFallback 1718 1719 1720/* ------------------------------ */ 1721 .balign 128 1722.L_op_aget: /* 0x44 */ 1723/* File: arm64/op_aget.S */ 1724 /* 1725 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1726 * 1727 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1728 * instructions. We use a pair of FETCH_Bs instead. 1729 * 1730 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1731 * 1732 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1733 * If this changes, specialize. 1734 */ 1735 /* op vAA, vBB, vCC */ 1736 FETCH_B w2, 1, 0 // w2<- BB 1737 lsr w9, wINST, #8 // w9<- AA 1738 FETCH_B w3, 1, 1 // w3<- CC 1739 GET_VREG w0, w2 // w0<- vBB (array object) 1740 GET_VREG w1, w3 // w1<- vCC (requested index) 1741 cbz x0, common_errNullObject // bail if null array object. 1742 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length 1743 add x0, x0, w1, uxtw #2 // w0<- arrayObj + index*width 1744 cmp w1, w3 // compare unsigned index, length 1745 bcs common_errArrayIndex // index >= length, bail 1746 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 1747 ldr w2, [x0, #MIRROR_INT_ARRAY_DATA_OFFSET] // w2<- vBB[vCC] 1748 GET_INST_OPCODE ip // extract opcode from rINST 1749 SET_VREG w2, w9 // vAA<- w2 1750 GOTO_OPCODE ip // jump to next instruction 1751 1752/* ------------------------------ */ 1753 .balign 128 1754.L_op_aget_wide: /* 0x45 */ 1755/* File: arm64/op_aget_wide.S */ 1756 /* 1757 * Array get, 64 bits. vAA <- vBB[vCC]. 1758 * 1759 */ 1760 /* aget-wide vAA, vBB, vCC */ 1761 FETCH w0, 1 // w0<- CCBB 1762 lsr w4, wINST, #8 // w4<- AA 1763 and w2, w0, #255 // w2<- BB 1764 lsr w3, w0, #8 // w3<- CC 1765 GET_VREG w0, w2 // w0<- vBB (array object) 1766 GET_VREG w1, w3 // w1<- vCC (requested index) 1767 cbz w0, common_errNullObject // yes, bail 1768 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length 1769 add x0, x0, w1, lsl #3 // w0<- arrayObj + index*width 1770 cmp w1, w3 // compare unsigned index, length 1771 bcs common_errArrayIndex // index >= length, bail 1772 FETCH_ADVANCE_INST 2 // advance rPC, load wINST 1773 ldr x2, [x0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] // x2<- vBB[vCC] 1774 GET_INST_OPCODE ip // extract opcode from wINST 1775 SET_VREG_WIDE x2, w4 1776 GOTO_OPCODE ip // jump to next instruction 1777 1778/* ------------------------------ */ 1779 .balign 128 1780.L_op_aget_object: /* 0x46 */ 1781/* File: arm64/op_aget_object.S */ 1782 /* 1783 * Array object get. vAA <- vBB[vCC]. 1784 * 1785 * for: aget-object 1786 */ 1787 /* op vAA, vBB, vCC */ 1788 FETCH_B w2, 1, 0 // w2<- BB 1789 FETCH_B w3, 1, 1 // w3<- CC 1790 EXPORT_PC 1791 GET_VREG w0, w2 // w0<- vBB (array object) 1792 GET_VREG w1, w3 // w1<- vCC (requested index) 1793 bl artAGetObjectFromMterp // (array, index) 1794 ldr x1, [xSELF, #THREAD_EXCEPTION_OFFSET] 1795 lsr w2, wINST, #8 // w9<- AA 1796 PREFETCH_INST 2 1797 cbnz w1, MterpException 1798 SET_VREG_OBJECT w0, w2 1799 ADVANCE 2 1800 GET_INST_OPCODE ip 1801 GOTO_OPCODE ip // jump to next instruction 1802 1803/* ------------------------------ */ 1804 .balign 128 1805.L_op_aget_boolean: /* 0x47 */ 1806/* File: arm64/op_aget_boolean.S */ 1807/* File: arm64/op_aget.S */ 1808 /* 1809 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1810 * 1811 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1812 * instructions. We use a pair of FETCH_Bs instead. 1813 * 1814 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1815 * 1816 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1817 * If this changes, specialize. 1818 */ 1819 /* op vAA, vBB, vCC */ 1820 FETCH_B w2, 1, 0 // w2<- BB 1821 lsr w9, wINST, #8 // w9<- AA 1822 FETCH_B w3, 1, 1 // w3<- CC 1823 GET_VREG w0, w2 // w0<- vBB (array object) 1824 GET_VREG w1, w3 // w1<- vCC (requested index) 1825 cbz x0, common_errNullObject // bail if null array object. 1826 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length 1827 add x0, x0, w1, uxtw #0 // w0<- arrayObj + index*width 1828 cmp w1, w3 // compare unsigned index, length 1829 bcs common_errArrayIndex // index >= length, bail 1830 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 1831 ldrb w2, [x0, #MIRROR_BOOLEAN_ARRAY_DATA_OFFSET] // w2<- vBB[vCC] 1832 GET_INST_OPCODE ip // extract opcode from rINST 1833 SET_VREG w2, w9 // vAA<- w2 1834 GOTO_OPCODE ip // jump to next instruction 1835 1836 1837/* ------------------------------ */ 1838 .balign 128 1839.L_op_aget_byte: /* 0x48 */ 1840/* File: arm64/op_aget_byte.S */ 1841/* File: arm64/op_aget.S */ 1842 /* 1843 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1844 * 1845 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1846 * instructions. We use a pair of FETCH_Bs instead. 1847 * 1848 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1849 * 1850 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1851 * If this changes, specialize. 1852 */ 1853 /* op vAA, vBB, vCC */ 1854 FETCH_B w2, 1, 0 // w2<- BB 1855 lsr w9, wINST, #8 // w9<- AA 1856 FETCH_B w3, 1, 1 // w3<- CC 1857 GET_VREG w0, w2 // w0<- vBB (array object) 1858 GET_VREG w1, w3 // w1<- vCC (requested index) 1859 cbz x0, common_errNullObject // bail if null array object. 1860 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length 1861 add x0, x0, w1, uxtw #0 // w0<- arrayObj + index*width 1862 cmp w1, w3 // compare unsigned index, length 1863 bcs common_errArrayIndex // index >= length, bail 1864 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 1865 ldrsb w2, [x0, #MIRROR_BYTE_ARRAY_DATA_OFFSET] // w2<- vBB[vCC] 1866 GET_INST_OPCODE ip // extract opcode from rINST 1867 SET_VREG w2, w9 // vAA<- w2 1868 GOTO_OPCODE ip // jump to next instruction 1869 1870 1871/* ------------------------------ */ 1872 .balign 128 1873.L_op_aget_char: /* 0x49 */ 1874/* File: arm64/op_aget_char.S */ 1875/* File: arm64/op_aget.S */ 1876 /* 1877 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1878 * 1879 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1880 * instructions. We use a pair of FETCH_Bs instead. 1881 * 1882 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1883 * 1884 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1885 * If this changes, specialize. 1886 */ 1887 /* op vAA, vBB, vCC */ 1888 FETCH_B w2, 1, 0 // w2<- BB 1889 lsr w9, wINST, #8 // w9<- AA 1890 FETCH_B w3, 1, 1 // w3<- CC 1891 GET_VREG w0, w2 // w0<- vBB (array object) 1892 GET_VREG w1, w3 // w1<- vCC (requested index) 1893 cbz x0, common_errNullObject // bail if null array object. 1894 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length 1895 add x0, x0, w1, uxtw #1 // w0<- arrayObj + index*width 1896 cmp w1, w3 // compare unsigned index, length 1897 bcs common_errArrayIndex // index >= length, bail 1898 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 1899 ldrh w2, [x0, #MIRROR_CHAR_ARRAY_DATA_OFFSET] // w2<- vBB[vCC] 1900 GET_INST_OPCODE ip // extract opcode from rINST 1901 SET_VREG w2, w9 // vAA<- w2 1902 GOTO_OPCODE ip // jump to next instruction 1903 1904 1905/* ------------------------------ */ 1906 .balign 128 1907.L_op_aget_short: /* 0x4a */ 1908/* File: arm64/op_aget_short.S */ 1909/* File: arm64/op_aget.S */ 1910 /* 1911 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1912 * 1913 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1914 * instructions. We use a pair of FETCH_Bs instead. 1915 * 1916 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1917 * 1918 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1919 * If this changes, specialize. 1920 */ 1921 /* op vAA, vBB, vCC */ 1922 FETCH_B w2, 1, 0 // w2<- BB 1923 lsr w9, wINST, #8 // w9<- AA 1924 FETCH_B w3, 1, 1 // w3<- CC 1925 GET_VREG w0, w2 // w0<- vBB (array object) 1926 GET_VREG w1, w3 // w1<- vCC (requested index) 1927 cbz x0, common_errNullObject // bail if null array object. 1928 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length 1929 add x0, x0, w1, uxtw #1 // w0<- arrayObj + index*width 1930 cmp w1, w3 // compare unsigned index, length 1931 bcs common_errArrayIndex // index >= length, bail 1932 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 1933 ldrsh w2, [x0, #MIRROR_SHORT_ARRAY_DATA_OFFSET] // w2<- vBB[vCC] 1934 GET_INST_OPCODE ip // extract opcode from rINST 1935 SET_VREG w2, w9 // vAA<- w2 1936 GOTO_OPCODE ip // jump to next instruction 1937 1938 1939/* ------------------------------ */ 1940 .balign 128 1941.L_op_aput: /* 0x4b */ 1942/* File: arm64/op_aput.S */ 1943 /* 1944 * Array put, 32 bits or less. vBB[vCC] <- vAA. 1945 * 1946 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1947 * instructions. We use a pair of FETCH_Bs instead. 1948 * 1949 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 1950 * 1951 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 1952 * If this changes, specialize. 1953 */ 1954 /* op vAA, vBB, vCC */ 1955 FETCH_B w2, 1, 0 // w2<- BB 1956 lsr w9, wINST, #8 // w9<- AA 1957 FETCH_B w3, 1, 1 // w3<- CC 1958 GET_VREG w0, w2 // w0<- vBB (array object) 1959 GET_VREG w1, w3 // w1<- vCC (requested index) 1960 cbz w0, common_errNullObject // bail if null 1961 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length 1962 add x0, x0, w1, lsl #2 // w0<- arrayObj + index*width 1963 cmp w1, w3 // compare unsigned index, length 1964 bcs common_errArrayIndex // index >= length, bail 1965 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 1966 GET_VREG w2, w9 // w2<- vAA 1967 GET_INST_OPCODE ip // extract opcode from rINST 1968 str w2, [x0, #MIRROR_INT_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2 1969 GOTO_OPCODE ip // jump to next instruction 1970 1971/* ------------------------------ */ 1972 .balign 128 1973.L_op_aput_wide: /* 0x4c */ 1974/* File: arm64/op_aput_wide.S */ 1975 /* 1976 * Array put, 64 bits. vBB[vCC] <- vAA. 1977 * 1978 */ 1979 /* aput-wide vAA, vBB, vCC */ 1980 FETCH w0, 1 // w0<- CCBB 1981 lsr w4, wINST, #8 // w4<- AA 1982 and w2, w0, #255 // w2<- BB 1983 lsr w3, w0, #8 // w3<- CC 1984 GET_VREG w0, w2 // w0<- vBB (array object) 1985 GET_VREG w1, w3 // w1<- vCC (requested index) 1986 cbz w0, common_errNullObject // bail if null 1987 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length 1988 add x0, x0, w1, lsl #3 // w0<- arrayObj + index*width 1989 cmp w1, w3 // compare unsigned index, length 1990 bcs common_errArrayIndex // index >= length, bail 1991 GET_VREG_WIDE x1, w4 1992 FETCH_ADVANCE_INST 2 // advance rPC, load wINST 1993 GET_INST_OPCODE ip // extract opcode from wINST 1994 str x1, [x0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] 1995 GOTO_OPCODE ip // jump to next instruction 1996 1997/* ------------------------------ */ 1998 .balign 128 1999.L_op_aput_object: /* 0x4d */ 2000/* File: arm64/op_aput_object.S */ 2001 /* 2002 * Store an object into an array. vBB[vCC] <- vAA. 2003 */ 2004 /* op vAA, vBB, vCC */ 2005 EXPORT_PC 2006 add x0, xFP, #OFF_FP_SHADOWFRAME 2007 mov x1, xPC 2008 mov w2, wINST 2009 bl MterpAputObject 2010 cbz w0, MterpPossibleException 2011 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 2012 GET_INST_OPCODE ip // extract opcode from rINST 2013 GOTO_OPCODE ip // jump to next instruction 2014 2015/* ------------------------------ */ 2016 .balign 128 2017.L_op_aput_boolean: /* 0x4e */ 2018/* File: arm64/op_aput_boolean.S */ 2019/* File: arm64/op_aput.S */ 2020 /* 2021 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2022 * 2023 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2024 * instructions. We use a pair of FETCH_Bs instead. 2025 * 2026 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2027 * 2028 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2029 * If this changes, specialize. 2030 */ 2031 /* op vAA, vBB, vCC */ 2032 FETCH_B w2, 1, 0 // w2<- BB 2033 lsr w9, wINST, #8 // w9<- AA 2034 FETCH_B w3, 1, 1 // w3<- CC 2035 GET_VREG w0, w2 // w0<- vBB (array object) 2036 GET_VREG w1, w3 // w1<- vCC (requested index) 2037 cbz w0, common_errNullObject // bail if null 2038 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length 2039 add x0, x0, w1, lsl #0 // w0<- arrayObj + index*width 2040 cmp w1, w3 // compare unsigned index, length 2041 bcs common_errArrayIndex // index >= length, bail 2042 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 2043 GET_VREG w2, w9 // w2<- vAA 2044 GET_INST_OPCODE ip // extract opcode from rINST 2045 strb w2, [x0, #MIRROR_BOOLEAN_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2 2046 GOTO_OPCODE ip // jump to next instruction 2047 2048 2049/* ------------------------------ */ 2050 .balign 128 2051.L_op_aput_byte: /* 0x4f */ 2052/* File: arm64/op_aput_byte.S */ 2053/* File: arm64/op_aput.S */ 2054 /* 2055 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2056 * 2057 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2058 * instructions. We use a pair of FETCH_Bs instead. 2059 * 2060 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2061 * 2062 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2063 * If this changes, specialize. 2064 */ 2065 /* op vAA, vBB, vCC */ 2066 FETCH_B w2, 1, 0 // w2<- BB 2067 lsr w9, wINST, #8 // w9<- AA 2068 FETCH_B w3, 1, 1 // w3<- CC 2069 GET_VREG w0, w2 // w0<- vBB (array object) 2070 GET_VREG w1, w3 // w1<- vCC (requested index) 2071 cbz w0, common_errNullObject // bail if null 2072 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length 2073 add x0, x0, w1, lsl #0 // w0<- arrayObj + index*width 2074 cmp w1, w3 // compare unsigned index, length 2075 bcs common_errArrayIndex // index >= length, bail 2076 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 2077 GET_VREG w2, w9 // w2<- vAA 2078 GET_INST_OPCODE ip // extract opcode from rINST 2079 strb w2, [x0, #MIRROR_BYTE_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2 2080 GOTO_OPCODE ip // jump to next instruction 2081 2082 2083/* ------------------------------ */ 2084 .balign 128 2085.L_op_aput_char: /* 0x50 */ 2086/* File: arm64/op_aput_char.S */ 2087/* File: arm64/op_aput.S */ 2088 /* 2089 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2090 * 2091 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2092 * instructions. We use a pair of FETCH_Bs instead. 2093 * 2094 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2095 * 2096 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2097 * If this changes, specialize. 2098 */ 2099 /* op vAA, vBB, vCC */ 2100 FETCH_B w2, 1, 0 // w2<- BB 2101 lsr w9, wINST, #8 // w9<- AA 2102 FETCH_B w3, 1, 1 // w3<- CC 2103 GET_VREG w0, w2 // w0<- vBB (array object) 2104 GET_VREG w1, w3 // w1<- vCC (requested index) 2105 cbz w0, common_errNullObject // bail if null 2106 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length 2107 add x0, x0, w1, lsl #1 // w0<- arrayObj + index*width 2108 cmp w1, w3 // compare unsigned index, length 2109 bcs common_errArrayIndex // index >= length, bail 2110 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 2111 GET_VREG w2, w9 // w2<- vAA 2112 GET_INST_OPCODE ip // extract opcode from rINST 2113 strh w2, [x0, #MIRROR_CHAR_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2 2114 GOTO_OPCODE ip // jump to next instruction 2115 2116 2117/* ------------------------------ */ 2118 .balign 128 2119.L_op_aput_short: /* 0x51 */ 2120/* File: arm64/op_aput_short.S */ 2121/* File: arm64/op_aput.S */ 2122 /* 2123 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2124 * 2125 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2126 * instructions. We use a pair of FETCH_Bs instead. 2127 * 2128 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2129 * 2130 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2131 * If this changes, specialize. 2132 */ 2133 /* op vAA, vBB, vCC */ 2134 FETCH_B w2, 1, 0 // w2<- BB 2135 lsr w9, wINST, #8 // w9<- AA 2136 FETCH_B w3, 1, 1 // w3<- CC 2137 GET_VREG w0, w2 // w0<- vBB (array object) 2138 GET_VREG w1, w3 // w1<- vCC (requested index) 2139 cbz w0, common_errNullObject // bail if null 2140 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length 2141 add x0, x0, w1, lsl #1 // w0<- arrayObj + index*width 2142 cmp w1, w3 // compare unsigned index, length 2143 bcs common_errArrayIndex // index >= length, bail 2144 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 2145 GET_VREG w2, w9 // w2<- vAA 2146 GET_INST_OPCODE ip // extract opcode from rINST 2147 strh w2, [x0, #MIRROR_SHORT_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2 2148 GOTO_OPCODE ip // jump to next instruction 2149 2150 2151/* ------------------------------ */ 2152 .balign 128 2153.L_op_iget: /* 0x52 */ 2154/* File: arm64/op_iget.S */ 2155 /* 2156 * General instance field get. 2157 * 2158 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2159 */ 2160 EXPORT_PC 2161 FETCH w0, 1 // w0<- field ref CCCC 2162 lsr w1, wINST, #12 // w1<- B 2163 GET_VREG w1, w1 // w1<- fp[B], the object pointer 2164 ldr x2, [xFP, #OFF_FP_METHOD] // w2<- referrer 2165 mov x3, xSELF // w3<- self 2166 bl artGet32InstanceFromCode 2167 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2168 2169 ubfx w2, wINST, #8, #4 // w2<- A 2170 PREFETCH_INST 2 2171 cbnz x3, MterpPossibleException // bail out 2172 .if 0 2173 SET_VREG_OBJECT w0, w2 // fp[A]<- w0 2174 .else 2175 SET_VREG w0, w2 // fp[A]<- w0 2176 .endif 2177 ADVANCE 2 2178 GET_INST_OPCODE ip // extract opcode from rINST 2179 GOTO_OPCODE ip // jump to next instruction 2180 2181/* ------------------------------ */ 2182 .balign 128 2183.L_op_iget_wide: /* 0x53 */ 2184/* File: arm64/op_iget_wide.S */ 2185 /* 2186 * 64-bit instance field get. 2187 * 2188 * for: iget-wide 2189 */ 2190 EXPORT_PC 2191 FETCH w0, 1 // w0<- field ref CCCC 2192 lsr w1, wINST, #12 // w1<- B 2193 GET_VREG w1, w1 // w1<- fp[B], the object pointer 2194 ldr x2, [xFP, #OFF_FP_METHOD] // w2<- referrer 2195 mov x3, xSELF // w3<- self 2196 bl artGet64InstanceFromCode 2197 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2198 ubfx w2, wINST, #8, #4 // w2<- A 2199 PREFETCH_INST 2 2200 cmp w3, #0 2201 cbnz w3, MterpException // bail out 2202 SET_VREG_WIDE x0, w2 2203 ADVANCE 2 2204 GET_INST_OPCODE ip // extract opcode from wINST 2205 GOTO_OPCODE ip // jump to next instruction 2206 2207/* ------------------------------ */ 2208 .balign 128 2209.L_op_iget_object: /* 0x54 */ 2210/* File: arm64/op_iget_object.S */ 2211/* File: arm64/op_iget.S */ 2212 /* 2213 * General instance field get. 2214 * 2215 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2216 */ 2217 EXPORT_PC 2218 FETCH w0, 1 // w0<- field ref CCCC 2219 lsr w1, wINST, #12 // w1<- B 2220 GET_VREG w1, w1 // w1<- fp[B], the object pointer 2221 ldr x2, [xFP, #OFF_FP_METHOD] // w2<- referrer 2222 mov x3, xSELF // w3<- self 2223 bl artGetObjInstanceFromCode 2224 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2225 2226 ubfx w2, wINST, #8, #4 // w2<- A 2227 PREFETCH_INST 2 2228 cbnz x3, MterpPossibleException // bail out 2229 .if 1 2230 SET_VREG_OBJECT w0, w2 // fp[A]<- w0 2231 .else 2232 SET_VREG w0, w2 // fp[A]<- w0 2233 .endif 2234 ADVANCE 2 2235 GET_INST_OPCODE ip // extract opcode from rINST 2236 GOTO_OPCODE ip // jump to next instruction 2237 2238 2239/* ------------------------------ */ 2240 .balign 128 2241.L_op_iget_boolean: /* 0x55 */ 2242/* File: arm64/op_iget_boolean.S */ 2243/* File: arm64/op_iget.S */ 2244 /* 2245 * General instance field get. 2246 * 2247 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2248 */ 2249 EXPORT_PC 2250 FETCH w0, 1 // w0<- field ref CCCC 2251 lsr w1, wINST, #12 // w1<- B 2252 GET_VREG w1, w1 // w1<- fp[B], the object pointer 2253 ldr x2, [xFP, #OFF_FP_METHOD] // w2<- referrer 2254 mov x3, xSELF // w3<- self 2255 bl artGetBooleanInstanceFromCode 2256 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2257 uxtb w0, w0 2258 ubfx w2, wINST, #8, #4 // w2<- A 2259 PREFETCH_INST 2 2260 cbnz x3, MterpPossibleException // bail out 2261 .if 0 2262 SET_VREG_OBJECT w0, w2 // fp[A]<- w0 2263 .else 2264 SET_VREG w0, w2 // fp[A]<- w0 2265 .endif 2266 ADVANCE 2 2267 GET_INST_OPCODE ip // extract opcode from rINST 2268 GOTO_OPCODE ip // jump to next instruction 2269 2270 2271/* ------------------------------ */ 2272 .balign 128 2273.L_op_iget_byte: /* 0x56 */ 2274/* File: arm64/op_iget_byte.S */ 2275/* File: arm64/op_iget.S */ 2276 /* 2277 * General instance field get. 2278 * 2279 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2280 */ 2281 EXPORT_PC 2282 FETCH w0, 1 // w0<- field ref CCCC 2283 lsr w1, wINST, #12 // w1<- B 2284 GET_VREG w1, w1 // w1<- fp[B], the object pointer 2285 ldr x2, [xFP, #OFF_FP_METHOD] // w2<- referrer 2286 mov x3, xSELF // w3<- self 2287 bl artGetByteInstanceFromCode 2288 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2289 sxtb w0, w0 2290 ubfx w2, wINST, #8, #4 // w2<- A 2291 PREFETCH_INST 2 2292 cbnz x3, MterpPossibleException // bail out 2293 .if 0 2294 SET_VREG_OBJECT w0, w2 // fp[A]<- w0 2295 .else 2296 SET_VREG w0, w2 // fp[A]<- w0 2297 .endif 2298 ADVANCE 2 2299 GET_INST_OPCODE ip // extract opcode from rINST 2300 GOTO_OPCODE ip // jump to next instruction 2301 2302 2303/* ------------------------------ */ 2304 .balign 128 2305.L_op_iget_char: /* 0x57 */ 2306/* File: arm64/op_iget_char.S */ 2307/* File: arm64/op_iget.S */ 2308 /* 2309 * General instance field get. 2310 * 2311 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2312 */ 2313 EXPORT_PC 2314 FETCH w0, 1 // w0<- field ref CCCC 2315 lsr w1, wINST, #12 // w1<- B 2316 GET_VREG w1, w1 // w1<- fp[B], the object pointer 2317 ldr x2, [xFP, #OFF_FP_METHOD] // w2<- referrer 2318 mov x3, xSELF // w3<- self 2319 bl artGetCharInstanceFromCode 2320 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2321 uxth w0, w0 2322 ubfx w2, wINST, #8, #4 // w2<- A 2323 PREFETCH_INST 2 2324 cbnz x3, MterpPossibleException // bail out 2325 .if 0 2326 SET_VREG_OBJECT w0, w2 // fp[A]<- w0 2327 .else 2328 SET_VREG w0, w2 // fp[A]<- w0 2329 .endif 2330 ADVANCE 2 2331 GET_INST_OPCODE ip // extract opcode from rINST 2332 GOTO_OPCODE ip // jump to next instruction 2333 2334 2335/* ------------------------------ */ 2336 .balign 128 2337.L_op_iget_short: /* 0x58 */ 2338/* File: arm64/op_iget_short.S */ 2339/* File: arm64/op_iget.S */ 2340 /* 2341 * General instance field get. 2342 * 2343 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2344 */ 2345 EXPORT_PC 2346 FETCH w0, 1 // w0<- field ref CCCC 2347 lsr w1, wINST, #12 // w1<- B 2348 GET_VREG w1, w1 // w1<- fp[B], the object pointer 2349 ldr x2, [xFP, #OFF_FP_METHOD] // w2<- referrer 2350 mov x3, xSELF // w3<- self 2351 bl artGetShortInstanceFromCode 2352 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2353 sxth w0, w0 2354 ubfx w2, wINST, #8, #4 // w2<- A 2355 PREFETCH_INST 2 2356 cbnz x3, MterpPossibleException // bail out 2357 .if 0 2358 SET_VREG_OBJECT w0, w2 // fp[A]<- w0 2359 .else 2360 SET_VREG w0, w2 // fp[A]<- w0 2361 .endif 2362 ADVANCE 2 2363 GET_INST_OPCODE ip // extract opcode from rINST 2364 GOTO_OPCODE ip // jump to next instruction 2365 2366 2367/* ------------------------------ */ 2368 .balign 128 2369.L_op_iput: /* 0x59 */ 2370/* File: arm64/op_iput.S */ 2371 /* 2372 * General 32-bit instance field put. 2373 * 2374 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2375 */ 2376 /* op vA, vB, field//CCCC */ 2377 .extern artSet32InstanceFromMterp 2378 EXPORT_PC 2379 FETCH w0, 1 // w0<- field ref CCCC 2380 lsr w1, wINST, #12 // w1<- B 2381 GET_VREG w1, w1 // w1<- fp[B], the object pointer 2382 ubfx w2, wINST, #8, #4 // w2<- A 2383 GET_VREG w2, w2 // w2<- fp[A] 2384 ldr x3, [xFP, #OFF_FP_METHOD] // w3<- referrer 2385 PREFETCH_INST 2 2386 bl artSet32InstanceFromMterp 2387 cbnz w0, MterpPossibleException 2388 ADVANCE 2 // advance rPC 2389 GET_INST_OPCODE ip // extract opcode from rINST 2390 GOTO_OPCODE ip // jump to next instruction 2391 2392/* ------------------------------ */ 2393 .balign 128 2394.L_op_iput_wide: /* 0x5a */ 2395/* File: arm64/op_iput_wide.S */ 2396 /* iput-wide vA, vB, field//CCCC */ 2397 .extern artSet64InstanceFromMterp 2398 EXPORT_PC 2399 FETCH w0, 1 // w0<- field ref CCCC 2400 lsr w1, wINST, #12 // w1<- B 2401 GET_VREG w1, w1 // w1<- fp[B], the object pointer 2402 ubfx w2, wINST, #8, #4 // w2<- A 2403 VREG_INDEX_TO_ADDR x2, x2 // w2<- &fp[A] 2404 ldr x3, [xFP, #OFF_FP_METHOD] // w3<- referrer 2405 PREFETCH_INST 2 2406 bl artSet64InstanceFromMterp 2407 cbnz w0, MterpPossibleException 2408 ADVANCE 2 // advance rPC 2409 GET_INST_OPCODE ip // extract opcode from wINST 2410 GOTO_OPCODE ip // jump to next instruction 2411 2412/* ------------------------------ */ 2413 .balign 128 2414.L_op_iput_object: /* 0x5b */ 2415/* File: arm64/op_iput_object.S */ 2416 EXPORT_PC 2417 add x0, xFP, #OFF_FP_SHADOWFRAME 2418 mov x1, xPC 2419 mov w2, wINST 2420 mov x3, xSELF 2421 bl MterpIputObject 2422 cbz w0, MterpException 2423 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 2424 GET_INST_OPCODE ip // extract opcode from rINST 2425 GOTO_OPCODE ip // jump to next instruction 2426 2427/* ------------------------------ */ 2428 .balign 128 2429.L_op_iput_boolean: /* 0x5c */ 2430/* File: arm64/op_iput_boolean.S */ 2431/* File: arm64/op_iput.S */ 2432 /* 2433 * General 32-bit instance field put. 2434 * 2435 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2436 */ 2437 /* op vA, vB, field//CCCC */ 2438 .extern artSet8InstanceFromMterp 2439 EXPORT_PC 2440 FETCH w0, 1 // w0<- field ref CCCC 2441 lsr w1, wINST, #12 // w1<- B 2442 GET_VREG w1, w1 // w1<- fp[B], the object pointer 2443 ubfx w2, wINST, #8, #4 // w2<- A 2444 GET_VREG w2, w2 // w2<- fp[A] 2445 ldr x3, [xFP, #OFF_FP_METHOD] // w3<- referrer 2446 PREFETCH_INST 2 2447 bl artSet8InstanceFromMterp 2448 cbnz w0, MterpPossibleException 2449 ADVANCE 2 // advance rPC 2450 GET_INST_OPCODE ip // extract opcode from rINST 2451 GOTO_OPCODE ip // jump to next instruction 2452 2453 2454/* ------------------------------ */ 2455 .balign 128 2456.L_op_iput_byte: /* 0x5d */ 2457/* File: arm64/op_iput_byte.S */ 2458/* File: arm64/op_iput.S */ 2459 /* 2460 * General 32-bit instance field put. 2461 * 2462 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2463 */ 2464 /* op vA, vB, field//CCCC */ 2465 .extern artSet8InstanceFromMterp 2466 EXPORT_PC 2467 FETCH w0, 1 // w0<- field ref CCCC 2468 lsr w1, wINST, #12 // w1<- B 2469 GET_VREG w1, w1 // w1<- fp[B], the object pointer 2470 ubfx w2, wINST, #8, #4 // w2<- A 2471 GET_VREG w2, w2 // w2<- fp[A] 2472 ldr x3, [xFP, #OFF_FP_METHOD] // w3<- referrer 2473 PREFETCH_INST 2 2474 bl artSet8InstanceFromMterp 2475 cbnz w0, MterpPossibleException 2476 ADVANCE 2 // advance rPC 2477 GET_INST_OPCODE ip // extract opcode from rINST 2478 GOTO_OPCODE ip // jump to next instruction 2479 2480 2481/* ------------------------------ */ 2482 .balign 128 2483.L_op_iput_char: /* 0x5e */ 2484/* File: arm64/op_iput_char.S */ 2485/* File: arm64/op_iput.S */ 2486 /* 2487 * General 32-bit instance field put. 2488 * 2489 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2490 */ 2491 /* op vA, vB, field//CCCC */ 2492 .extern artSet16InstanceFromMterp 2493 EXPORT_PC 2494 FETCH w0, 1 // w0<- field ref CCCC 2495 lsr w1, wINST, #12 // w1<- B 2496 GET_VREG w1, w1 // w1<- fp[B], the object pointer 2497 ubfx w2, wINST, #8, #4 // w2<- A 2498 GET_VREG w2, w2 // w2<- fp[A] 2499 ldr x3, [xFP, #OFF_FP_METHOD] // w3<- referrer 2500 PREFETCH_INST 2 2501 bl artSet16InstanceFromMterp 2502 cbnz w0, MterpPossibleException 2503 ADVANCE 2 // advance rPC 2504 GET_INST_OPCODE ip // extract opcode from rINST 2505 GOTO_OPCODE ip // jump to next instruction 2506 2507 2508/* ------------------------------ */ 2509 .balign 128 2510.L_op_iput_short: /* 0x5f */ 2511/* File: arm64/op_iput_short.S */ 2512/* File: arm64/op_iput.S */ 2513 /* 2514 * General 32-bit instance field put. 2515 * 2516 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2517 */ 2518 /* op vA, vB, field//CCCC */ 2519 .extern artSet16InstanceFromMterp 2520 EXPORT_PC 2521 FETCH w0, 1 // w0<- field ref CCCC 2522 lsr w1, wINST, #12 // w1<- B 2523 GET_VREG w1, w1 // w1<- fp[B], the object pointer 2524 ubfx w2, wINST, #8, #4 // w2<- A 2525 GET_VREG w2, w2 // w2<- fp[A] 2526 ldr x3, [xFP, #OFF_FP_METHOD] // w3<- referrer 2527 PREFETCH_INST 2 2528 bl artSet16InstanceFromMterp 2529 cbnz w0, MterpPossibleException 2530 ADVANCE 2 // advance rPC 2531 GET_INST_OPCODE ip // extract opcode from rINST 2532 GOTO_OPCODE ip // jump to next instruction 2533 2534 2535/* ------------------------------ */ 2536 .balign 128 2537.L_op_sget: /* 0x60 */ 2538/* File: arm64/op_sget.S */ 2539 /* 2540 * General SGET handler wrapper. 2541 * 2542 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2543 */ 2544 /* op vAA, field//BBBB */ 2545 2546 .extern MterpGet32Static 2547 EXPORT_PC 2548 FETCH w0, 1 // w0<- field ref BBBB 2549 ldr x1, [xFP, #OFF_FP_METHOD] 2550 mov x2, xSELF 2551 bl MterpGet32Static 2552 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2553 lsr w2, wINST, #8 // w2<- AA 2554 2555 PREFETCH_INST 2 2556 cbnz x3, MterpException // bail out 2557.if 0 2558 SET_VREG_OBJECT w0, w2 // fp[AA]<- w0 2559.else 2560 SET_VREG w0, w2 // fp[AA]<- w0 2561.endif 2562 ADVANCE 2 2563 GET_INST_OPCODE ip // extract opcode from rINST 2564 GOTO_OPCODE ip 2565 2566/* ------------------------------ */ 2567 .balign 128 2568.L_op_sget_wide: /* 0x61 */ 2569/* File: arm64/op_sget_wide.S */ 2570 /* 2571 * SGET_WIDE handler wrapper. 2572 * 2573 */ 2574 /* sget-wide vAA, field//BBBB */ 2575 2576 .extern MterpGet64StaticFromCode 2577 EXPORT_PC 2578 FETCH w0, 1 // w0<- field ref BBBB 2579 ldr x1, [xFP, #OFF_FP_METHOD] 2580 mov x2, xSELF 2581 bl MterpGet64Static 2582 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2583 lsr w4, wINST, #8 // w4<- AA 2584 cbnz x3, MterpException // bail out 2585 FETCH_ADVANCE_INST 2 // advance rPC, load wINST 2586 SET_VREG_WIDE x0, w4 2587 GET_INST_OPCODE ip // extract opcode from wINST 2588 GOTO_OPCODE ip // jump to next instruction 2589 2590/* ------------------------------ */ 2591 .balign 128 2592.L_op_sget_object: /* 0x62 */ 2593/* File: arm64/op_sget_object.S */ 2594/* File: arm64/op_sget.S */ 2595 /* 2596 * General SGET handler wrapper. 2597 * 2598 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2599 */ 2600 /* op vAA, field//BBBB */ 2601 2602 .extern MterpGetObjStatic 2603 EXPORT_PC 2604 FETCH w0, 1 // w0<- field ref BBBB 2605 ldr x1, [xFP, #OFF_FP_METHOD] 2606 mov x2, xSELF 2607 bl MterpGetObjStatic 2608 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2609 lsr w2, wINST, #8 // w2<- AA 2610 2611 PREFETCH_INST 2 2612 cbnz x3, MterpException // bail out 2613.if 1 2614 SET_VREG_OBJECT w0, w2 // fp[AA]<- w0 2615.else 2616 SET_VREG w0, w2 // fp[AA]<- w0 2617.endif 2618 ADVANCE 2 2619 GET_INST_OPCODE ip // extract opcode from rINST 2620 GOTO_OPCODE ip 2621 2622 2623/* ------------------------------ */ 2624 .balign 128 2625.L_op_sget_boolean: /* 0x63 */ 2626/* File: arm64/op_sget_boolean.S */ 2627/* File: arm64/op_sget.S */ 2628 /* 2629 * General SGET handler wrapper. 2630 * 2631 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2632 */ 2633 /* op vAA, field//BBBB */ 2634 2635 .extern MterpGetBooleanStatic 2636 EXPORT_PC 2637 FETCH w0, 1 // w0<- field ref BBBB 2638 ldr x1, [xFP, #OFF_FP_METHOD] 2639 mov x2, xSELF 2640 bl MterpGetBooleanStatic 2641 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2642 lsr w2, wINST, #8 // w2<- AA 2643 uxtb w0, w0 2644 PREFETCH_INST 2 2645 cbnz x3, MterpException // bail out 2646.if 0 2647 SET_VREG_OBJECT w0, w2 // fp[AA]<- w0 2648.else 2649 SET_VREG w0, w2 // fp[AA]<- w0 2650.endif 2651 ADVANCE 2 2652 GET_INST_OPCODE ip // extract opcode from rINST 2653 GOTO_OPCODE ip 2654 2655 2656/* ------------------------------ */ 2657 .balign 128 2658.L_op_sget_byte: /* 0x64 */ 2659/* File: arm64/op_sget_byte.S */ 2660/* File: arm64/op_sget.S */ 2661 /* 2662 * General SGET handler wrapper. 2663 * 2664 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2665 */ 2666 /* op vAA, field//BBBB */ 2667 2668 .extern MterpGetByteStatic 2669 EXPORT_PC 2670 FETCH w0, 1 // w0<- field ref BBBB 2671 ldr x1, [xFP, #OFF_FP_METHOD] 2672 mov x2, xSELF 2673 bl MterpGetByteStatic 2674 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2675 lsr w2, wINST, #8 // w2<- AA 2676 sxtb w0, w0 2677 PREFETCH_INST 2 2678 cbnz x3, MterpException // bail out 2679.if 0 2680 SET_VREG_OBJECT w0, w2 // fp[AA]<- w0 2681.else 2682 SET_VREG w0, w2 // fp[AA]<- w0 2683.endif 2684 ADVANCE 2 2685 GET_INST_OPCODE ip // extract opcode from rINST 2686 GOTO_OPCODE ip 2687 2688 2689/* ------------------------------ */ 2690 .balign 128 2691.L_op_sget_char: /* 0x65 */ 2692/* File: arm64/op_sget_char.S */ 2693/* File: arm64/op_sget.S */ 2694 /* 2695 * General SGET handler wrapper. 2696 * 2697 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2698 */ 2699 /* op vAA, field//BBBB */ 2700 2701 .extern MterpGetCharStatic 2702 EXPORT_PC 2703 FETCH w0, 1 // w0<- field ref BBBB 2704 ldr x1, [xFP, #OFF_FP_METHOD] 2705 mov x2, xSELF 2706 bl MterpGetCharStatic 2707 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2708 lsr w2, wINST, #8 // w2<- AA 2709 uxth w0, w0 2710 PREFETCH_INST 2 2711 cbnz x3, MterpException // bail out 2712.if 0 2713 SET_VREG_OBJECT w0, w2 // fp[AA]<- w0 2714.else 2715 SET_VREG w0, w2 // fp[AA]<- w0 2716.endif 2717 ADVANCE 2 2718 GET_INST_OPCODE ip // extract opcode from rINST 2719 GOTO_OPCODE ip 2720 2721 2722/* ------------------------------ */ 2723 .balign 128 2724.L_op_sget_short: /* 0x66 */ 2725/* File: arm64/op_sget_short.S */ 2726/* File: arm64/op_sget.S */ 2727 /* 2728 * General SGET handler wrapper. 2729 * 2730 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2731 */ 2732 /* op vAA, field//BBBB */ 2733 2734 .extern MterpGetShortStatic 2735 EXPORT_PC 2736 FETCH w0, 1 // w0<- field ref BBBB 2737 ldr x1, [xFP, #OFF_FP_METHOD] 2738 mov x2, xSELF 2739 bl MterpGetShortStatic 2740 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2741 lsr w2, wINST, #8 // w2<- AA 2742 sxth w0, w0 2743 PREFETCH_INST 2 2744 cbnz x3, MterpException // bail out 2745.if 0 2746 SET_VREG_OBJECT w0, w2 // fp[AA]<- w0 2747.else 2748 SET_VREG w0, w2 // fp[AA]<- w0 2749.endif 2750 ADVANCE 2 2751 GET_INST_OPCODE ip // extract opcode from rINST 2752 GOTO_OPCODE ip 2753 2754 2755/* ------------------------------ */ 2756 .balign 128 2757.L_op_sput: /* 0x67 */ 2758/* File: arm64/op_sput.S */ 2759 /* 2760 * General SPUT handler wrapper. 2761 * 2762 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2763 */ 2764 /* op vAA, field//BBBB */ 2765 EXPORT_PC 2766 FETCH w0, 1 // r0<- field ref BBBB 2767 lsr w3, wINST, #8 // r3<- AA 2768 GET_VREG w1, w3 // r1<= fp[AA] 2769 ldr x2, [xFP, #OFF_FP_METHOD] 2770 mov x3, xSELF 2771 PREFETCH_INST 2 // Get next inst, but don't advance rPC 2772 bl MterpSet32Static 2773 cbnz w0, MterpException // 0 on success 2774 ADVANCE 2 // Past exception point - now advance rPC 2775 GET_INST_OPCODE ip // extract opcode from rINST 2776 GOTO_OPCODE ip // jump to next instruction 2777 2778/* ------------------------------ */ 2779 .balign 128 2780.L_op_sput_wide: /* 0x68 */ 2781/* File: arm64/op_sput_wide.S */ 2782 /* 2783 * SPUT_WIDE handler wrapper. 2784 * 2785 */ 2786 /* sput-wide vAA, field//BBBB */ 2787 .extern MterpSet64Static 2788 EXPORT_PC 2789 FETCH w0, 1 // w0<- field ref BBBB 2790 lsr w1, wINST, #8 // w1<- AA 2791 VREG_INDEX_TO_ADDR x1, w1 2792 ldr x2, [xFP, #OFF_FP_METHOD] 2793 mov x3, xSELF 2794 PREFETCH_INST 2 // Get next inst, but don't advance rPC 2795 bl MterpSet64Static 2796 cbnz w0, MterpException // 0 on success, -1 on failure 2797 ADVANCE 2 // Past exception point - now advance rPC 2798 GET_INST_OPCODE ip // extract opcode from wINST 2799 GOTO_OPCODE ip // jump to next instruction 2800 2801/* ------------------------------ */ 2802 .balign 128 2803.L_op_sput_object: /* 0x69 */ 2804/* File: arm64/op_sput_object.S */ 2805 EXPORT_PC 2806 add x0, xFP, #OFF_FP_SHADOWFRAME 2807 mov x1, xPC 2808 mov x2, xINST 2809 mov x3, xSELF 2810 bl MterpSputObject 2811 cbz w0, MterpException 2812 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 2813 GET_INST_OPCODE ip // extract opcode from rINST 2814 GOTO_OPCODE ip // jump to next instruction 2815 2816/* ------------------------------ */ 2817 .balign 128 2818.L_op_sput_boolean: /* 0x6a */ 2819/* File: arm64/op_sput_boolean.S */ 2820/* File: arm64/op_sput.S */ 2821 /* 2822 * General SPUT handler wrapper. 2823 * 2824 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2825 */ 2826 /* op vAA, field//BBBB */ 2827 EXPORT_PC 2828 FETCH w0, 1 // r0<- field ref BBBB 2829 lsr w3, wINST, #8 // r3<- AA 2830 GET_VREG w1, w3 // r1<= fp[AA] 2831 ldr x2, [xFP, #OFF_FP_METHOD] 2832 mov x3, xSELF 2833 PREFETCH_INST 2 // Get next inst, but don't advance rPC 2834 bl MterpSetBooleanStatic 2835 cbnz w0, MterpException // 0 on success 2836 ADVANCE 2 // Past exception point - now advance rPC 2837 GET_INST_OPCODE ip // extract opcode from rINST 2838 GOTO_OPCODE ip // jump to next instruction 2839 2840 2841/* ------------------------------ */ 2842 .balign 128 2843.L_op_sput_byte: /* 0x6b */ 2844/* File: arm64/op_sput_byte.S */ 2845/* File: arm64/op_sput.S */ 2846 /* 2847 * General SPUT handler wrapper. 2848 * 2849 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2850 */ 2851 /* op vAA, field//BBBB */ 2852 EXPORT_PC 2853 FETCH w0, 1 // r0<- field ref BBBB 2854 lsr w3, wINST, #8 // r3<- AA 2855 GET_VREG w1, w3 // r1<= fp[AA] 2856 ldr x2, [xFP, #OFF_FP_METHOD] 2857 mov x3, xSELF 2858 PREFETCH_INST 2 // Get next inst, but don't advance rPC 2859 bl MterpSetByteStatic 2860 cbnz w0, MterpException // 0 on success 2861 ADVANCE 2 // Past exception point - now advance rPC 2862 GET_INST_OPCODE ip // extract opcode from rINST 2863 GOTO_OPCODE ip // jump to next instruction 2864 2865 2866/* ------------------------------ */ 2867 .balign 128 2868.L_op_sput_char: /* 0x6c */ 2869/* File: arm64/op_sput_char.S */ 2870/* File: arm64/op_sput.S */ 2871 /* 2872 * General SPUT handler wrapper. 2873 * 2874 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2875 */ 2876 /* op vAA, field//BBBB */ 2877 EXPORT_PC 2878 FETCH w0, 1 // r0<- field ref BBBB 2879 lsr w3, wINST, #8 // r3<- AA 2880 GET_VREG w1, w3 // r1<= fp[AA] 2881 ldr x2, [xFP, #OFF_FP_METHOD] 2882 mov x3, xSELF 2883 PREFETCH_INST 2 // Get next inst, but don't advance rPC 2884 bl MterpSetCharStatic 2885 cbnz w0, MterpException // 0 on success 2886 ADVANCE 2 // Past exception point - now advance rPC 2887 GET_INST_OPCODE ip // extract opcode from rINST 2888 GOTO_OPCODE ip // jump to next instruction 2889 2890 2891/* ------------------------------ */ 2892 .balign 128 2893.L_op_sput_short: /* 0x6d */ 2894/* File: arm64/op_sput_short.S */ 2895/* File: arm64/op_sput.S */ 2896 /* 2897 * General SPUT handler wrapper. 2898 * 2899 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2900 */ 2901 /* op vAA, field//BBBB */ 2902 EXPORT_PC 2903 FETCH w0, 1 // r0<- field ref BBBB 2904 lsr w3, wINST, #8 // r3<- AA 2905 GET_VREG w1, w3 // r1<= fp[AA] 2906 ldr x2, [xFP, #OFF_FP_METHOD] 2907 mov x3, xSELF 2908 PREFETCH_INST 2 // Get next inst, but don't advance rPC 2909 bl MterpSetShortStatic 2910 cbnz w0, MterpException // 0 on success 2911 ADVANCE 2 // Past exception point - now advance rPC 2912 GET_INST_OPCODE ip // extract opcode from rINST 2913 GOTO_OPCODE ip // jump to next instruction 2914 2915 2916/* ------------------------------ */ 2917 .balign 128 2918.L_op_invoke_virtual: /* 0x6e */ 2919/* File: arm64/op_invoke_virtual.S */ 2920/* File: arm64/invoke.S */ 2921 /* 2922 * Generic invoke handler wrapper. 2923 */ 2924 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 2925 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 2926 .extern MterpInvokeVirtual 2927 EXPORT_PC 2928 mov x0, xSELF 2929 add x1, xFP, #OFF_FP_SHADOWFRAME 2930 mov x2, xPC 2931 mov x3, xINST 2932 bl MterpInvokeVirtual 2933 cbz w0, MterpException 2934 FETCH_ADVANCE_INST 3 2935 bl MterpShouldSwitchInterpreters 2936 cbnz w0, MterpFallback 2937 GET_INST_OPCODE ip 2938 GOTO_OPCODE ip 2939 2940 2941 /* 2942 * Handle a virtual method call. 2943 * 2944 * for: invoke-virtual, invoke-virtual/range 2945 */ 2946 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 2947 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 2948 2949/* ------------------------------ */ 2950 .balign 128 2951.L_op_invoke_super: /* 0x6f */ 2952/* File: arm64/op_invoke_super.S */ 2953/* File: arm64/invoke.S */ 2954 /* 2955 * Generic invoke handler wrapper. 2956 */ 2957 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 2958 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 2959 .extern MterpInvokeSuper 2960 EXPORT_PC 2961 mov x0, xSELF 2962 add x1, xFP, #OFF_FP_SHADOWFRAME 2963 mov x2, xPC 2964 mov x3, xINST 2965 bl MterpInvokeSuper 2966 cbz w0, MterpException 2967 FETCH_ADVANCE_INST 3 2968 bl MterpShouldSwitchInterpreters 2969 cbnz w0, MterpFallback 2970 GET_INST_OPCODE ip 2971 GOTO_OPCODE ip 2972 2973 2974 /* 2975 * Handle a "super" method call. 2976 * 2977 * for: invoke-super, invoke-super/range 2978 */ 2979 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 2980 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 2981 2982/* ------------------------------ */ 2983 .balign 128 2984.L_op_invoke_direct: /* 0x70 */ 2985/* File: arm64/op_invoke_direct.S */ 2986/* File: arm64/invoke.S */ 2987 /* 2988 * Generic invoke handler wrapper. 2989 */ 2990 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 2991 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 2992 .extern MterpInvokeDirect 2993 EXPORT_PC 2994 mov x0, xSELF 2995 add x1, xFP, #OFF_FP_SHADOWFRAME 2996 mov x2, xPC 2997 mov x3, xINST 2998 bl MterpInvokeDirect 2999 cbz w0, MterpException 3000 FETCH_ADVANCE_INST 3 3001 bl MterpShouldSwitchInterpreters 3002 cbnz w0, MterpFallback 3003 GET_INST_OPCODE ip 3004 GOTO_OPCODE ip 3005 3006 3007 3008/* ------------------------------ */ 3009 .balign 128 3010.L_op_invoke_static: /* 0x71 */ 3011/* File: arm64/op_invoke_static.S */ 3012/* File: arm64/invoke.S */ 3013 /* 3014 * Generic invoke handler wrapper. 3015 */ 3016 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3017 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3018 .extern MterpInvokeStatic 3019 EXPORT_PC 3020 mov x0, xSELF 3021 add x1, xFP, #OFF_FP_SHADOWFRAME 3022 mov x2, xPC 3023 mov x3, xINST 3024 bl MterpInvokeStatic 3025 cbz w0, MterpException 3026 FETCH_ADVANCE_INST 3 3027 bl MterpShouldSwitchInterpreters 3028 cbnz w0, MterpFallback 3029 GET_INST_OPCODE ip 3030 GOTO_OPCODE ip 3031 3032 3033 3034 3035/* ------------------------------ */ 3036 .balign 128 3037.L_op_invoke_interface: /* 0x72 */ 3038/* File: arm64/op_invoke_interface.S */ 3039/* File: arm64/invoke.S */ 3040 /* 3041 * Generic invoke handler wrapper. 3042 */ 3043 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3044 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3045 .extern MterpInvokeInterface 3046 EXPORT_PC 3047 mov x0, xSELF 3048 add x1, xFP, #OFF_FP_SHADOWFRAME 3049 mov x2, xPC 3050 mov x3, xINST 3051 bl MterpInvokeInterface 3052 cbz w0, MterpException 3053 FETCH_ADVANCE_INST 3 3054 bl MterpShouldSwitchInterpreters 3055 cbnz w0, MterpFallback 3056 GET_INST_OPCODE ip 3057 GOTO_OPCODE ip 3058 3059 3060 /* 3061 * Handle an interface method call. 3062 * 3063 * for: invoke-interface, invoke-interface/range 3064 */ 3065 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3066 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3067 3068/* ------------------------------ */ 3069 .balign 128 3070.L_op_return_void_no_barrier: /* 0x73 */ 3071/* File: arm64/op_return_void_no_barrier.S */ 3072 ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] 3073 mov x0, xSELF 3074 ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 3075 b.ne .Lop_return_void_no_barrier_check 3076.Lop_return_void_no_barrier_return: 3077 mov x0, #0 3078 b MterpReturn 3079.Lop_return_void_no_barrier_check: 3080 bl MterpSuspendCheck // (self) 3081 b .Lop_return_void_no_barrier_return 3082 3083/* ------------------------------ */ 3084 .balign 128 3085.L_op_invoke_virtual_range: /* 0x74 */ 3086/* File: arm64/op_invoke_virtual_range.S */ 3087/* File: arm64/invoke.S */ 3088 /* 3089 * Generic invoke handler wrapper. 3090 */ 3091 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3092 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3093 .extern MterpInvokeVirtualRange 3094 EXPORT_PC 3095 mov x0, xSELF 3096 add x1, xFP, #OFF_FP_SHADOWFRAME 3097 mov x2, xPC 3098 mov x3, xINST 3099 bl MterpInvokeVirtualRange 3100 cbz w0, MterpException 3101 FETCH_ADVANCE_INST 3 3102 bl MterpShouldSwitchInterpreters 3103 cbnz w0, MterpFallback 3104 GET_INST_OPCODE ip 3105 GOTO_OPCODE ip 3106 3107 3108 3109/* ------------------------------ */ 3110 .balign 128 3111.L_op_invoke_super_range: /* 0x75 */ 3112/* File: arm64/op_invoke_super_range.S */ 3113/* File: arm64/invoke.S */ 3114 /* 3115 * Generic invoke handler wrapper. 3116 */ 3117 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3118 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3119 .extern MterpInvokeSuperRange 3120 EXPORT_PC 3121 mov x0, xSELF 3122 add x1, xFP, #OFF_FP_SHADOWFRAME 3123 mov x2, xPC 3124 mov x3, xINST 3125 bl MterpInvokeSuperRange 3126 cbz w0, MterpException 3127 FETCH_ADVANCE_INST 3 3128 bl MterpShouldSwitchInterpreters 3129 cbnz w0, MterpFallback 3130 GET_INST_OPCODE ip 3131 GOTO_OPCODE ip 3132 3133 3134 3135/* ------------------------------ */ 3136 .balign 128 3137.L_op_invoke_direct_range: /* 0x76 */ 3138/* File: arm64/op_invoke_direct_range.S */ 3139/* File: arm64/invoke.S */ 3140 /* 3141 * Generic invoke handler wrapper. 3142 */ 3143 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3144 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3145 .extern MterpInvokeDirectRange 3146 EXPORT_PC 3147 mov x0, xSELF 3148 add x1, xFP, #OFF_FP_SHADOWFRAME 3149 mov x2, xPC 3150 mov x3, xINST 3151 bl MterpInvokeDirectRange 3152 cbz w0, MterpException 3153 FETCH_ADVANCE_INST 3 3154 bl MterpShouldSwitchInterpreters 3155 cbnz w0, MterpFallback 3156 GET_INST_OPCODE ip 3157 GOTO_OPCODE ip 3158 3159 3160 3161/* ------------------------------ */ 3162 .balign 128 3163.L_op_invoke_static_range: /* 0x77 */ 3164/* File: arm64/op_invoke_static_range.S */ 3165/* File: arm64/invoke.S */ 3166 /* 3167 * Generic invoke handler wrapper. 3168 */ 3169 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3170 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3171 .extern MterpInvokeStaticRange 3172 EXPORT_PC 3173 mov x0, xSELF 3174 add x1, xFP, #OFF_FP_SHADOWFRAME 3175 mov x2, xPC 3176 mov x3, xINST 3177 bl MterpInvokeStaticRange 3178 cbz w0, MterpException 3179 FETCH_ADVANCE_INST 3 3180 bl MterpShouldSwitchInterpreters 3181 cbnz w0, MterpFallback 3182 GET_INST_OPCODE ip 3183 GOTO_OPCODE ip 3184 3185 3186 3187/* ------------------------------ */ 3188 .balign 128 3189.L_op_invoke_interface_range: /* 0x78 */ 3190/* File: arm64/op_invoke_interface_range.S */ 3191/* File: arm64/invoke.S */ 3192 /* 3193 * Generic invoke handler wrapper. 3194 */ 3195 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3196 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3197 .extern MterpInvokeInterfaceRange 3198 EXPORT_PC 3199 mov x0, xSELF 3200 add x1, xFP, #OFF_FP_SHADOWFRAME 3201 mov x2, xPC 3202 mov x3, xINST 3203 bl MterpInvokeInterfaceRange 3204 cbz w0, MterpException 3205 FETCH_ADVANCE_INST 3 3206 bl MterpShouldSwitchInterpreters 3207 cbnz w0, MterpFallback 3208 GET_INST_OPCODE ip 3209 GOTO_OPCODE ip 3210 3211 3212 3213/* ------------------------------ */ 3214 .balign 128 3215.L_op_unused_79: /* 0x79 */ 3216/* File: arm64/op_unused_79.S */ 3217/* File: arm64/unused.S */ 3218/* 3219 * Bail to reference interpreter to throw. 3220 */ 3221 b MterpFallback 3222 3223 3224/* ------------------------------ */ 3225 .balign 128 3226.L_op_unused_7a: /* 0x7a */ 3227/* File: arm64/op_unused_7a.S */ 3228/* File: arm64/unused.S */ 3229/* 3230 * Bail to reference interpreter to throw. 3231 */ 3232 b MterpFallback 3233 3234 3235/* ------------------------------ */ 3236 .balign 128 3237.L_op_neg_int: /* 0x7b */ 3238/* File: arm64/op_neg_int.S */ 3239/* File: arm64/unop.S */ 3240 /* 3241 * Generic 32-bit unary operation. Provide an "instr" line that 3242 * specifies an instruction that performs "result = op w0". 3243 * This could be an ARM instruction or a function call. 3244 * 3245 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3246 * int-to-byte, int-to-char, int-to-short 3247 */ 3248 /* unop vA, vB */ 3249 lsr w3, wINST, #12 // w3<- B 3250 GET_VREG w0, w3 // w0<- vB 3251 ubfx w9, wINST, #8, #4 // w9<- A 3252 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 3253 sub w0, wzr, w0 // w0<- op, w0-w3 changed 3254 GET_INST_OPCODE ip // extract opcode from rINST 3255 SET_VREG w0, w9 // vAA<- w0 3256 GOTO_OPCODE ip // jump to next instruction 3257 /* 8-9 instructions */ 3258 3259 3260/* ------------------------------ */ 3261 .balign 128 3262.L_op_not_int: /* 0x7c */ 3263/* File: arm64/op_not_int.S */ 3264/* File: arm64/unop.S */ 3265 /* 3266 * Generic 32-bit unary operation. Provide an "instr" line that 3267 * specifies an instruction that performs "result = op w0". 3268 * This could be an ARM instruction or a function call. 3269 * 3270 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3271 * int-to-byte, int-to-char, int-to-short 3272 */ 3273 /* unop vA, vB */ 3274 lsr w3, wINST, #12 // w3<- B 3275 GET_VREG w0, w3 // w0<- vB 3276 ubfx w9, wINST, #8, #4 // w9<- A 3277 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 3278 mvn w0, w0 // w0<- op, w0-w3 changed 3279 GET_INST_OPCODE ip // extract opcode from rINST 3280 SET_VREG w0, w9 // vAA<- w0 3281 GOTO_OPCODE ip // jump to next instruction 3282 /* 8-9 instructions */ 3283 3284 3285/* ------------------------------ */ 3286 .balign 128 3287.L_op_neg_long: /* 0x7d */ 3288/* File: arm64/op_neg_long.S */ 3289/* File: arm64/unopWide.S */ 3290 /* 3291 * Generic 64-bit unary operation. Provide an "instr" line that 3292 * specifies an instruction that performs "result = op x0". 3293 * 3294 * For: neg-long, not-long 3295 */ 3296 /* unop vA, vB */ 3297 lsr w3, wINST, #12 // w3<- B 3298 ubfx w4, wINST, #8, #4 // w4<- A 3299 GET_VREG_WIDE x0, w3 3300 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3301 sub x0, xzr, x0 3302 GET_INST_OPCODE ip // extract opcode from wINST 3303 SET_VREG_WIDE x0, w4 3304 GOTO_OPCODE ip // jump to next instruction 3305 /* 10-11 instructions */ 3306 3307 3308/* ------------------------------ */ 3309 .balign 128 3310.L_op_not_long: /* 0x7e */ 3311/* File: arm64/op_not_long.S */ 3312/* File: arm64/unopWide.S */ 3313 /* 3314 * Generic 64-bit unary operation. Provide an "instr" line that 3315 * specifies an instruction that performs "result = op x0". 3316 * 3317 * For: neg-long, not-long 3318 */ 3319 /* unop vA, vB */ 3320 lsr w3, wINST, #12 // w3<- B 3321 ubfx w4, wINST, #8, #4 // w4<- A 3322 GET_VREG_WIDE x0, w3 3323 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3324 mvn x0, x0 3325 GET_INST_OPCODE ip // extract opcode from wINST 3326 SET_VREG_WIDE x0, w4 3327 GOTO_OPCODE ip // jump to next instruction 3328 /* 10-11 instructions */ 3329 3330 3331/* ------------------------------ */ 3332 .balign 128 3333.L_op_neg_float: /* 0x7f */ 3334/* File: arm64/op_neg_float.S */ 3335/* File: arm64/unop.S */ 3336 /* 3337 * Generic 32-bit unary operation. Provide an "instr" line that 3338 * specifies an instruction that performs "result = op w0". 3339 * This could be an ARM instruction or a function call. 3340 * 3341 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3342 * int-to-byte, int-to-char, int-to-short 3343 */ 3344 /* unop vA, vB */ 3345 lsr w3, wINST, #12 // w3<- B 3346 GET_VREG w0, w3 // w0<- vB 3347 ubfx w9, wINST, #8, #4 // w9<- A 3348 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 3349 eor w0, w0, #0x80000000 // w0<- op, w0-w3 changed 3350 GET_INST_OPCODE ip // extract opcode from rINST 3351 SET_VREG w0, w9 // vAA<- w0 3352 GOTO_OPCODE ip // jump to next instruction 3353 /* 8-9 instructions */ 3354 3355 3356/* ------------------------------ */ 3357 .balign 128 3358.L_op_neg_double: /* 0x80 */ 3359/* File: arm64/op_neg_double.S */ 3360/* File: arm64/unopWide.S */ 3361 /* 3362 * Generic 64-bit unary operation. Provide an "instr" line that 3363 * specifies an instruction that performs "result = op x0". 3364 * 3365 * For: neg-long, not-long 3366 */ 3367 /* unop vA, vB */ 3368 lsr w3, wINST, #12 // w3<- B 3369 ubfx w4, wINST, #8, #4 // w4<- A 3370 GET_VREG_WIDE x0, w3 3371 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3372 eor x0, x0, #0x8000000000000000 3373 GET_INST_OPCODE ip // extract opcode from wINST 3374 SET_VREG_WIDE x0, w4 3375 GOTO_OPCODE ip // jump to next instruction 3376 /* 10-11 instructions */ 3377 3378 3379/* ------------------------------ */ 3380 .balign 128 3381.L_op_int_to_long: /* 0x81 */ 3382/* File: arm64/op_int_to_long.S */ 3383 /* int-to-long vA, vB */ 3384 lsr w3, wINST, #12 // w3<- B 3385 ubfx w4, wINST, #8, #4 // w4<- A 3386 GET_VREG_S x0, w3 // x0<- sign_extend(fp[B]) 3387 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3388 GET_INST_OPCODE ip // extract opcode from wINST 3389 SET_VREG_WIDE x0, w4 // fp[A]<- x0 3390 GOTO_OPCODE ip // jump to next instruction 3391 3392/* ------------------------------ */ 3393 .balign 128 3394.L_op_int_to_float: /* 0x82 */ 3395/* File: arm64/op_int_to_float.S */ 3396/* File: arm64/funopNarrow.S */ 3397 /* 3398 * Generic 32bit-to-32bit floating point unary operation. Provide an 3399 * "instr" line that specifies an instruction that performs "s0 = op w0". 3400 * 3401 * For: int-to-float, float-to-int 3402 * TODO: refactor all of the conversions - parameterize width and use same template. 3403 */ 3404 /* unop vA, vB */ 3405 lsr w3, wINST, #12 // w3<- B 3406 ubfx w4, wINST, #8, #4 // w4<- A 3407 GET_VREG w0, w3 3408 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3409 scvtf s0, w0 // d0<- op 3410 GET_INST_OPCODE ip // extract opcode from wINST 3411 SET_VREG s0, w4 // vA<- d0 3412 GOTO_OPCODE ip // jump to next instruction 3413 3414 3415/* ------------------------------ */ 3416 .balign 128 3417.L_op_int_to_double: /* 0x83 */ 3418/* File: arm64/op_int_to_double.S */ 3419/* File: arm64/funopWider.S */ 3420 /* 3421 * Generic 32bit-to-64bit floating point unary operation. Provide an 3422 * "instr" line that specifies an instruction that performs "d0 = op w0". 3423 * 3424 * For: int-to-double, float-to-double, float-to-long 3425 */ 3426 /* unop vA, vB */ 3427 lsr w3, wINST, #12 // w3<- B 3428 ubfx w4, wINST, #8, #4 // w4<- A 3429 GET_VREG w0, w3 3430 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3431 scvtf d0, w0 // d0<- op 3432 GET_INST_OPCODE ip // extract opcode from wINST 3433 SET_VREG_WIDE d0, w4 // vA<- d0 3434 GOTO_OPCODE ip // jump to next instruction 3435 3436 3437/* ------------------------------ */ 3438 .balign 128 3439.L_op_long_to_int: /* 0x84 */ 3440/* File: arm64/op_long_to_int.S */ 3441/* we ignore the high word, making this equivalent to a 32-bit reg move */ 3442/* File: arm64/op_move.S */ 3443 /* for move, move-object, long-to-int */ 3444 /* op vA, vB */ 3445 lsr w1, wINST, #12 // x1<- B from 15:12 3446 ubfx w0, wINST, #8, #4 // x0<- A from 11:8 3447 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3448 GET_VREG w2, w1 // x2<- fp[B] 3449 GET_INST_OPCODE ip // ip<- opcode from wINST 3450 .if 0 3451 SET_VREG_OBJECT w2, w0 // fp[A]<- x2 3452 .else 3453 SET_VREG w2, w0 // fp[A]<- x2 3454 .endif 3455 GOTO_OPCODE ip // execute next instruction 3456 3457 3458/* ------------------------------ */ 3459 .balign 128 3460.L_op_long_to_float: /* 0x85 */ 3461/* File: arm64/op_long_to_float.S */ 3462/* File: arm64/funopNarrower.S */ 3463 /* 3464 * Generic 64bit-to-32bit floating point unary operation. Provide an 3465 * "instr" line that specifies an instruction that performs "s0 = op x0". 3466 * 3467 * For: int-to-double, float-to-double, float-to-long 3468 */ 3469 /* unop vA, vB */ 3470 lsr w3, wINST, #12 // w3<- B 3471 ubfx w4, wINST, #8, #4 // w4<- A 3472 GET_VREG_WIDE x0, w3 3473 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3474 scvtf s0, x0 // d0<- op 3475 GET_INST_OPCODE ip // extract opcode from wINST 3476 SET_VREG s0, w4 // vA<- d0 3477 GOTO_OPCODE ip // jump to next instruction 3478 3479 3480/* ------------------------------ */ 3481 .balign 128 3482.L_op_long_to_double: /* 0x86 */ 3483/* File: arm64/op_long_to_double.S */ 3484/* File: arm64/funopWide.S */ 3485 /* 3486 * Generic 64bit-to-64bit floating point unary operation. Provide an 3487 * "instr" line that specifies an instruction that performs "d0 = op x0". 3488 * 3489 * For: long-to-double, double-to-long 3490 */ 3491 /* unop vA, vB */ 3492 lsr w3, wINST, #12 // w3<- B 3493 ubfx w4, wINST, #8, #4 // w4<- A 3494 GET_VREG_WIDE x0, w3 3495 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3496 scvtf d0, x0 // d0<- op 3497 GET_INST_OPCODE ip // extract opcode from wINST 3498 SET_VREG_WIDE d0, w4 // vA<- d0 3499 GOTO_OPCODE ip // jump to next instruction 3500 3501 3502/* ------------------------------ */ 3503 .balign 128 3504.L_op_float_to_int: /* 0x87 */ 3505/* File: arm64/op_float_to_int.S */ 3506/* File: arm64/funopNarrow.S */ 3507 /* 3508 * Generic 32bit-to-32bit floating point unary operation. Provide an 3509 * "instr" line that specifies an instruction that performs "w0 = op s0". 3510 * 3511 * For: int-to-float, float-to-int 3512 * TODO: refactor all of the conversions - parameterize width and use same template. 3513 */ 3514 /* unop vA, vB */ 3515 lsr w3, wINST, #12 // w3<- B 3516 ubfx w4, wINST, #8, #4 // w4<- A 3517 GET_VREG s0, w3 3518 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3519 fcvtzs w0, s0 // d0<- op 3520 GET_INST_OPCODE ip // extract opcode from wINST 3521 SET_VREG w0, w4 // vA<- d0 3522 GOTO_OPCODE ip // jump to next instruction 3523 3524 3525/* ------------------------------ */ 3526 .balign 128 3527.L_op_float_to_long: /* 0x88 */ 3528/* File: arm64/op_float_to_long.S */ 3529/* File: arm64/funopWider.S */ 3530 /* 3531 * Generic 32bit-to-64bit floating point unary operation. Provide an 3532 * "instr" line that specifies an instruction that performs "x0 = op s0". 3533 * 3534 * For: int-to-double, float-to-double, float-to-long 3535 */ 3536 /* unop vA, vB */ 3537 lsr w3, wINST, #12 // w3<- B 3538 ubfx w4, wINST, #8, #4 // w4<- A 3539 GET_VREG s0, w3 3540 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3541 fcvtzs x0, s0 // d0<- op 3542 GET_INST_OPCODE ip // extract opcode from wINST 3543 SET_VREG_WIDE x0, w4 // vA<- d0 3544 GOTO_OPCODE ip // jump to next instruction 3545 3546 3547/* ------------------------------ */ 3548 .balign 128 3549.L_op_float_to_double: /* 0x89 */ 3550/* File: arm64/op_float_to_double.S */ 3551/* File: arm64/funopWider.S */ 3552 /* 3553 * Generic 32bit-to-64bit floating point unary operation. Provide an 3554 * "instr" line that specifies an instruction that performs "d0 = op s0". 3555 * 3556 * For: int-to-double, float-to-double, float-to-long 3557 */ 3558 /* unop vA, vB */ 3559 lsr w3, wINST, #12 // w3<- B 3560 ubfx w4, wINST, #8, #4 // w4<- A 3561 GET_VREG s0, w3 3562 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3563 fcvt d0, s0 // d0<- op 3564 GET_INST_OPCODE ip // extract opcode from wINST 3565 SET_VREG_WIDE d0, w4 // vA<- d0 3566 GOTO_OPCODE ip // jump to next instruction 3567 3568 3569/* ------------------------------ */ 3570 .balign 128 3571.L_op_double_to_int: /* 0x8a */ 3572/* File: arm64/op_double_to_int.S */ 3573/* File: arm64/funopNarrower.S */ 3574 /* 3575 * Generic 64bit-to-32bit floating point unary operation. Provide an 3576 * "instr" line that specifies an instruction that performs "w0 = op d0". 3577 * 3578 * For: int-to-double, float-to-double, float-to-long 3579 */ 3580 /* unop vA, vB */ 3581 lsr w3, wINST, #12 // w3<- B 3582 ubfx w4, wINST, #8, #4 // w4<- A 3583 GET_VREG_WIDE d0, w3 3584 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3585 fcvtzs w0, d0 // d0<- op 3586 GET_INST_OPCODE ip // extract opcode from wINST 3587 SET_VREG w0, w4 // vA<- d0 3588 GOTO_OPCODE ip // jump to next instruction 3589 3590 3591/* ------------------------------ */ 3592 .balign 128 3593.L_op_double_to_long: /* 0x8b */ 3594/* File: arm64/op_double_to_long.S */ 3595/* File: arm64/funopWide.S */ 3596 /* 3597 * Generic 64bit-to-64bit floating point unary operation. Provide an 3598 * "instr" line that specifies an instruction that performs "x0 = op d0". 3599 * 3600 * For: long-to-double, double-to-long 3601 */ 3602 /* unop vA, vB */ 3603 lsr w3, wINST, #12 // w3<- B 3604 ubfx w4, wINST, #8, #4 // w4<- A 3605 GET_VREG_WIDE d0, w3 3606 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3607 fcvtzs x0, d0 // d0<- op 3608 GET_INST_OPCODE ip // extract opcode from wINST 3609 SET_VREG_WIDE x0, w4 // vA<- d0 3610 GOTO_OPCODE ip // jump to next instruction 3611 3612 3613/* ------------------------------ */ 3614 .balign 128 3615.L_op_double_to_float: /* 0x8c */ 3616/* File: arm64/op_double_to_float.S */ 3617/* File: arm64/funopNarrower.S */ 3618 /* 3619 * Generic 64bit-to-32bit floating point unary operation. Provide an 3620 * "instr" line that specifies an instruction that performs "s0 = op d0". 3621 * 3622 * For: int-to-double, float-to-double, float-to-long 3623 */ 3624 /* unop vA, vB */ 3625 lsr w3, wINST, #12 // w3<- B 3626 ubfx w4, wINST, #8, #4 // w4<- A 3627 GET_VREG_WIDE d0, w3 3628 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3629 fcvt s0, d0 // d0<- op 3630 GET_INST_OPCODE ip // extract opcode from wINST 3631 SET_VREG s0, w4 // vA<- d0 3632 GOTO_OPCODE ip // jump to next instruction 3633 3634 3635/* ------------------------------ */ 3636 .balign 128 3637.L_op_int_to_byte: /* 0x8d */ 3638/* File: arm64/op_int_to_byte.S */ 3639/* File: arm64/unop.S */ 3640 /* 3641 * Generic 32-bit unary operation. Provide an "instr" line that 3642 * specifies an instruction that performs "result = op w0". 3643 * This could be an ARM instruction or a function call. 3644 * 3645 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3646 * int-to-byte, int-to-char, int-to-short 3647 */ 3648 /* unop vA, vB */ 3649 lsr w3, wINST, #12 // w3<- B 3650 GET_VREG w0, w3 // w0<- vB 3651 ubfx w9, wINST, #8, #4 // w9<- A 3652 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 3653 sxtb w0, w0 // w0<- op, w0-w3 changed 3654 GET_INST_OPCODE ip // extract opcode from rINST 3655 SET_VREG w0, w9 // vAA<- w0 3656 GOTO_OPCODE ip // jump to next instruction 3657 /* 8-9 instructions */ 3658 3659 3660/* ------------------------------ */ 3661 .balign 128 3662.L_op_int_to_char: /* 0x8e */ 3663/* File: arm64/op_int_to_char.S */ 3664/* File: arm64/unop.S */ 3665 /* 3666 * Generic 32-bit unary operation. Provide an "instr" line that 3667 * specifies an instruction that performs "result = op w0". 3668 * This could be an ARM instruction or a function call. 3669 * 3670 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3671 * int-to-byte, int-to-char, int-to-short 3672 */ 3673 /* unop vA, vB */ 3674 lsr w3, wINST, #12 // w3<- B 3675 GET_VREG w0, w3 // w0<- vB 3676 ubfx w9, wINST, #8, #4 // w9<- A 3677 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 3678 uxth w0, w0 // w0<- op, w0-w3 changed 3679 GET_INST_OPCODE ip // extract opcode from rINST 3680 SET_VREG w0, w9 // vAA<- w0 3681 GOTO_OPCODE ip // jump to next instruction 3682 /* 8-9 instructions */ 3683 3684 3685/* ------------------------------ */ 3686 .balign 128 3687.L_op_int_to_short: /* 0x8f */ 3688/* File: arm64/op_int_to_short.S */ 3689/* File: arm64/unop.S */ 3690 /* 3691 * Generic 32-bit unary operation. Provide an "instr" line that 3692 * specifies an instruction that performs "result = op w0". 3693 * This could be an ARM instruction or a function call. 3694 * 3695 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3696 * int-to-byte, int-to-char, int-to-short 3697 */ 3698 /* unop vA, vB */ 3699 lsr w3, wINST, #12 // w3<- B 3700 GET_VREG w0, w3 // w0<- vB 3701 ubfx w9, wINST, #8, #4 // w9<- A 3702 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 3703 sxth w0, w0 // w0<- op, w0-w3 changed 3704 GET_INST_OPCODE ip // extract opcode from rINST 3705 SET_VREG w0, w9 // vAA<- w0 3706 GOTO_OPCODE ip // jump to next instruction 3707 /* 8-9 instructions */ 3708 3709 3710/* ------------------------------ */ 3711 .balign 128 3712.L_op_add_int: /* 0x90 */ 3713/* File: arm64/op_add_int.S */ 3714/* File: arm64/binop.S */ 3715 /* 3716 * Generic 32-bit binary operation. Provide an "instr" line that 3717 * specifies an instruction that performs "result = w0 op w1". 3718 * This could be an ARM instruction or a function call. (If the result 3719 * comes back in a register other than w0, you can override "result".) 3720 * 3721 * If "chkzero" is set to 1, we perform a divide-by-zero check on 3722 * vCC (w1). Useful for integer division and modulus. Note that we 3723 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 3724 * handles it correctly. 3725 * 3726 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 3727 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 3728 * mul-float, div-float, rem-float 3729 */ 3730 /* binop vAA, vBB, vCC */ 3731 FETCH w0, 1 // w0<- CCBB 3732 lsr w9, wINST, #8 // w9<- AA 3733 lsr w3, w0, #8 // w3<- CC 3734 and w2, w0, #255 // w2<- BB 3735 GET_VREG w1, w3 // w1<- vCC 3736 GET_VREG w0, w2 // w0<- vBB 3737 .if 0 3738 cbz w1, common_errDivideByZero // is second operand zero? 3739 .endif 3740 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 3741 // optional op; may set condition codes 3742 add w0, w0, w1 // w0<- op, w0-w3 changed 3743 GET_INST_OPCODE ip // extract opcode from rINST 3744 SET_VREG w0, w9 // vAA<- w0 3745 GOTO_OPCODE ip // jump to next instruction 3746 /* 11-14 instructions */ 3747 3748 3749/* ------------------------------ */ 3750 .balign 128 3751.L_op_sub_int: /* 0x91 */ 3752/* File: arm64/op_sub_int.S */ 3753/* File: arm64/binop.S */ 3754 /* 3755 * Generic 32-bit binary operation. Provide an "instr" line that 3756 * specifies an instruction that performs "result = w0 op w1". 3757 * This could be an ARM instruction or a function call. (If the result 3758 * comes back in a register other than w0, you can override "result".) 3759 * 3760 * If "chkzero" is set to 1, we perform a divide-by-zero check on 3761 * vCC (w1). Useful for integer division and modulus. Note that we 3762 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 3763 * handles it correctly. 3764 * 3765 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 3766 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 3767 * mul-float, div-float, rem-float 3768 */ 3769 /* binop vAA, vBB, vCC */ 3770 FETCH w0, 1 // w0<- CCBB 3771 lsr w9, wINST, #8 // w9<- AA 3772 lsr w3, w0, #8 // w3<- CC 3773 and w2, w0, #255 // w2<- BB 3774 GET_VREG w1, w3 // w1<- vCC 3775 GET_VREG w0, w2 // w0<- vBB 3776 .if 0 3777 cbz w1, common_errDivideByZero // is second operand zero? 3778 .endif 3779 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 3780 // optional op; may set condition codes 3781 sub w0, w0, w1 // w0<- op, w0-w3 changed 3782 GET_INST_OPCODE ip // extract opcode from rINST 3783 SET_VREG w0, w9 // vAA<- w0 3784 GOTO_OPCODE ip // jump to next instruction 3785 /* 11-14 instructions */ 3786 3787 3788/* ------------------------------ */ 3789 .balign 128 3790.L_op_mul_int: /* 0x92 */ 3791/* File: arm64/op_mul_int.S */ 3792/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ 3793/* File: arm64/binop.S */ 3794 /* 3795 * Generic 32-bit binary operation. Provide an "instr" line that 3796 * specifies an instruction that performs "result = w0 op w1". 3797 * This could be an ARM instruction or a function call. (If the result 3798 * comes back in a register other than w0, you can override "result".) 3799 * 3800 * If "chkzero" is set to 1, we perform a divide-by-zero check on 3801 * vCC (w1). Useful for integer division and modulus. Note that we 3802 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 3803 * handles it correctly. 3804 * 3805 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 3806 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 3807 * mul-float, div-float, rem-float 3808 */ 3809 /* binop vAA, vBB, vCC */ 3810 FETCH w0, 1 // w0<- CCBB 3811 lsr w9, wINST, #8 // w9<- AA 3812 lsr w3, w0, #8 // w3<- CC 3813 and w2, w0, #255 // w2<- BB 3814 GET_VREG w1, w3 // w1<- vCC 3815 GET_VREG w0, w2 // w0<- vBB 3816 .if 0 3817 cbz w1, common_errDivideByZero // is second operand zero? 3818 .endif 3819 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 3820 // optional op; may set condition codes 3821 mul w0, w1, w0 // w0<- op, w0-w3 changed 3822 GET_INST_OPCODE ip // extract opcode from rINST 3823 SET_VREG w0, w9 // vAA<- w0 3824 GOTO_OPCODE ip // jump to next instruction 3825 /* 11-14 instructions */ 3826 3827 3828/* ------------------------------ */ 3829 .balign 128 3830.L_op_div_int: /* 0x93 */ 3831/* File: arm64/op_div_int.S */ 3832/* File: arm64/binop.S */ 3833 /* 3834 * Generic 32-bit binary operation. Provide an "instr" line that 3835 * specifies an instruction that performs "result = w0 op w1". 3836 * This could be an ARM instruction or a function call. (If the result 3837 * comes back in a register other than w0, you can override "result".) 3838 * 3839 * If "chkzero" is set to 1, we perform a divide-by-zero check on 3840 * vCC (w1). Useful for integer division and modulus. Note that we 3841 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 3842 * handles it correctly. 3843 * 3844 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 3845 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 3846 * mul-float, div-float, rem-float 3847 */ 3848 /* binop vAA, vBB, vCC */ 3849 FETCH w0, 1 // w0<- CCBB 3850 lsr w9, wINST, #8 // w9<- AA 3851 lsr w3, w0, #8 // w3<- CC 3852 and w2, w0, #255 // w2<- BB 3853 GET_VREG w1, w3 // w1<- vCC 3854 GET_VREG w0, w2 // w0<- vBB 3855 .if 1 3856 cbz w1, common_errDivideByZero // is second operand zero? 3857 .endif 3858 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 3859 // optional op; may set condition codes 3860 sdiv w0, w0, w1 // w0<- op, w0-w3 changed 3861 GET_INST_OPCODE ip // extract opcode from rINST 3862 SET_VREG w0, w9 // vAA<- w0 3863 GOTO_OPCODE ip // jump to next instruction 3864 /* 11-14 instructions */ 3865 3866 3867/* ------------------------------ */ 3868 .balign 128 3869.L_op_rem_int: /* 0x94 */ 3870/* File: arm64/op_rem_int.S */ 3871/* File: arm64/binop.S */ 3872 /* 3873 * Generic 32-bit binary operation. Provide an "instr" line that 3874 * specifies an instruction that performs "result = w0 op w1". 3875 * This could be an ARM instruction or a function call. (If the result 3876 * comes back in a register other than w0, you can override "result".) 3877 * 3878 * If "chkzero" is set to 1, we perform a divide-by-zero check on 3879 * vCC (w1). Useful for integer division and modulus. Note that we 3880 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 3881 * handles it correctly. 3882 * 3883 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 3884 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 3885 * mul-float, div-float, rem-float 3886 */ 3887 /* binop vAA, vBB, vCC */ 3888 FETCH w0, 1 // w0<- CCBB 3889 lsr w9, wINST, #8 // w9<- AA 3890 lsr w3, w0, #8 // w3<- CC 3891 and w2, w0, #255 // w2<- BB 3892 GET_VREG w1, w3 // w1<- vCC 3893 GET_VREG w0, w2 // w0<- vBB 3894 .if 1 3895 cbz w1, common_errDivideByZero // is second operand zero? 3896 .endif 3897 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 3898 sdiv w2, w0, w1 // optional op; may set condition codes 3899 msub w0, w2, w1, w0 // w0<- op, w0-w3 changed 3900 GET_INST_OPCODE ip // extract opcode from rINST 3901 SET_VREG w0, w9 // vAA<- w0 3902 GOTO_OPCODE ip // jump to next instruction 3903 /* 11-14 instructions */ 3904 3905 3906/* ------------------------------ */ 3907 .balign 128 3908.L_op_and_int: /* 0x95 */ 3909/* File: arm64/op_and_int.S */ 3910/* File: arm64/binop.S */ 3911 /* 3912 * Generic 32-bit binary operation. Provide an "instr" line that 3913 * specifies an instruction that performs "result = w0 op w1". 3914 * This could be an ARM instruction or a function call. (If the result 3915 * comes back in a register other than w0, you can override "result".) 3916 * 3917 * If "chkzero" is set to 1, we perform a divide-by-zero check on 3918 * vCC (w1). Useful for integer division and modulus. Note that we 3919 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 3920 * handles it correctly. 3921 * 3922 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 3923 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 3924 * mul-float, div-float, rem-float 3925 */ 3926 /* binop vAA, vBB, vCC */ 3927 FETCH w0, 1 // w0<- CCBB 3928 lsr w9, wINST, #8 // w9<- AA 3929 lsr w3, w0, #8 // w3<- CC 3930 and w2, w0, #255 // w2<- BB 3931 GET_VREG w1, w3 // w1<- vCC 3932 GET_VREG w0, w2 // w0<- vBB 3933 .if 0 3934 cbz w1, common_errDivideByZero // is second operand zero? 3935 .endif 3936 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 3937 // optional op; may set condition codes 3938 and w0, w0, w1 // w0<- op, w0-w3 changed 3939 GET_INST_OPCODE ip // extract opcode from rINST 3940 SET_VREG w0, w9 // vAA<- w0 3941 GOTO_OPCODE ip // jump to next instruction 3942 /* 11-14 instructions */ 3943 3944 3945/* ------------------------------ */ 3946 .balign 128 3947.L_op_or_int: /* 0x96 */ 3948/* File: arm64/op_or_int.S */ 3949/* File: arm64/binop.S */ 3950 /* 3951 * Generic 32-bit binary operation. Provide an "instr" line that 3952 * specifies an instruction that performs "result = w0 op w1". 3953 * This could be an ARM instruction or a function call. (If the result 3954 * comes back in a register other than w0, you can override "result".) 3955 * 3956 * If "chkzero" is set to 1, we perform a divide-by-zero check on 3957 * vCC (w1). Useful for integer division and modulus. Note that we 3958 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 3959 * handles it correctly. 3960 * 3961 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 3962 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 3963 * mul-float, div-float, rem-float 3964 */ 3965 /* binop vAA, vBB, vCC */ 3966 FETCH w0, 1 // w0<- CCBB 3967 lsr w9, wINST, #8 // w9<- AA 3968 lsr w3, w0, #8 // w3<- CC 3969 and w2, w0, #255 // w2<- BB 3970 GET_VREG w1, w3 // w1<- vCC 3971 GET_VREG w0, w2 // w0<- vBB 3972 .if 0 3973 cbz w1, common_errDivideByZero // is second operand zero? 3974 .endif 3975 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 3976 // optional op; may set condition codes 3977 orr w0, w0, w1 // w0<- op, w0-w3 changed 3978 GET_INST_OPCODE ip // extract opcode from rINST 3979 SET_VREG w0, w9 // vAA<- w0 3980 GOTO_OPCODE ip // jump to next instruction 3981 /* 11-14 instructions */ 3982 3983 3984/* ------------------------------ */ 3985 .balign 128 3986.L_op_xor_int: /* 0x97 */ 3987/* File: arm64/op_xor_int.S */ 3988/* File: arm64/binop.S */ 3989 /* 3990 * Generic 32-bit binary operation. Provide an "instr" line that 3991 * specifies an instruction that performs "result = w0 op w1". 3992 * This could be an ARM instruction or a function call. (If the result 3993 * comes back in a register other than w0, you can override "result".) 3994 * 3995 * If "chkzero" is set to 1, we perform a divide-by-zero check on 3996 * vCC (w1). Useful for integer division and modulus. Note that we 3997 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 3998 * handles it correctly. 3999 * 4000 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4001 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4002 * mul-float, div-float, rem-float 4003 */ 4004 /* binop vAA, vBB, vCC */ 4005 FETCH w0, 1 // w0<- CCBB 4006 lsr w9, wINST, #8 // w9<- AA 4007 lsr w3, w0, #8 // w3<- CC 4008 and w2, w0, #255 // w2<- BB 4009 GET_VREG w1, w3 // w1<- vCC 4010 GET_VREG w0, w2 // w0<- vBB 4011 .if 0 4012 cbz w1, common_errDivideByZero // is second operand zero? 4013 .endif 4014 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4015 // optional op; may set condition codes 4016 eor w0, w0, w1 // w0<- op, w0-w3 changed 4017 GET_INST_OPCODE ip // extract opcode from rINST 4018 SET_VREG w0, w9 // vAA<- w0 4019 GOTO_OPCODE ip // jump to next instruction 4020 /* 11-14 instructions */ 4021 4022 4023/* ------------------------------ */ 4024 .balign 128 4025.L_op_shl_int: /* 0x98 */ 4026/* File: arm64/op_shl_int.S */ 4027/* File: arm64/binop.S */ 4028 /* 4029 * Generic 32-bit binary operation. Provide an "instr" line that 4030 * specifies an instruction that performs "result = w0 op w1". 4031 * This could be an ARM instruction or a function call. (If the result 4032 * comes back in a register other than w0, you can override "result".) 4033 * 4034 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4035 * vCC (w1). Useful for integer division and modulus. Note that we 4036 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4037 * handles it correctly. 4038 * 4039 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4040 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4041 * mul-float, div-float, rem-float 4042 */ 4043 /* binop vAA, vBB, vCC */ 4044 FETCH w0, 1 // w0<- CCBB 4045 lsr w9, wINST, #8 // w9<- AA 4046 lsr w3, w0, #8 // w3<- CC 4047 and w2, w0, #255 // w2<- BB 4048 GET_VREG w1, w3 // w1<- vCC 4049 GET_VREG w0, w2 // w0<- vBB 4050 .if 0 4051 cbz w1, common_errDivideByZero // is second operand zero? 4052 .endif 4053 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4054 // optional op; may set condition codes 4055 lsl w0, w0, w1 // w0<- op, w0-w3 changed 4056 GET_INST_OPCODE ip // extract opcode from rINST 4057 SET_VREG w0, w9 // vAA<- w0 4058 GOTO_OPCODE ip // jump to next instruction 4059 /* 11-14 instructions */ 4060 4061 4062/* ------------------------------ */ 4063 .balign 128 4064.L_op_shr_int: /* 0x99 */ 4065/* File: arm64/op_shr_int.S */ 4066/* File: arm64/binop.S */ 4067 /* 4068 * Generic 32-bit binary operation. Provide an "instr" line that 4069 * specifies an instruction that performs "result = w0 op w1". 4070 * This could be an ARM instruction or a function call. (If the result 4071 * comes back in a register other than w0, you can override "result".) 4072 * 4073 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4074 * vCC (w1). Useful for integer division and modulus. Note that we 4075 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4076 * handles it correctly. 4077 * 4078 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4079 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4080 * mul-float, div-float, rem-float 4081 */ 4082 /* binop vAA, vBB, vCC */ 4083 FETCH w0, 1 // w0<- CCBB 4084 lsr w9, wINST, #8 // w9<- AA 4085 lsr w3, w0, #8 // w3<- CC 4086 and w2, w0, #255 // w2<- BB 4087 GET_VREG w1, w3 // w1<- vCC 4088 GET_VREG w0, w2 // w0<- vBB 4089 .if 0 4090 cbz w1, common_errDivideByZero // is second operand zero? 4091 .endif 4092 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4093 // optional op; may set condition codes 4094 asr w0, w0, w1 // w0<- op, w0-w3 changed 4095 GET_INST_OPCODE ip // extract opcode from rINST 4096 SET_VREG w0, w9 // vAA<- w0 4097 GOTO_OPCODE ip // jump to next instruction 4098 /* 11-14 instructions */ 4099 4100 4101/* ------------------------------ */ 4102 .balign 128 4103.L_op_ushr_int: /* 0x9a */ 4104/* File: arm64/op_ushr_int.S */ 4105/* File: arm64/binop.S */ 4106 /* 4107 * Generic 32-bit binary operation. Provide an "instr" line that 4108 * specifies an instruction that performs "result = w0 op w1". 4109 * This could be an ARM instruction or a function call. (If the result 4110 * comes back in a register other than w0, you can override "result".) 4111 * 4112 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4113 * vCC (w1). Useful for integer division and modulus. Note that we 4114 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4115 * handles it correctly. 4116 * 4117 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4118 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4119 * mul-float, div-float, rem-float 4120 */ 4121 /* binop vAA, vBB, vCC */ 4122 FETCH w0, 1 // w0<- CCBB 4123 lsr w9, wINST, #8 // w9<- AA 4124 lsr w3, w0, #8 // w3<- CC 4125 and w2, w0, #255 // w2<- BB 4126 GET_VREG w1, w3 // w1<- vCC 4127 GET_VREG w0, w2 // w0<- vBB 4128 .if 0 4129 cbz w1, common_errDivideByZero // is second operand zero? 4130 .endif 4131 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4132 // optional op; may set condition codes 4133 lsr w0, w0, w1 // w0<- op, w0-w3 changed 4134 GET_INST_OPCODE ip // extract opcode from rINST 4135 SET_VREG w0, w9 // vAA<- w0 4136 GOTO_OPCODE ip // jump to next instruction 4137 /* 11-14 instructions */ 4138 4139 4140/* ------------------------------ */ 4141 .balign 128 4142.L_op_add_long: /* 0x9b */ 4143/* File: arm64/op_add_long.S */ 4144/* File: arm64/binopWide.S */ 4145 /* 4146 * Generic 64-bit binary operation. Provide an "instr" line that 4147 * specifies an instruction that performs "result = x1 op x2". 4148 * This could be an ARM instruction or a function call. (If the result 4149 * comes back in a register other than x0, you can override "result".) 4150 * 4151 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4152 * vCC (w1). Useful for integer division and modulus. 4153 * 4154 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4155 * xor-long, add-double, sub-double, mul-double, div-double, rem-double 4156 */ 4157 /* binop vAA, vBB, vCC */ 4158 FETCH w0, 1 // w0<- CCBB 4159 lsr w4, wINST, #8 // w4<- AA 4160 lsr w2, w0, #8 // w2<- CC 4161 and w1, w0, #255 // w1<- BB 4162 GET_VREG_WIDE x2, w2 // w2<- vCC 4163 GET_VREG_WIDE x1, w1 // w1<- vBB 4164 .if 0 4165 cbz x2, common_errDivideByZero // is second operand zero? 4166 .endif 4167 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4168 4169 add x0, x1, x2 // x0<- op, w0-w4 changed 4170 GET_INST_OPCODE ip // extract opcode from rINST 4171 SET_VREG_WIDE x0, w4 // vAA<- x0 4172 GOTO_OPCODE ip // jump to next instruction 4173 /* 11-14 instructions */ 4174 4175 4176/* ------------------------------ */ 4177 .balign 128 4178.L_op_sub_long: /* 0x9c */ 4179/* File: arm64/op_sub_long.S */ 4180/* File: arm64/binopWide.S */ 4181 /* 4182 * Generic 64-bit binary operation. Provide an "instr" line that 4183 * specifies an instruction that performs "result = x1 op x2". 4184 * This could be an ARM instruction or a function call. (If the result 4185 * comes back in a register other than x0, you can override "result".) 4186 * 4187 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4188 * vCC (w1). Useful for integer division and modulus. 4189 * 4190 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4191 * xor-long, add-double, sub-double, mul-double, div-double, rem-double 4192 */ 4193 /* binop vAA, vBB, vCC */ 4194 FETCH w0, 1 // w0<- CCBB 4195 lsr w4, wINST, #8 // w4<- AA 4196 lsr w2, w0, #8 // w2<- CC 4197 and w1, w0, #255 // w1<- BB 4198 GET_VREG_WIDE x2, w2 // w2<- vCC 4199 GET_VREG_WIDE x1, w1 // w1<- vBB 4200 .if 0 4201 cbz x2, common_errDivideByZero // is second operand zero? 4202 .endif 4203 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4204 4205 sub x0, x1, x2 // x0<- op, w0-w4 changed 4206 GET_INST_OPCODE ip // extract opcode from rINST 4207 SET_VREG_WIDE x0, w4 // vAA<- x0 4208 GOTO_OPCODE ip // jump to next instruction 4209 /* 11-14 instructions */ 4210 4211 4212/* ------------------------------ */ 4213 .balign 128 4214.L_op_mul_long: /* 0x9d */ 4215/* File: arm64/op_mul_long.S */ 4216/* File: arm64/binopWide.S */ 4217 /* 4218 * Generic 64-bit binary operation. Provide an "instr" line that 4219 * specifies an instruction that performs "result = x1 op x2". 4220 * This could be an ARM instruction or a function call. (If the result 4221 * comes back in a register other than x0, you can override "result".) 4222 * 4223 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4224 * vCC (w1). Useful for integer division and modulus. 4225 * 4226 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4227 * xor-long, add-double, sub-double, mul-double, div-double, rem-double 4228 */ 4229 /* binop vAA, vBB, vCC */ 4230 FETCH w0, 1 // w0<- CCBB 4231 lsr w4, wINST, #8 // w4<- AA 4232 lsr w2, w0, #8 // w2<- CC 4233 and w1, w0, #255 // w1<- BB 4234 GET_VREG_WIDE x2, w2 // w2<- vCC 4235 GET_VREG_WIDE x1, w1 // w1<- vBB 4236 .if 0 4237 cbz x2, common_errDivideByZero // is second operand zero? 4238 .endif 4239 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4240 4241 mul x0, x1, x2 // x0<- op, w0-w4 changed 4242 GET_INST_OPCODE ip // extract opcode from rINST 4243 SET_VREG_WIDE x0, w4 // vAA<- x0 4244 GOTO_OPCODE ip // jump to next instruction 4245 /* 11-14 instructions */ 4246 4247 4248/* ------------------------------ */ 4249 .balign 128 4250.L_op_div_long: /* 0x9e */ 4251/* File: arm64/op_div_long.S */ 4252/* File: arm64/binopWide.S */ 4253 /* 4254 * Generic 64-bit binary operation. Provide an "instr" line that 4255 * specifies an instruction that performs "result = x1 op x2". 4256 * This could be an ARM instruction or a function call. (If the result 4257 * comes back in a register other than x0, you can override "result".) 4258 * 4259 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4260 * vCC (w1). Useful for integer division and modulus. 4261 * 4262 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4263 * xor-long, add-double, sub-double, mul-double, div-double, rem-double 4264 */ 4265 /* binop vAA, vBB, vCC */ 4266 FETCH w0, 1 // w0<- CCBB 4267 lsr w4, wINST, #8 // w4<- AA 4268 lsr w2, w0, #8 // w2<- CC 4269 and w1, w0, #255 // w1<- BB 4270 GET_VREG_WIDE x2, w2 // w2<- vCC 4271 GET_VREG_WIDE x1, w1 // w1<- vBB 4272 .if 1 4273 cbz x2, common_errDivideByZero // is second operand zero? 4274 .endif 4275 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4276 4277 sdiv x0, x1, x2 // x0<- op, w0-w4 changed 4278 GET_INST_OPCODE ip // extract opcode from rINST 4279 SET_VREG_WIDE x0, w4 // vAA<- x0 4280 GOTO_OPCODE ip // jump to next instruction 4281 /* 11-14 instructions */ 4282 4283 4284/* ------------------------------ */ 4285 .balign 128 4286.L_op_rem_long: /* 0x9f */ 4287/* File: arm64/op_rem_long.S */ 4288/* File: arm64/binopWide.S */ 4289 /* 4290 * Generic 64-bit binary operation. Provide an "instr" line that 4291 * specifies an instruction that performs "result = x1 op x2". 4292 * This could be an ARM instruction or a function call. (If the result 4293 * comes back in a register other than x0, you can override "result".) 4294 * 4295 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4296 * vCC (w1). Useful for integer division and modulus. 4297 * 4298 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4299 * xor-long, add-double, sub-double, mul-double, div-double, rem-double 4300 */ 4301 /* binop vAA, vBB, vCC */ 4302 FETCH w0, 1 // w0<- CCBB 4303 lsr w4, wINST, #8 // w4<- AA 4304 lsr w2, w0, #8 // w2<- CC 4305 and w1, w0, #255 // w1<- BB 4306 GET_VREG_WIDE x2, w2 // w2<- vCC 4307 GET_VREG_WIDE x1, w1 // w1<- vBB 4308 .if 1 4309 cbz x2, common_errDivideByZero // is second operand zero? 4310 .endif 4311 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4312 sdiv x3, x1, x2 4313 msub x0, x3, x2, x1 // x0<- op, w0-w4 changed 4314 GET_INST_OPCODE ip // extract opcode from rINST 4315 SET_VREG_WIDE x0, w4 // vAA<- x0 4316 GOTO_OPCODE ip // jump to next instruction 4317 /* 11-14 instructions */ 4318 4319 4320/* ------------------------------ */ 4321 .balign 128 4322.L_op_and_long: /* 0xa0 */ 4323/* File: arm64/op_and_long.S */ 4324/* File: arm64/binopWide.S */ 4325 /* 4326 * Generic 64-bit binary operation. Provide an "instr" line that 4327 * specifies an instruction that performs "result = x1 op x2". 4328 * This could be an ARM instruction or a function call. (If the result 4329 * comes back in a register other than x0, you can override "result".) 4330 * 4331 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4332 * vCC (w1). Useful for integer division and modulus. 4333 * 4334 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4335 * xor-long, add-double, sub-double, mul-double, div-double, rem-double 4336 */ 4337 /* binop vAA, vBB, vCC */ 4338 FETCH w0, 1 // w0<- CCBB 4339 lsr w4, wINST, #8 // w4<- AA 4340 lsr w2, w0, #8 // w2<- CC 4341 and w1, w0, #255 // w1<- BB 4342 GET_VREG_WIDE x2, w2 // w2<- vCC 4343 GET_VREG_WIDE x1, w1 // w1<- vBB 4344 .if 0 4345 cbz x2, common_errDivideByZero // is second operand zero? 4346 .endif 4347 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4348 4349 and x0, x1, x2 // x0<- op, w0-w4 changed 4350 GET_INST_OPCODE ip // extract opcode from rINST 4351 SET_VREG_WIDE x0, w4 // vAA<- x0 4352 GOTO_OPCODE ip // jump to next instruction 4353 /* 11-14 instructions */ 4354 4355 4356/* ------------------------------ */ 4357 .balign 128 4358.L_op_or_long: /* 0xa1 */ 4359/* File: arm64/op_or_long.S */ 4360/* File: arm64/binopWide.S */ 4361 /* 4362 * Generic 64-bit binary operation. Provide an "instr" line that 4363 * specifies an instruction that performs "result = x1 op x2". 4364 * This could be an ARM instruction or a function call. (If the result 4365 * comes back in a register other than x0, you can override "result".) 4366 * 4367 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4368 * vCC (w1). Useful for integer division and modulus. 4369 * 4370 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4371 * xor-long, add-double, sub-double, mul-double, div-double, rem-double 4372 */ 4373 /* binop vAA, vBB, vCC */ 4374 FETCH w0, 1 // w0<- CCBB 4375 lsr w4, wINST, #8 // w4<- AA 4376 lsr w2, w0, #8 // w2<- CC 4377 and w1, w0, #255 // w1<- BB 4378 GET_VREG_WIDE x2, w2 // w2<- vCC 4379 GET_VREG_WIDE x1, w1 // w1<- vBB 4380 .if 0 4381 cbz x2, common_errDivideByZero // is second operand zero? 4382 .endif 4383 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4384 4385 orr x0, x1, x2 // x0<- op, w0-w4 changed 4386 GET_INST_OPCODE ip // extract opcode from rINST 4387 SET_VREG_WIDE x0, w4 // vAA<- x0 4388 GOTO_OPCODE ip // jump to next instruction 4389 /* 11-14 instructions */ 4390 4391 4392/* ------------------------------ */ 4393 .balign 128 4394.L_op_xor_long: /* 0xa2 */ 4395/* File: arm64/op_xor_long.S */ 4396/* File: arm64/binopWide.S */ 4397 /* 4398 * Generic 64-bit binary operation. Provide an "instr" line that 4399 * specifies an instruction that performs "result = x1 op x2". 4400 * This could be an ARM instruction or a function call. (If the result 4401 * comes back in a register other than x0, you can override "result".) 4402 * 4403 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4404 * vCC (w1). Useful for integer division and modulus. 4405 * 4406 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4407 * xor-long, add-double, sub-double, mul-double, div-double, rem-double 4408 */ 4409 /* binop vAA, vBB, vCC */ 4410 FETCH w0, 1 // w0<- CCBB 4411 lsr w4, wINST, #8 // w4<- AA 4412 lsr w2, w0, #8 // w2<- CC 4413 and w1, w0, #255 // w1<- BB 4414 GET_VREG_WIDE x2, w2 // w2<- vCC 4415 GET_VREG_WIDE x1, w1 // w1<- vBB 4416 .if 0 4417 cbz x2, common_errDivideByZero // is second operand zero? 4418 .endif 4419 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4420 4421 eor x0, x1, x2 // x0<- op, w0-w4 changed 4422 GET_INST_OPCODE ip // extract opcode from rINST 4423 SET_VREG_WIDE x0, w4 // vAA<- x0 4424 GOTO_OPCODE ip // jump to next instruction 4425 /* 11-14 instructions */ 4426 4427 4428/* ------------------------------ */ 4429 .balign 128 4430.L_op_shl_long: /* 0xa3 */ 4431/* File: arm64/op_shl_long.S */ 4432/* File: arm64/shiftWide.S */ 4433 /* 4434 * 64-bit shift operation. 4435 * 4436 * For: shl-long, shr-long, ushr-long 4437 */ 4438 /* binop vAA, vBB, vCC */ 4439 FETCH w0, 1 // w0<- CCBB 4440 lsr w3, wINST, #8 // w3<- AA 4441 lsr w2, w0, #8 // w2<- CC 4442 GET_VREG w2, w2 // w2<- vCC (shift count) 4443 and w1, w0, #255 // w1<- BB 4444 GET_VREG_WIDE x1, w1 // x1<- vBB 4445 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4446 lsl x0, x1, x2 // Do the shift. Only low 6 bits of x2 are used. 4447 GET_INST_OPCODE ip // extract opcode from rINST 4448 SET_VREG_WIDE x0, w3 // vAA<- x0 4449 GOTO_OPCODE ip // jump to next instruction 4450 /* 11-14 instructions */ 4451 4452 4453/* ------------------------------ */ 4454 .balign 128 4455.L_op_shr_long: /* 0xa4 */ 4456/* File: arm64/op_shr_long.S */ 4457/* File: arm64/shiftWide.S */ 4458 /* 4459 * 64-bit shift operation. 4460 * 4461 * For: shl-long, shr-long, ushr-long 4462 */ 4463 /* binop vAA, vBB, vCC */ 4464 FETCH w0, 1 // w0<- CCBB 4465 lsr w3, wINST, #8 // w3<- AA 4466 lsr w2, w0, #8 // w2<- CC 4467 GET_VREG w2, w2 // w2<- vCC (shift count) 4468 and w1, w0, #255 // w1<- BB 4469 GET_VREG_WIDE x1, w1 // x1<- vBB 4470 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4471 asr x0, x1, x2 // Do the shift. Only low 6 bits of x2 are used. 4472 GET_INST_OPCODE ip // extract opcode from rINST 4473 SET_VREG_WIDE x0, w3 // vAA<- x0 4474 GOTO_OPCODE ip // jump to next instruction 4475 /* 11-14 instructions */ 4476 4477 4478/* ------------------------------ */ 4479 .balign 128 4480.L_op_ushr_long: /* 0xa5 */ 4481/* File: arm64/op_ushr_long.S */ 4482/* File: arm64/shiftWide.S */ 4483 /* 4484 * 64-bit shift operation. 4485 * 4486 * For: shl-long, shr-long, ushr-long 4487 */ 4488 /* binop vAA, vBB, vCC */ 4489 FETCH w0, 1 // w0<- CCBB 4490 lsr w3, wINST, #8 // w3<- AA 4491 lsr w2, w0, #8 // w2<- CC 4492 GET_VREG w2, w2 // w2<- vCC (shift count) 4493 and w1, w0, #255 // w1<- BB 4494 GET_VREG_WIDE x1, w1 // x1<- vBB 4495 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4496 lsr x0, x1, x2 // Do the shift. Only low 6 bits of x2 are used. 4497 GET_INST_OPCODE ip // extract opcode from rINST 4498 SET_VREG_WIDE x0, w3 // vAA<- x0 4499 GOTO_OPCODE ip // jump to next instruction 4500 /* 11-14 instructions */ 4501 4502 4503/* ------------------------------ */ 4504 .balign 128 4505.L_op_add_float: /* 0xa6 */ 4506/* File: arm64/op_add_float.S */ 4507/* File: arm64/fbinop.S */ 4508 /*: 4509 * Generic 32-bit floating-point operation. 4510 * 4511 * For: add-float, sub-float, mul-float, div-float 4512 * form: <op> s0, s0, s1 4513 */ 4514 /* floatop vAA, vBB, vCC */ 4515 FETCH w0, 1 // r0<- CCBB 4516 lsr w1, w0, #8 // r2<- CC 4517 and w0, w0, #255 // r1<- BB 4518 GET_VREG s1, w1 4519 GET_VREG s0, w0 4520 fadd s0, s0, s1 // s0<- op 4521 lsr w1, wINST, #8 // r1<- AA 4522 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4523 GET_INST_OPCODE ip // extract opcode from rINST 4524 SET_VREG s0, w1 4525 GOTO_OPCODE ip // jump to next instruction 4526 4527 4528/* ------------------------------ */ 4529 .balign 128 4530.L_op_sub_float: /* 0xa7 */ 4531/* File: arm64/op_sub_float.S */ 4532/* File: arm64/fbinop.S */ 4533 /*: 4534 * Generic 32-bit floating-point operation. 4535 * 4536 * For: add-float, sub-float, mul-float, div-float 4537 * form: <op> s0, s0, s1 4538 */ 4539 /* floatop vAA, vBB, vCC */ 4540 FETCH w0, 1 // r0<- CCBB 4541 lsr w1, w0, #8 // r2<- CC 4542 and w0, w0, #255 // r1<- BB 4543 GET_VREG s1, w1 4544 GET_VREG s0, w0 4545 fsub s0, s0, s1 // s0<- op 4546 lsr w1, wINST, #8 // r1<- AA 4547 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4548 GET_INST_OPCODE ip // extract opcode from rINST 4549 SET_VREG s0, w1 4550 GOTO_OPCODE ip // jump to next instruction 4551 4552 4553/* ------------------------------ */ 4554 .balign 128 4555.L_op_mul_float: /* 0xa8 */ 4556/* File: arm64/op_mul_float.S */ 4557/* File: arm64/fbinop.S */ 4558 /*: 4559 * Generic 32-bit floating-point operation. 4560 * 4561 * For: add-float, sub-float, mul-float, div-float 4562 * form: <op> s0, s0, s1 4563 */ 4564 /* floatop vAA, vBB, vCC */ 4565 FETCH w0, 1 // r0<- CCBB 4566 lsr w1, w0, #8 // r2<- CC 4567 and w0, w0, #255 // r1<- BB 4568 GET_VREG s1, w1 4569 GET_VREG s0, w0 4570 fmul s0, s0, s1 // s0<- op 4571 lsr w1, wINST, #8 // r1<- AA 4572 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4573 GET_INST_OPCODE ip // extract opcode from rINST 4574 SET_VREG s0, w1 4575 GOTO_OPCODE ip // jump to next instruction 4576 4577 4578/* ------------------------------ */ 4579 .balign 128 4580.L_op_div_float: /* 0xa9 */ 4581/* File: arm64/op_div_float.S */ 4582/* File: arm64/fbinop.S */ 4583 /*: 4584 * Generic 32-bit floating-point operation. 4585 * 4586 * For: add-float, sub-float, mul-float, div-float 4587 * form: <op> s0, s0, s1 4588 */ 4589 /* floatop vAA, vBB, vCC */ 4590 FETCH w0, 1 // r0<- CCBB 4591 lsr w1, w0, #8 // r2<- CC 4592 and w0, w0, #255 // r1<- BB 4593 GET_VREG s1, w1 4594 GET_VREG s0, w0 4595 fdiv s0, s0, s1 // s0<- op 4596 lsr w1, wINST, #8 // r1<- AA 4597 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4598 GET_INST_OPCODE ip // extract opcode from rINST 4599 SET_VREG s0, w1 4600 GOTO_OPCODE ip // jump to next instruction 4601 4602 4603/* ------------------------------ */ 4604 .balign 128 4605.L_op_rem_float: /* 0xaa */ 4606/* File: arm64/op_rem_float.S */ 4607/* EABI doesn't define a float remainder function, but libm does */ 4608/* File: arm64/fbinop.S */ 4609 /*: 4610 * Generic 32-bit floating-point operation. 4611 * 4612 * For: add-float, sub-float, mul-float, div-float 4613 * form: <op> s0, s0, s1 4614 */ 4615 /* floatop vAA, vBB, vCC */ 4616 FETCH w0, 1 // r0<- CCBB 4617 lsr w1, w0, #8 // r2<- CC 4618 and w0, w0, #255 // r1<- BB 4619 GET_VREG s1, w1 4620 GET_VREG s0, w0 4621 bl fmodf // s0<- op 4622 lsr w1, wINST, #8 // r1<- AA 4623 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4624 GET_INST_OPCODE ip // extract opcode from rINST 4625 SET_VREG s0, w1 4626 GOTO_OPCODE ip // jump to next instruction 4627 4628 4629/* ------------------------------ */ 4630 .balign 128 4631.L_op_add_double: /* 0xab */ 4632/* File: arm64/op_add_double.S */ 4633/* File: arm64/binopWide.S */ 4634 /* 4635 * Generic 64-bit binary operation. Provide an "instr" line that 4636 * specifies an instruction that performs "result = x1 op x2". 4637 * This could be an ARM instruction or a function call. (If the result 4638 * comes back in a register other than x0, you can override "result".) 4639 * 4640 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4641 * vCC (w1). Useful for integer division and modulus. 4642 * 4643 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4644 * xor-long, add-double, sub-double, mul-double, div-double, rem-double 4645 */ 4646 /* binop vAA, vBB, vCC */ 4647 FETCH w0, 1 // w0<- CCBB 4648 lsr w4, wINST, #8 // w4<- AA 4649 lsr w2, w0, #8 // w2<- CC 4650 and w1, w0, #255 // w1<- BB 4651 GET_VREG_WIDE d2, w2 // w2<- vCC 4652 GET_VREG_WIDE d1, w1 // w1<- vBB 4653 .if 0 4654 cbz d2, common_errDivideByZero // is second operand zero? 4655 .endif 4656 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4657 4658 fadd d0, d1, d2 // d0<- op, w0-w4 changed 4659 GET_INST_OPCODE ip // extract opcode from rINST 4660 SET_VREG_WIDE d0, w4 // vAA<- d0 4661 GOTO_OPCODE ip // jump to next instruction 4662 /* 11-14 instructions */ 4663 4664 4665/* ------------------------------ */ 4666 .balign 128 4667.L_op_sub_double: /* 0xac */ 4668/* File: arm64/op_sub_double.S */ 4669/* File: arm64/binopWide.S */ 4670 /* 4671 * Generic 64-bit binary operation. Provide an "instr" line that 4672 * specifies an instruction that performs "result = x1 op x2". 4673 * This could be an ARM instruction or a function call. (If the result 4674 * comes back in a register other than x0, you can override "result".) 4675 * 4676 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4677 * vCC (w1). Useful for integer division and modulus. 4678 * 4679 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4680 * xor-long, add-double, sub-double, mul-double, div-double, rem-double 4681 */ 4682 /* binop vAA, vBB, vCC */ 4683 FETCH w0, 1 // w0<- CCBB 4684 lsr w4, wINST, #8 // w4<- AA 4685 lsr w2, w0, #8 // w2<- CC 4686 and w1, w0, #255 // w1<- BB 4687 GET_VREG_WIDE d2, w2 // w2<- vCC 4688 GET_VREG_WIDE d1, w1 // w1<- vBB 4689 .if 0 4690 cbz d2, common_errDivideByZero // is second operand zero? 4691 .endif 4692 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4693 4694 fsub d0, d1, d2 // d0<- op, w0-w4 changed 4695 GET_INST_OPCODE ip // extract opcode from rINST 4696 SET_VREG_WIDE d0, w4 // vAA<- d0 4697 GOTO_OPCODE ip // jump to next instruction 4698 /* 11-14 instructions */ 4699 4700 4701/* ------------------------------ */ 4702 .balign 128 4703.L_op_mul_double: /* 0xad */ 4704/* File: arm64/op_mul_double.S */ 4705/* File: arm64/binopWide.S */ 4706 /* 4707 * Generic 64-bit binary operation. Provide an "instr" line that 4708 * specifies an instruction that performs "result = x1 op x2". 4709 * This could be an ARM instruction or a function call. (If the result 4710 * comes back in a register other than x0, you can override "result".) 4711 * 4712 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4713 * vCC (w1). Useful for integer division and modulus. 4714 * 4715 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4716 * xor-long, add-double, sub-double, mul-double, div-double, rem-double 4717 */ 4718 /* binop vAA, vBB, vCC */ 4719 FETCH w0, 1 // w0<- CCBB 4720 lsr w4, wINST, #8 // w4<- AA 4721 lsr w2, w0, #8 // w2<- CC 4722 and w1, w0, #255 // w1<- BB 4723 GET_VREG_WIDE d2, w2 // w2<- vCC 4724 GET_VREG_WIDE d1, w1 // w1<- vBB 4725 .if 0 4726 cbz d2, common_errDivideByZero // is second operand zero? 4727 .endif 4728 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4729 4730 fmul d0, d1, d2 // d0<- op, w0-w4 changed 4731 GET_INST_OPCODE ip // extract opcode from rINST 4732 SET_VREG_WIDE d0, w4 // vAA<- d0 4733 GOTO_OPCODE ip // jump to next instruction 4734 /* 11-14 instructions */ 4735 4736 4737/* ------------------------------ */ 4738 .balign 128 4739.L_op_div_double: /* 0xae */ 4740/* File: arm64/op_div_double.S */ 4741/* File: arm64/binopWide.S */ 4742 /* 4743 * Generic 64-bit binary operation. Provide an "instr" line that 4744 * specifies an instruction that performs "result = x1 op x2". 4745 * This could be an ARM instruction or a function call. (If the result 4746 * comes back in a register other than x0, you can override "result".) 4747 * 4748 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4749 * vCC (w1). Useful for integer division and modulus. 4750 * 4751 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4752 * xor-long, add-double, sub-double, mul-double, div-double, rem-double 4753 */ 4754 /* binop vAA, vBB, vCC */ 4755 FETCH w0, 1 // w0<- CCBB 4756 lsr w4, wINST, #8 // w4<- AA 4757 lsr w2, w0, #8 // w2<- CC 4758 and w1, w0, #255 // w1<- BB 4759 GET_VREG_WIDE d2, w2 // w2<- vCC 4760 GET_VREG_WIDE d1, w1 // w1<- vBB 4761 .if 0 4762 cbz d2, common_errDivideByZero // is second operand zero? 4763 .endif 4764 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4765 4766 fdiv d0, d1, d2 // d0<- op, w0-w4 changed 4767 GET_INST_OPCODE ip // extract opcode from rINST 4768 SET_VREG_WIDE d0, w4 // vAA<- d0 4769 GOTO_OPCODE ip // jump to next instruction 4770 /* 11-14 instructions */ 4771 4772 4773/* ------------------------------ */ 4774 .balign 128 4775.L_op_rem_double: /* 0xaf */ 4776/* File: arm64/op_rem_double.S */ 4777 /* rem vAA, vBB, vCC */ 4778 FETCH w0, 1 // w0<- CCBB 4779 lsr w2, w0, #8 // w2<- CC 4780 and w1, w0, #255 // w1<- BB 4781 GET_VREG_WIDE d1, w2 // d1<- vCC 4782 GET_VREG_WIDE d0, w1 // d0<- vBB 4783 bl fmod 4784 lsr w4, wINST, #8 // w4<- AA 4785 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4786 GET_INST_OPCODE ip // extract opcode from rINST 4787 SET_VREG_WIDE d0, w4 // vAA<- result 4788 GOTO_OPCODE ip // jump to next instruction 4789 /* 11-14 instructions */ 4790 4791/* ------------------------------ */ 4792 .balign 128 4793.L_op_add_int_2addr: /* 0xb0 */ 4794/* File: arm64/op_add_int_2addr.S */ 4795/* File: arm64/binop2addr.S */ 4796 /* 4797 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 4798 * that specifies an instruction that performs "result = w0 op w1". 4799 * This could be an ARM instruction or a function call. (If the result 4800 * comes back in a register other than w0, you can override "result".) 4801 * 4802 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4803 * vCC (w1). Useful for integer division and modulus. 4804 * 4805 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 4806 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 4807 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 4808 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 4809 */ 4810 /* binop/2addr vA, vB */ 4811 lsr w3, wINST, #12 // w3<- B 4812 ubfx w9, wINST, #8, #4 // w9<- A 4813 GET_VREG w1, w3 // w1<- vB 4814 GET_VREG w0, w9 // w0<- vA 4815 .if 0 4816 cbz w1, common_errDivideByZero 4817 .endif 4818 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 4819 // optional op; may set condition codes 4820 add w0, w0, w1 // w0<- op, w0-w3 changed 4821 GET_INST_OPCODE ip // extract opcode from rINST 4822 SET_VREG w0, w9 // vAA<- w0 4823 GOTO_OPCODE ip // jump to next instruction 4824 /* 10-13 instructions */ 4825 4826 4827/* ------------------------------ */ 4828 .balign 128 4829.L_op_sub_int_2addr: /* 0xb1 */ 4830/* File: arm64/op_sub_int_2addr.S */ 4831/* File: arm64/binop2addr.S */ 4832 /* 4833 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 4834 * that specifies an instruction that performs "result = w0 op w1". 4835 * This could be an ARM instruction or a function call. (If the result 4836 * comes back in a register other than w0, you can override "result".) 4837 * 4838 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4839 * vCC (w1). Useful for integer division and modulus. 4840 * 4841 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 4842 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 4843 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 4844 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 4845 */ 4846 /* binop/2addr vA, vB */ 4847 lsr w3, wINST, #12 // w3<- B 4848 ubfx w9, wINST, #8, #4 // w9<- A 4849 GET_VREG w1, w3 // w1<- vB 4850 GET_VREG w0, w9 // w0<- vA 4851 .if 0 4852 cbz w1, common_errDivideByZero 4853 .endif 4854 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 4855 // optional op; may set condition codes 4856 sub w0, w0, w1 // w0<- op, w0-w3 changed 4857 GET_INST_OPCODE ip // extract opcode from rINST 4858 SET_VREG w0, w9 // vAA<- w0 4859 GOTO_OPCODE ip // jump to next instruction 4860 /* 10-13 instructions */ 4861 4862 4863/* ------------------------------ */ 4864 .balign 128 4865.L_op_mul_int_2addr: /* 0xb2 */ 4866/* File: arm64/op_mul_int_2addr.S */ 4867/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ 4868/* File: arm64/binop2addr.S */ 4869 /* 4870 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 4871 * that specifies an instruction that performs "result = w0 op w1". 4872 * This could be an ARM instruction or a function call. (If the result 4873 * comes back in a register other than w0, you can override "result".) 4874 * 4875 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4876 * vCC (w1). Useful for integer division and modulus. 4877 * 4878 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 4879 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 4880 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 4881 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 4882 */ 4883 /* binop/2addr vA, vB */ 4884 lsr w3, wINST, #12 // w3<- B 4885 ubfx w9, wINST, #8, #4 // w9<- A 4886 GET_VREG w1, w3 // w1<- vB 4887 GET_VREG w0, w9 // w0<- vA 4888 .if 0 4889 cbz w1, common_errDivideByZero 4890 .endif 4891 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 4892 // optional op; may set condition codes 4893 mul w0, w1, w0 // w0<- op, w0-w3 changed 4894 GET_INST_OPCODE ip // extract opcode from rINST 4895 SET_VREG w0, w9 // vAA<- w0 4896 GOTO_OPCODE ip // jump to next instruction 4897 /* 10-13 instructions */ 4898 4899 4900/* ------------------------------ */ 4901 .balign 128 4902.L_op_div_int_2addr: /* 0xb3 */ 4903/* File: arm64/op_div_int_2addr.S */ 4904/* File: arm64/binop2addr.S */ 4905 /* 4906 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 4907 * that specifies an instruction that performs "result = w0 op w1". 4908 * This could be an ARM instruction or a function call. (If the result 4909 * comes back in a register other than w0, you can override "result".) 4910 * 4911 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4912 * vCC (w1). Useful for integer division and modulus. 4913 * 4914 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 4915 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 4916 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 4917 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 4918 */ 4919 /* binop/2addr vA, vB */ 4920 lsr w3, wINST, #12 // w3<- B 4921 ubfx w9, wINST, #8, #4 // w9<- A 4922 GET_VREG w1, w3 // w1<- vB 4923 GET_VREG w0, w9 // w0<- vA 4924 .if 1 4925 cbz w1, common_errDivideByZero 4926 .endif 4927 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 4928 // optional op; may set condition codes 4929 sdiv w0, w0, w1 // w0<- op, w0-w3 changed 4930 GET_INST_OPCODE ip // extract opcode from rINST 4931 SET_VREG w0, w9 // vAA<- w0 4932 GOTO_OPCODE ip // jump to next instruction 4933 /* 10-13 instructions */ 4934 4935 4936/* ------------------------------ */ 4937 .balign 128 4938.L_op_rem_int_2addr: /* 0xb4 */ 4939/* File: arm64/op_rem_int_2addr.S */ 4940/* File: arm64/binop2addr.S */ 4941 /* 4942 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 4943 * that specifies an instruction that performs "result = w0 op w1". 4944 * This could be an ARM instruction or a function call. (If the result 4945 * comes back in a register other than w0, you can override "result".) 4946 * 4947 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4948 * vCC (w1). Useful for integer division and modulus. 4949 * 4950 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 4951 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 4952 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 4953 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 4954 */ 4955 /* binop/2addr vA, vB */ 4956 lsr w3, wINST, #12 // w3<- B 4957 ubfx w9, wINST, #8, #4 // w9<- A 4958 GET_VREG w1, w3 // w1<- vB 4959 GET_VREG w0, w9 // w0<- vA 4960 .if 1 4961 cbz w1, common_errDivideByZero 4962 .endif 4963 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 4964 sdiv w2, w0, w1 // optional op; may set condition codes 4965 msub w0, w2, w1, w0 // w0<- op, w0-w3 changed 4966 GET_INST_OPCODE ip // extract opcode from rINST 4967 SET_VREG w0, w9 // vAA<- w0 4968 GOTO_OPCODE ip // jump to next instruction 4969 /* 10-13 instructions */ 4970 4971 4972/* ------------------------------ */ 4973 .balign 128 4974.L_op_and_int_2addr: /* 0xb5 */ 4975/* File: arm64/op_and_int_2addr.S */ 4976/* File: arm64/binop2addr.S */ 4977 /* 4978 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 4979 * that specifies an instruction that performs "result = w0 op w1". 4980 * This could be an ARM instruction or a function call. (If the result 4981 * comes back in a register other than w0, you can override "result".) 4982 * 4983 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4984 * vCC (w1). Useful for integer division and modulus. 4985 * 4986 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 4987 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 4988 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 4989 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 4990 */ 4991 /* binop/2addr vA, vB */ 4992 lsr w3, wINST, #12 // w3<- B 4993 ubfx w9, wINST, #8, #4 // w9<- A 4994 GET_VREG w1, w3 // w1<- vB 4995 GET_VREG w0, w9 // w0<- vA 4996 .if 0 4997 cbz w1, common_errDivideByZero 4998 .endif 4999 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5000 // optional op; may set condition codes 5001 and w0, w0, w1 // w0<- op, w0-w3 changed 5002 GET_INST_OPCODE ip // extract opcode from rINST 5003 SET_VREG w0, w9 // vAA<- w0 5004 GOTO_OPCODE ip // jump to next instruction 5005 /* 10-13 instructions */ 5006 5007 5008/* ------------------------------ */ 5009 .balign 128 5010.L_op_or_int_2addr: /* 0xb6 */ 5011/* File: arm64/op_or_int_2addr.S */ 5012/* File: arm64/binop2addr.S */ 5013 /* 5014 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5015 * that specifies an instruction that performs "result = w0 op w1". 5016 * This could be an ARM instruction or a function call. (If the result 5017 * comes back in a register other than w0, you can override "result".) 5018 * 5019 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5020 * vCC (w1). Useful for integer division and modulus. 5021 * 5022 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5023 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5024 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5025 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5026 */ 5027 /* binop/2addr vA, vB */ 5028 lsr w3, wINST, #12 // w3<- B 5029 ubfx w9, wINST, #8, #4 // w9<- A 5030 GET_VREG w1, w3 // w1<- vB 5031 GET_VREG w0, w9 // w0<- vA 5032 .if 0 5033 cbz w1, common_errDivideByZero 5034 .endif 5035 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5036 // optional op; may set condition codes 5037 orr w0, w0, w1 // w0<- op, w0-w3 changed 5038 GET_INST_OPCODE ip // extract opcode from rINST 5039 SET_VREG w0, w9 // vAA<- w0 5040 GOTO_OPCODE ip // jump to next instruction 5041 /* 10-13 instructions */ 5042 5043 5044/* ------------------------------ */ 5045 .balign 128 5046.L_op_xor_int_2addr: /* 0xb7 */ 5047/* File: arm64/op_xor_int_2addr.S */ 5048/* File: arm64/binop2addr.S */ 5049 /* 5050 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5051 * that specifies an instruction that performs "result = w0 op w1". 5052 * This could be an ARM instruction or a function call. (If the result 5053 * comes back in a register other than w0, you can override "result".) 5054 * 5055 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5056 * vCC (w1). Useful for integer division and modulus. 5057 * 5058 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5059 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5060 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5061 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5062 */ 5063 /* binop/2addr vA, vB */ 5064 lsr w3, wINST, #12 // w3<- B 5065 ubfx w9, wINST, #8, #4 // w9<- A 5066 GET_VREG w1, w3 // w1<- vB 5067 GET_VREG w0, w9 // w0<- vA 5068 .if 0 5069 cbz w1, common_errDivideByZero 5070 .endif 5071 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5072 // optional op; may set condition codes 5073 eor w0, w0, w1 // w0<- op, w0-w3 changed 5074 GET_INST_OPCODE ip // extract opcode from rINST 5075 SET_VREG w0, w9 // vAA<- w0 5076 GOTO_OPCODE ip // jump to next instruction 5077 /* 10-13 instructions */ 5078 5079 5080/* ------------------------------ */ 5081 .balign 128 5082.L_op_shl_int_2addr: /* 0xb8 */ 5083/* File: arm64/op_shl_int_2addr.S */ 5084/* File: arm64/binop2addr.S */ 5085 /* 5086 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5087 * that specifies an instruction that performs "result = w0 op w1". 5088 * This could be an ARM instruction or a function call. (If the result 5089 * comes back in a register other than w0, you can override "result".) 5090 * 5091 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5092 * vCC (w1). Useful for integer division and modulus. 5093 * 5094 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5095 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5096 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5097 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5098 */ 5099 /* binop/2addr vA, vB */ 5100 lsr w3, wINST, #12 // w3<- B 5101 ubfx w9, wINST, #8, #4 // w9<- A 5102 GET_VREG w1, w3 // w1<- vB 5103 GET_VREG w0, w9 // w0<- vA 5104 .if 0 5105 cbz w1, common_errDivideByZero 5106 .endif 5107 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5108 // optional op; may set condition codes 5109 lsl w0, w0, w1 // w0<- op, w0-w3 changed 5110 GET_INST_OPCODE ip // extract opcode from rINST 5111 SET_VREG w0, w9 // vAA<- w0 5112 GOTO_OPCODE ip // jump to next instruction 5113 /* 10-13 instructions */ 5114 5115 5116/* ------------------------------ */ 5117 .balign 128 5118.L_op_shr_int_2addr: /* 0xb9 */ 5119/* File: arm64/op_shr_int_2addr.S */ 5120/* File: arm64/binop2addr.S */ 5121 /* 5122 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5123 * that specifies an instruction that performs "result = w0 op w1". 5124 * This could be an ARM instruction or a function call. (If the result 5125 * comes back in a register other than w0, you can override "result".) 5126 * 5127 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5128 * vCC (w1). Useful for integer division and modulus. 5129 * 5130 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5131 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5132 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5133 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5134 */ 5135 /* binop/2addr vA, vB */ 5136 lsr w3, wINST, #12 // w3<- B 5137 ubfx w9, wINST, #8, #4 // w9<- A 5138 GET_VREG w1, w3 // w1<- vB 5139 GET_VREG w0, w9 // w0<- vA 5140 .if 0 5141 cbz w1, common_errDivideByZero 5142 .endif 5143 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5144 // optional op; may set condition codes 5145 asr w0, w0, w1 // w0<- op, w0-w3 changed 5146 GET_INST_OPCODE ip // extract opcode from rINST 5147 SET_VREG w0, w9 // vAA<- w0 5148 GOTO_OPCODE ip // jump to next instruction 5149 /* 10-13 instructions */ 5150 5151 5152/* ------------------------------ */ 5153 .balign 128 5154.L_op_ushr_int_2addr: /* 0xba */ 5155/* File: arm64/op_ushr_int_2addr.S */ 5156/* File: arm64/binop2addr.S */ 5157 /* 5158 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5159 * that specifies an instruction that performs "result = w0 op w1". 5160 * This could be an ARM instruction or a function call. (If the result 5161 * comes back in a register other than w0, you can override "result".) 5162 * 5163 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5164 * vCC (w1). Useful for integer division and modulus. 5165 * 5166 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5167 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5168 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5169 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5170 */ 5171 /* binop/2addr vA, vB */ 5172 lsr w3, wINST, #12 // w3<- B 5173 ubfx w9, wINST, #8, #4 // w9<- A 5174 GET_VREG w1, w3 // w1<- vB 5175 GET_VREG w0, w9 // w0<- vA 5176 .if 0 5177 cbz w1, common_errDivideByZero 5178 .endif 5179 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5180 // optional op; may set condition codes 5181 lsr w0, w0, w1 // w0<- op, w0-w3 changed 5182 GET_INST_OPCODE ip // extract opcode from rINST 5183 SET_VREG w0, w9 // vAA<- w0 5184 GOTO_OPCODE ip // jump to next instruction 5185 /* 10-13 instructions */ 5186 5187 5188/* ------------------------------ */ 5189 .balign 128 5190.L_op_add_long_2addr: /* 0xbb */ 5191/* File: arm64/op_add_long_2addr.S */ 5192/* File: arm64/binopWide2addr.S */ 5193 /* 5194 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5195 * that specifies an instruction that performs "x0 = x0 op x1". 5196 * This must not be a function call, as we keep w2 live across it. 5197 * 5198 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5199 * vCC (w1). Useful for integer division and modulus. 5200 * 5201 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5202 * and-long/2addr, or-long/2addr, xor-long/2addr, 5203 * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, 5204 * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr 5205 */ 5206 /* binop/2addr vA, vB */ 5207 lsr w1, wINST, #12 // w1<- B 5208 ubfx w2, wINST, #8, #4 // w2<- A 5209 GET_VREG_WIDE x1, w1 // x1<- vB 5210 GET_VREG_WIDE x0, w2 // x0<- vA 5211 .if 0 5212 cbz x1, common_errDivideByZero 5213 .endif 5214 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5215 5216 add x0, x0, x1 // result<- op 5217 GET_INST_OPCODE ip // extract opcode from rINST 5218 SET_VREG_WIDE x0, w2 // vAA<- result 5219 GOTO_OPCODE ip // jump to next instruction 5220 /* 10-13 instructions */ 5221 5222 5223/* ------------------------------ */ 5224 .balign 128 5225.L_op_sub_long_2addr: /* 0xbc */ 5226/* File: arm64/op_sub_long_2addr.S */ 5227/* File: arm64/binopWide2addr.S */ 5228 /* 5229 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5230 * that specifies an instruction that performs "x0 = x0 op x1". 5231 * This must not be a function call, as we keep w2 live across it. 5232 * 5233 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5234 * vCC (w1). Useful for integer division and modulus. 5235 * 5236 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5237 * and-long/2addr, or-long/2addr, xor-long/2addr, 5238 * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, 5239 * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr 5240 */ 5241 /* binop/2addr vA, vB */ 5242 lsr w1, wINST, #12 // w1<- B 5243 ubfx w2, wINST, #8, #4 // w2<- A 5244 GET_VREG_WIDE x1, w1 // x1<- vB 5245 GET_VREG_WIDE x0, w2 // x0<- vA 5246 .if 0 5247 cbz x1, common_errDivideByZero 5248 .endif 5249 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5250 5251 sub x0, x0, x1 // result<- op 5252 GET_INST_OPCODE ip // extract opcode from rINST 5253 SET_VREG_WIDE x0, w2 // vAA<- result 5254 GOTO_OPCODE ip // jump to next instruction 5255 /* 10-13 instructions */ 5256 5257 5258/* ------------------------------ */ 5259 .balign 128 5260.L_op_mul_long_2addr: /* 0xbd */ 5261/* File: arm64/op_mul_long_2addr.S */ 5262/* File: arm64/binopWide2addr.S */ 5263 /* 5264 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5265 * that specifies an instruction that performs "x0 = x0 op x1". 5266 * This must not be a function call, as we keep w2 live across it. 5267 * 5268 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5269 * vCC (w1). Useful for integer division and modulus. 5270 * 5271 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5272 * and-long/2addr, or-long/2addr, xor-long/2addr, 5273 * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, 5274 * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr 5275 */ 5276 /* binop/2addr vA, vB */ 5277 lsr w1, wINST, #12 // w1<- B 5278 ubfx w2, wINST, #8, #4 // w2<- A 5279 GET_VREG_WIDE x1, w1 // x1<- vB 5280 GET_VREG_WIDE x0, w2 // x0<- vA 5281 .if 0 5282 cbz x1, common_errDivideByZero 5283 .endif 5284 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5285 5286 mul x0, x0, x1 // result<- op 5287 GET_INST_OPCODE ip // extract opcode from rINST 5288 SET_VREG_WIDE x0, w2 // vAA<- result 5289 GOTO_OPCODE ip // jump to next instruction 5290 /* 10-13 instructions */ 5291 5292 5293/* ------------------------------ */ 5294 .balign 128 5295.L_op_div_long_2addr: /* 0xbe */ 5296/* File: arm64/op_div_long_2addr.S */ 5297/* File: arm64/binopWide2addr.S */ 5298 /* 5299 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5300 * that specifies an instruction that performs "x0 = x0 op x1". 5301 * This must not be a function call, as we keep w2 live across it. 5302 * 5303 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5304 * vCC (w1). Useful for integer division and modulus. 5305 * 5306 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5307 * and-long/2addr, or-long/2addr, xor-long/2addr, 5308 * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, 5309 * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr 5310 */ 5311 /* binop/2addr vA, vB */ 5312 lsr w1, wINST, #12 // w1<- B 5313 ubfx w2, wINST, #8, #4 // w2<- A 5314 GET_VREG_WIDE x1, w1 // x1<- vB 5315 GET_VREG_WIDE x0, w2 // x0<- vA 5316 .if 1 5317 cbz x1, common_errDivideByZero 5318 .endif 5319 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5320 5321 sdiv x0, x0, x1 // result<- op 5322 GET_INST_OPCODE ip // extract opcode from rINST 5323 SET_VREG_WIDE x0, w2 // vAA<- result 5324 GOTO_OPCODE ip // jump to next instruction 5325 /* 10-13 instructions */ 5326 5327 5328/* ------------------------------ */ 5329 .balign 128 5330.L_op_rem_long_2addr: /* 0xbf */ 5331/* File: arm64/op_rem_long_2addr.S */ 5332/* File: arm64/binopWide2addr.S */ 5333 /* 5334 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5335 * that specifies an instruction that performs "x0 = x0 op x1". 5336 * This must not be a function call, as we keep w2 live across it. 5337 * 5338 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5339 * vCC (w1). Useful for integer division and modulus. 5340 * 5341 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5342 * and-long/2addr, or-long/2addr, xor-long/2addr, 5343 * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, 5344 * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr 5345 */ 5346 /* binop/2addr vA, vB */ 5347 lsr w1, wINST, #12 // w1<- B 5348 ubfx w2, wINST, #8, #4 // w2<- A 5349 GET_VREG_WIDE x1, w1 // x1<- vB 5350 GET_VREG_WIDE x0, w2 // x0<- vA 5351 .if 1 5352 cbz x1, common_errDivideByZero 5353 .endif 5354 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5355 sdiv x3, x0, x1 5356 msub x0, x3, x1, x0 // result<- op 5357 GET_INST_OPCODE ip // extract opcode from rINST 5358 SET_VREG_WIDE x0, w2 // vAA<- result 5359 GOTO_OPCODE ip // jump to next instruction 5360 /* 10-13 instructions */ 5361 5362 5363/* ------------------------------ */ 5364 .balign 128 5365.L_op_and_long_2addr: /* 0xc0 */ 5366/* File: arm64/op_and_long_2addr.S */ 5367/* File: arm64/binopWide2addr.S */ 5368 /* 5369 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5370 * that specifies an instruction that performs "x0 = x0 op x1". 5371 * This must not be a function call, as we keep w2 live across it. 5372 * 5373 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5374 * vCC (w1). Useful for integer division and modulus. 5375 * 5376 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5377 * and-long/2addr, or-long/2addr, xor-long/2addr, 5378 * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, 5379 * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr 5380 */ 5381 /* binop/2addr vA, vB */ 5382 lsr w1, wINST, #12 // w1<- B 5383 ubfx w2, wINST, #8, #4 // w2<- A 5384 GET_VREG_WIDE x1, w1 // x1<- vB 5385 GET_VREG_WIDE x0, w2 // x0<- vA 5386 .if 0 5387 cbz x1, common_errDivideByZero 5388 .endif 5389 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5390 5391 and x0, x0, x1 // result<- op 5392 GET_INST_OPCODE ip // extract opcode from rINST 5393 SET_VREG_WIDE x0, w2 // vAA<- result 5394 GOTO_OPCODE ip // jump to next instruction 5395 /* 10-13 instructions */ 5396 5397 5398/* ------------------------------ */ 5399 .balign 128 5400.L_op_or_long_2addr: /* 0xc1 */ 5401/* File: arm64/op_or_long_2addr.S */ 5402/* File: arm64/binopWide2addr.S */ 5403 /* 5404 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5405 * that specifies an instruction that performs "x0 = x0 op x1". 5406 * This must not be a function call, as we keep w2 live across it. 5407 * 5408 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5409 * vCC (w1). Useful for integer division and modulus. 5410 * 5411 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5412 * and-long/2addr, or-long/2addr, xor-long/2addr, 5413 * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, 5414 * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr 5415 */ 5416 /* binop/2addr vA, vB */ 5417 lsr w1, wINST, #12 // w1<- B 5418 ubfx w2, wINST, #8, #4 // w2<- A 5419 GET_VREG_WIDE x1, w1 // x1<- vB 5420 GET_VREG_WIDE x0, w2 // x0<- vA 5421 .if 0 5422 cbz x1, common_errDivideByZero 5423 .endif 5424 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5425 5426 orr x0, x0, x1 // result<- op 5427 GET_INST_OPCODE ip // extract opcode from rINST 5428 SET_VREG_WIDE x0, w2 // vAA<- result 5429 GOTO_OPCODE ip // jump to next instruction 5430 /* 10-13 instructions */ 5431 5432 5433/* ------------------------------ */ 5434 .balign 128 5435.L_op_xor_long_2addr: /* 0xc2 */ 5436/* File: arm64/op_xor_long_2addr.S */ 5437/* File: arm64/binopWide2addr.S */ 5438 /* 5439 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5440 * that specifies an instruction that performs "x0 = x0 op x1". 5441 * This must not be a function call, as we keep w2 live across it. 5442 * 5443 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5444 * vCC (w1). Useful for integer division and modulus. 5445 * 5446 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5447 * and-long/2addr, or-long/2addr, xor-long/2addr, 5448 * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, 5449 * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr 5450 */ 5451 /* binop/2addr vA, vB */ 5452 lsr w1, wINST, #12 // w1<- B 5453 ubfx w2, wINST, #8, #4 // w2<- A 5454 GET_VREG_WIDE x1, w1 // x1<- vB 5455 GET_VREG_WIDE x0, w2 // x0<- vA 5456 .if 0 5457 cbz x1, common_errDivideByZero 5458 .endif 5459 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5460 5461 eor x0, x0, x1 // result<- op 5462 GET_INST_OPCODE ip // extract opcode from rINST 5463 SET_VREG_WIDE x0, w2 // vAA<- result 5464 GOTO_OPCODE ip // jump to next instruction 5465 /* 10-13 instructions */ 5466 5467 5468/* ------------------------------ */ 5469 .balign 128 5470.L_op_shl_long_2addr: /* 0xc3 */ 5471/* File: arm64/op_shl_long_2addr.S */ 5472/* File: arm64/shiftWide2addr.S */ 5473 /* 5474 * Generic 64-bit shift operation. 5475 */ 5476 /* binop/2addr vA, vB */ 5477 lsr w1, wINST, #12 // w1<- B 5478 ubfx w2, wINST, #8, #4 // w2<- A 5479 GET_VREG w1, w1 // x1<- vB 5480 GET_VREG_WIDE x0, w2 // x0<- vA 5481 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5482 lsl x0, x0, x1 // Do the shift. Only low 6 bits of x1 are used. 5483 GET_INST_OPCODE ip // extract opcode from rINST 5484 SET_VREG_WIDE x0, w2 // vAA<- result 5485 GOTO_OPCODE ip // jump to next instruction 5486 /* 10-13 instructions */ 5487 5488 5489/* ------------------------------ */ 5490 .balign 128 5491.L_op_shr_long_2addr: /* 0xc4 */ 5492/* File: arm64/op_shr_long_2addr.S */ 5493/* File: arm64/shiftWide2addr.S */ 5494 /* 5495 * Generic 64-bit shift operation. 5496 */ 5497 /* binop/2addr vA, vB */ 5498 lsr w1, wINST, #12 // w1<- B 5499 ubfx w2, wINST, #8, #4 // w2<- A 5500 GET_VREG w1, w1 // x1<- vB 5501 GET_VREG_WIDE x0, w2 // x0<- vA 5502 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5503 asr x0, x0, x1 // Do the shift. Only low 6 bits of x1 are used. 5504 GET_INST_OPCODE ip // extract opcode from rINST 5505 SET_VREG_WIDE x0, w2 // vAA<- result 5506 GOTO_OPCODE ip // jump to next instruction 5507 /* 10-13 instructions */ 5508 5509 5510/* ------------------------------ */ 5511 .balign 128 5512.L_op_ushr_long_2addr: /* 0xc5 */ 5513/* File: arm64/op_ushr_long_2addr.S */ 5514/* File: arm64/shiftWide2addr.S */ 5515 /* 5516 * Generic 64-bit shift operation. 5517 */ 5518 /* binop/2addr vA, vB */ 5519 lsr w1, wINST, #12 // w1<- B 5520 ubfx w2, wINST, #8, #4 // w2<- A 5521 GET_VREG w1, w1 // x1<- vB 5522 GET_VREG_WIDE x0, w2 // x0<- vA 5523 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5524 lsr x0, x0, x1 // Do the shift. Only low 6 bits of x1 are used. 5525 GET_INST_OPCODE ip // extract opcode from rINST 5526 SET_VREG_WIDE x0, w2 // vAA<- result 5527 GOTO_OPCODE ip // jump to next instruction 5528 /* 10-13 instructions */ 5529 5530 5531/* ------------------------------ */ 5532 .balign 128 5533.L_op_add_float_2addr: /* 0xc6 */ 5534/* File: arm64/op_add_float_2addr.S */ 5535/* File: arm64/fbinop2addr.S */ 5536 /* 5537 * Generic 32-bit floating point "/2addr" binary operation. Provide 5538 * an "instr" line that specifies an instruction that performs 5539 * "s2 = s0 op s1". 5540 * 5541 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 5542 */ 5543 /* binop/2addr vA, vB */ 5544 lsr w3, wINST, #12 // w3<- B 5545 ubfx w9, wINST, #8, #4 // w9<- A 5546 GET_VREG s1, w3 5547 GET_VREG s0, w9 5548 fadd s2, s0, s1 // s2<- op 5549 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5550 GET_INST_OPCODE ip // extract opcode from rINST 5551 SET_VREG s2, w9 5552 GOTO_OPCODE ip // jump to next instruction 5553 5554 5555/* ------------------------------ */ 5556 .balign 128 5557.L_op_sub_float_2addr: /* 0xc7 */ 5558/* File: arm64/op_sub_float_2addr.S */ 5559/* File: arm64/fbinop2addr.S */ 5560 /* 5561 * Generic 32-bit floating point "/2addr" binary operation. Provide 5562 * an "instr" line that specifies an instruction that performs 5563 * "s2 = s0 op s1". 5564 * 5565 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 5566 */ 5567 /* binop/2addr vA, vB */ 5568 lsr w3, wINST, #12 // w3<- B 5569 ubfx w9, wINST, #8, #4 // w9<- A 5570 GET_VREG s1, w3 5571 GET_VREG s0, w9 5572 fsub s2, s0, s1 // s2<- op 5573 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5574 GET_INST_OPCODE ip // extract opcode from rINST 5575 SET_VREG s2, w9 5576 GOTO_OPCODE ip // jump to next instruction 5577 5578 5579/* ------------------------------ */ 5580 .balign 128 5581.L_op_mul_float_2addr: /* 0xc8 */ 5582/* File: arm64/op_mul_float_2addr.S */ 5583/* File: arm64/fbinop2addr.S */ 5584 /* 5585 * Generic 32-bit floating point "/2addr" binary operation. Provide 5586 * an "instr" line that specifies an instruction that performs 5587 * "s2 = s0 op s1". 5588 * 5589 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 5590 */ 5591 /* binop/2addr vA, vB */ 5592 lsr w3, wINST, #12 // w3<- B 5593 ubfx w9, wINST, #8, #4 // w9<- A 5594 GET_VREG s1, w3 5595 GET_VREG s0, w9 5596 fmul s2, s0, s1 // s2<- op 5597 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5598 GET_INST_OPCODE ip // extract opcode from rINST 5599 SET_VREG s2, w9 5600 GOTO_OPCODE ip // jump to next instruction 5601 5602 5603/* ------------------------------ */ 5604 .balign 128 5605.L_op_div_float_2addr: /* 0xc9 */ 5606/* File: arm64/op_div_float_2addr.S */ 5607/* File: arm64/fbinop2addr.S */ 5608 /* 5609 * Generic 32-bit floating point "/2addr" binary operation. Provide 5610 * an "instr" line that specifies an instruction that performs 5611 * "s2 = s0 op s1". 5612 * 5613 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 5614 */ 5615 /* binop/2addr vA, vB */ 5616 lsr w3, wINST, #12 // w3<- B 5617 ubfx w9, wINST, #8, #4 // w9<- A 5618 GET_VREG s1, w3 5619 GET_VREG s0, w9 5620 fdiv s2, s0, s1 // s2<- op 5621 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5622 GET_INST_OPCODE ip // extract opcode from rINST 5623 SET_VREG s2, w9 5624 GOTO_OPCODE ip // jump to next instruction 5625 5626 5627/* ------------------------------ */ 5628 .balign 128 5629.L_op_rem_float_2addr: /* 0xca */ 5630/* File: arm64/op_rem_float_2addr.S */ 5631 /* rem vA, vB */ 5632 lsr w3, wINST, #12 // w3<- B 5633 ubfx w9, wINST, #8, #4 // w9<- A 5634 GET_VREG s1, w3 5635 GET_VREG s0, w9 5636 bl fmodf 5637 ubfx w9, wINST, #8, #4 // w9<- A 5638 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5639 GET_INST_OPCODE ip // extract opcode from rINST 5640 SET_VREG s0, w9 5641 GOTO_OPCODE ip // jump to next instruction 5642 5643/* ------------------------------ */ 5644 .balign 128 5645.L_op_add_double_2addr: /* 0xcb */ 5646/* File: arm64/op_add_double_2addr.S */ 5647/* File: arm64/binopWide2addr.S */ 5648 /* 5649 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5650 * that specifies an instruction that performs "x0 = x0 op x1". 5651 * This must not be a function call, as we keep w2 live across it. 5652 * 5653 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5654 * vCC (w1). Useful for integer division and modulus. 5655 * 5656 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5657 * and-long/2addr, or-long/2addr, xor-long/2addr, 5658 * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, 5659 * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr 5660 */ 5661 /* binop/2addr vA, vB */ 5662 lsr w1, wINST, #12 // w1<- B 5663 ubfx w2, wINST, #8, #4 // w2<- A 5664 GET_VREG_WIDE d1, w1 // x1<- vB 5665 GET_VREG_WIDE d0, w2 // x0<- vA 5666 .if 0 5667 cbz d1, common_errDivideByZero 5668 .endif 5669 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5670 5671 fadd d0, d0, d1 // result<- op 5672 GET_INST_OPCODE ip // extract opcode from rINST 5673 SET_VREG_WIDE d0, w2 // vAA<- result 5674 GOTO_OPCODE ip // jump to next instruction 5675 /* 10-13 instructions */ 5676 5677 5678/* ------------------------------ */ 5679 .balign 128 5680.L_op_sub_double_2addr: /* 0xcc */ 5681/* File: arm64/op_sub_double_2addr.S */ 5682/* File: arm64/binopWide2addr.S */ 5683 /* 5684 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5685 * that specifies an instruction that performs "x0 = x0 op x1". 5686 * This must not be a function call, as we keep w2 live across it. 5687 * 5688 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5689 * vCC (w1). Useful for integer division and modulus. 5690 * 5691 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5692 * and-long/2addr, or-long/2addr, xor-long/2addr, 5693 * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, 5694 * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr 5695 */ 5696 /* binop/2addr vA, vB */ 5697 lsr w1, wINST, #12 // w1<- B 5698 ubfx w2, wINST, #8, #4 // w2<- A 5699 GET_VREG_WIDE d1, w1 // x1<- vB 5700 GET_VREG_WIDE d0, w2 // x0<- vA 5701 .if 0 5702 cbz d1, common_errDivideByZero 5703 .endif 5704 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5705 5706 fsub d0, d0, d1 // result<- op 5707 GET_INST_OPCODE ip // extract opcode from rINST 5708 SET_VREG_WIDE d0, w2 // vAA<- result 5709 GOTO_OPCODE ip // jump to next instruction 5710 /* 10-13 instructions */ 5711 5712 5713/* ------------------------------ */ 5714 .balign 128 5715.L_op_mul_double_2addr: /* 0xcd */ 5716/* File: arm64/op_mul_double_2addr.S */ 5717/* File: arm64/binopWide2addr.S */ 5718 /* 5719 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5720 * that specifies an instruction that performs "x0 = x0 op x1". 5721 * This must not be a function call, as we keep w2 live across it. 5722 * 5723 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5724 * vCC (w1). Useful for integer division and modulus. 5725 * 5726 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5727 * and-long/2addr, or-long/2addr, xor-long/2addr, 5728 * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, 5729 * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr 5730 */ 5731 /* binop/2addr vA, vB */ 5732 lsr w1, wINST, #12 // w1<- B 5733 ubfx w2, wINST, #8, #4 // w2<- A 5734 GET_VREG_WIDE d1, w1 // x1<- vB 5735 GET_VREG_WIDE d0, w2 // x0<- vA 5736 .if 0 5737 cbz d1, common_errDivideByZero 5738 .endif 5739 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5740 5741 fmul d0, d0, d1 // result<- op 5742 GET_INST_OPCODE ip // extract opcode from rINST 5743 SET_VREG_WIDE d0, w2 // vAA<- result 5744 GOTO_OPCODE ip // jump to next instruction 5745 /* 10-13 instructions */ 5746 5747 5748/* ------------------------------ */ 5749 .balign 128 5750.L_op_div_double_2addr: /* 0xce */ 5751/* File: arm64/op_div_double_2addr.S */ 5752/* File: arm64/binopWide2addr.S */ 5753 /* 5754 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5755 * that specifies an instruction that performs "x0 = x0 op x1". 5756 * This must not be a function call, as we keep w2 live across it. 5757 * 5758 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5759 * vCC (w1). Useful for integer division and modulus. 5760 * 5761 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5762 * and-long/2addr, or-long/2addr, xor-long/2addr, 5763 * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, 5764 * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr 5765 */ 5766 /* binop/2addr vA, vB */ 5767 lsr w1, wINST, #12 // w1<- B 5768 ubfx w2, wINST, #8, #4 // w2<- A 5769 GET_VREG_WIDE d1, w1 // x1<- vB 5770 GET_VREG_WIDE d0, w2 // x0<- vA 5771 .if 0 5772 cbz d1, common_errDivideByZero 5773 .endif 5774 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5775 5776 fdiv d0, d0, d1 // result<- op 5777 GET_INST_OPCODE ip // extract opcode from rINST 5778 SET_VREG_WIDE d0, w2 // vAA<- result 5779 GOTO_OPCODE ip // jump to next instruction 5780 /* 10-13 instructions */ 5781 5782 5783/* ------------------------------ */ 5784 .balign 128 5785.L_op_rem_double_2addr: /* 0xcf */ 5786/* File: arm64/op_rem_double_2addr.S */ 5787 /* rem vA, vB */ 5788 lsr w1, wINST, #12 // w1<- B 5789 ubfx w2, wINST, #8, #4 // w2<- A 5790 GET_VREG_WIDE d1, w1 // d1<- vB 5791 GET_VREG_WIDE d0, w2 // d0<- vA 5792 bl fmod 5793 ubfx w2, wINST, #8, #4 // w2<- A (need to reload - killed across call) 5794 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5795 GET_INST_OPCODE ip // extract opcode from rINST 5796 SET_VREG_WIDE d0, w2 // vAA<- result 5797 GOTO_OPCODE ip // jump to next instruction 5798 /* 10-13 instructions */ 5799 5800/* ------------------------------ */ 5801 .balign 128 5802.L_op_add_int_lit16: /* 0xd0 */ 5803/* File: arm64/op_add_int_lit16.S */ 5804/* File: arm64/binopLit16.S */ 5805 /* 5806 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 5807 * that specifies an instruction that performs "result = w0 op w1". 5808 * This could be an ARM instruction or a function call. (If the result 5809 * comes back in a register other than w0, you can override "result".) 5810 * 5811 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5812 * vCC (w1). Useful for integer division and modulus. 5813 * 5814 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 5815 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 5816 */ 5817 /* binop/lit16 vA, vB, #+CCCC */ 5818 FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) 5819 lsr w2, wINST, #12 // w2<- B 5820 ubfx w9, wINST, #8, #4 // w9<- A 5821 GET_VREG w0, w2 // w0<- vB 5822 .if 0 5823 cbz w1, common_errDivideByZero 5824 .endif 5825 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 5826 5827 add w0, w0, w1 // w0<- op, w0-w3 changed 5828 GET_INST_OPCODE ip // extract opcode from rINST 5829 SET_VREG w0, w9 // vAA<- w0 5830 GOTO_OPCODE ip // jump to next instruction 5831 /* 10-13 instructions */ 5832 5833 5834/* ------------------------------ */ 5835 .balign 128 5836.L_op_rsub_int: /* 0xd1 */ 5837/* File: arm64/op_rsub_int.S */ 5838/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ 5839/* File: arm64/binopLit16.S */ 5840 /* 5841 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 5842 * that specifies an instruction that performs "result = w0 op w1". 5843 * This could be an ARM instruction or a function call. (If the result 5844 * comes back in a register other than w0, you can override "result".) 5845 * 5846 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5847 * vCC (w1). Useful for integer division and modulus. 5848 * 5849 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 5850 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 5851 */ 5852 /* binop/lit16 vA, vB, #+CCCC */ 5853 FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) 5854 lsr w2, wINST, #12 // w2<- B 5855 ubfx w9, wINST, #8, #4 // w9<- A 5856 GET_VREG w0, w2 // w0<- vB 5857 .if 0 5858 cbz w1, common_errDivideByZero 5859 .endif 5860 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 5861 5862 sub w0, w1, w0 // w0<- op, w0-w3 changed 5863 GET_INST_OPCODE ip // extract opcode from rINST 5864 SET_VREG w0, w9 // vAA<- w0 5865 GOTO_OPCODE ip // jump to next instruction 5866 /* 10-13 instructions */ 5867 5868 5869/* ------------------------------ */ 5870 .balign 128 5871.L_op_mul_int_lit16: /* 0xd2 */ 5872/* File: arm64/op_mul_int_lit16.S */ 5873/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ 5874/* File: arm64/binopLit16.S */ 5875 /* 5876 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 5877 * that specifies an instruction that performs "result = w0 op w1". 5878 * This could be an ARM instruction or a function call. (If the result 5879 * comes back in a register other than w0, you can override "result".) 5880 * 5881 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5882 * vCC (w1). Useful for integer division and modulus. 5883 * 5884 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 5885 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 5886 */ 5887 /* binop/lit16 vA, vB, #+CCCC */ 5888 FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) 5889 lsr w2, wINST, #12 // w2<- B 5890 ubfx w9, wINST, #8, #4 // w9<- A 5891 GET_VREG w0, w2 // w0<- vB 5892 .if 0 5893 cbz w1, common_errDivideByZero 5894 .endif 5895 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 5896 5897 mul w0, w1, w0 // w0<- op, w0-w3 changed 5898 GET_INST_OPCODE ip // extract opcode from rINST 5899 SET_VREG w0, w9 // vAA<- w0 5900 GOTO_OPCODE ip // jump to next instruction 5901 /* 10-13 instructions */ 5902 5903 5904/* ------------------------------ */ 5905 .balign 128 5906.L_op_div_int_lit16: /* 0xd3 */ 5907/* File: arm64/op_div_int_lit16.S */ 5908/* File: arm64/binopLit16.S */ 5909 /* 5910 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 5911 * that specifies an instruction that performs "result = w0 op w1". 5912 * This could be an ARM instruction or a function call. (If the result 5913 * comes back in a register other than w0, you can override "result".) 5914 * 5915 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5916 * vCC (w1). Useful for integer division and modulus. 5917 * 5918 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 5919 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 5920 */ 5921 /* binop/lit16 vA, vB, #+CCCC */ 5922 FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) 5923 lsr w2, wINST, #12 // w2<- B 5924 ubfx w9, wINST, #8, #4 // w9<- A 5925 GET_VREG w0, w2 // w0<- vB 5926 .if 1 5927 cbz w1, common_errDivideByZero 5928 .endif 5929 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 5930 5931 sdiv w0, w0, w1 // w0<- op, w0-w3 changed 5932 GET_INST_OPCODE ip // extract opcode from rINST 5933 SET_VREG w0, w9 // vAA<- w0 5934 GOTO_OPCODE ip // jump to next instruction 5935 /* 10-13 instructions */ 5936 5937 5938/* ------------------------------ */ 5939 .balign 128 5940.L_op_rem_int_lit16: /* 0xd4 */ 5941/* File: arm64/op_rem_int_lit16.S */ 5942/* File: arm64/binopLit16.S */ 5943 /* 5944 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 5945 * that specifies an instruction that performs "result = w0 op w1". 5946 * This could be an ARM instruction or a function call. (If the result 5947 * comes back in a register other than w0, you can override "result".) 5948 * 5949 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5950 * vCC (w1). Useful for integer division and modulus. 5951 * 5952 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 5953 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 5954 */ 5955 /* binop/lit16 vA, vB, #+CCCC */ 5956 FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) 5957 lsr w2, wINST, #12 // w2<- B 5958 ubfx w9, wINST, #8, #4 // w9<- A 5959 GET_VREG w0, w2 // w0<- vB 5960 .if 1 5961 cbz w1, common_errDivideByZero 5962 .endif 5963 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 5964 sdiv w3, w0, w1 5965 msub w0, w3, w1, w0 // w0<- op, w0-w3 changed 5966 GET_INST_OPCODE ip // extract opcode from rINST 5967 SET_VREG w0, w9 // vAA<- w0 5968 GOTO_OPCODE ip // jump to next instruction 5969 /* 10-13 instructions */ 5970 5971 5972/* ------------------------------ */ 5973 .balign 128 5974.L_op_and_int_lit16: /* 0xd5 */ 5975/* File: arm64/op_and_int_lit16.S */ 5976/* File: arm64/binopLit16.S */ 5977 /* 5978 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 5979 * that specifies an instruction that performs "result = w0 op w1". 5980 * This could be an ARM instruction or a function call. (If the result 5981 * comes back in a register other than w0, you can override "result".) 5982 * 5983 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5984 * vCC (w1). Useful for integer division and modulus. 5985 * 5986 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 5987 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 5988 */ 5989 /* binop/lit16 vA, vB, #+CCCC */ 5990 FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) 5991 lsr w2, wINST, #12 // w2<- B 5992 ubfx w9, wINST, #8, #4 // w9<- A 5993 GET_VREG w0, w2 // w0<- vB 5994 .if 0 5995 cbz w1, common_errDivideByZero 5996 .endif 5997 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 5998 5999 and w0, w0, w1 // w0<- op, w0-w3 changed 6000 GET_INST_OPCODE ip // extract opcode from rINST 6001 SET_VREG w0, w9 // vAA<- w0 6002 GOTO_OPCODE ip // jump to next instruction 6003 /* 10-13 instructions */ 6004 6005 6006/* ------------------------------ */ 6007 .balign 128 6008.L_op_or_int_lit16: /* 0xd6 */ 6009/* File: arm64/op_or_int_lit16.S */ 6010/* File: arm64/binopLit16.S */ 6011 /* 6012 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6013 * that specifies an instruction that performs "result = w0 op w1". 6014 * This could be an ARM instruction or a function call. (If the result 6015 * comes back in a register other than w0, you can override "result".) 6016 * 6017 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6018 * vCC (w1). Useful for integer division and modulus. 6019 * 6020 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6021 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6022 */ 6023 /* binop/lit16 vA, vB, #+CCCC */ 6024 FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) 6025 lsr w2, wINST, #12 // w2<- B 6026 ubfx w9, wINST, #8, #4 // w9<- A 6027 GET_VREG w0, w2 // w0<- vB 6028 .if 0 6029 cbz w1, common_errDivideByZero 6030 .endif 6031 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6032 6033 orr w0, w0, w1 // w0<- op, w0-w3 changed 6034 GET_INST_OPCODE ip // extract opcode from rINST 6035 SET_VREG w0, w9 // vAA<- w0 6036 GOTO_OPCODE ip // jump to next instruction 6037 /* 10-13 instructions */ 6038 6039 6040/* ------------------------------ */ 6041 .balign 128 6042.L_op_xor_int_lit16: /* 0xd7 */ 6043/* File: arm64/op_xor_int_lit16.S */ 6044/* File: arm64/binopLit16.S */ 6045 /* 6046 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6047 * that specifies an instruction that performs "result = w0 op w1". 6048 * This could be an ARM instruction or a function call. (If the result 6049 * comes back in a register other than w0, you can override "result".) 6050 * 6051 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6052 * vCC (w1). Useful for integer division and modulus. 6053 * 6054 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6055 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6056 */ 6057 /* binop/lit16 vA, vB, #+CCCC */ 6058 FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) 6059 lsr w2, wINST, #12 // w2<- B 6060 ubfx w9, wINST, #8, #4 // w9<- A 6061 GET_VREG w0, w2 // w0<- vB 6062 .if 0 6063 cbz w1, common_errDivideByZero 6064 .endif 6065 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6066 6067 eor w0, w0, w1 // w0<- op, w0-w3 changed 6068 GET_INST_OPCODE ip // extract opcode from rINST 6069 SET_VREG w0, w9 // vAA<- w0 6070 GOTO_OPCODE ip // jump to next instruction 6071 /* 10-13 instructions */ 6072 6073 6074/* ------------------------------ */ 6075 .balign 128 6076.L_op_add_int_lit8: /* 0xd8 */ 6077/* File: arm64/op_add_int_lit8.S */ 6078/* File: arm64/binopLit8.S */ 6079 /* 6080 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6081 * that specifies an instruction that performs "result = w0 op w1". 6082 * This could be an ARM instruction or a function call. (If the result 6083 * comes back in a register other than w0, you can override "result".) 6084 * 6085 * You can override "extract" if the extraction of the literal value 6086 * from w3 to w1 is not the default "asr w1, w3, #8". The extraction 6087 * can be omitted completely if the shift is embedded in "instr". 6088 * 6089 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6090 * vCC (w1). Useful for integer division and modulus. 6091 * 6092 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6093 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6094 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6095 */ 6096 /* binop/lit8 vAA, vBB, #+CC */ 6097 FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) 6098 lsr w9, wINST, #8 // w9<- AA 6099 and w2, w3, #255 // w2<- BB 6100 GET_VREG w0, w2 // w0<- vBB 6101 // optional; typically w1<- ssssssCC (sign extended) 6102 .if 0 6103 cbz w1, common_errDivideByZero 6104 .endif 6105 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6106 // optional op; may set condition codes 6107 add w0, w0, w3, asr #8 // w0<- op, w0-w3 changed 6108 GET_INST_OPCODE ip // extract opcode from rINST 6109 SET_VREG w0, w9 // vAA<- w0 6110 GOTO_OPCODE ip // jump to next instruction 6111 /* 10-12 instructions */ 6112 6113 6114/* ------------------------------ */ 6115 .balign 128 6116.L_op_rsub_int_lit8: /* 0xd9 */ 6117/* File: arm64/op_rsub_int_lit8.S */ 6118/* File: arm64/binopLit8.S */ 6119 /* 6120 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6121 * that specifies an instruction that performs "result = w0 op w1". 6122 * This could be an ARM instruction or a function call. (If the result 6123 * comes back in a register other than w0, you can override "result".) 6124 * 6125 * You can override "extract" if the extraction of the literal value 6126 * from w3 to w1 is not the default "asr w1, w3, #8". The extraction 6127 * can be omitted completely if the shift is embedded in "instr". 6128 * 6129 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6130 * vCC (w1). Useful for integer division and modulus. 6131 * 6132 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6133 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6134 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6135 */ 6136 /* binop/lit8 vAA, vBB, #+CC */ 6137 FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) 6138 lsr w9, wINST, #8 // w9<- AA 6139 and w2, w3, #255 // w2<- BB 6140 GET_VREG w0, w2 // w0<- vBB 6141 asr w1, w3, #8 // optional; typically w1<- ssssssCC (sign extended) 6142 .if 0 6143 cbz w1, common_errDivideByZero 6144 .endif 6145 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6146 // optional op; may set condition codes 6147 sub w0, w1, w0 // w0<- op, w0-w3 changed 6148 GET_INST_OPCODE ip // extract opcode from rINST 6149 SET_VREG w0, w9 // vAA<- w0 6150 GOTO_OPCODE ip // jump to next instruction 6151 /* 10-12 instructions */ 6152 6153 6154/* ------------------------------ */ 6155 .balign 128 6156.L_op_mul_int_lit8: /* 0xda */ 6157/* File: arm64/op_mul_int_lit8.S */ 6158/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ 6159/* File: arm64/binopLit8.S */ 6160 /* 6161 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6162 * that specifies an instruction that performs "result = w0 op w1". 6163 * This could be an ARM instruction or a function call. (If the result 6164 * comes back in a register other than w0, you can override "result".) 6165 * 6166 * You can override "extract" if the extraction of the literal value 6167 * from w3 to w1 is not the default "asr w1, w3, #8". The extraction 6168 * can be omitted completely if the shift is embedded in "instr". 6169 * 6170 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6171 * vCC (w1). Useful for integer division and modulus. 6172 * 6173 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6174 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6175 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6176 */ 6177 /* binop/lit8 vAA, vBB, #+CC */ 6178 FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) 6179 lsr w9, wINST, #8 // w9<- AA 6180 and w2, w3, #255 // w2<- BB 6181 GET_VREG w0, w2 // w0<- vBB 6182 asr w1, w3, #8 // optional; typically w1<- ssssssCC (sign extended) 6183 .if 0 6184 cbz w1, common_errDivideByZero 6185 .endif 6186 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6187 // optional op; may set condition codes 6188 mul w0, w1, w0 // w0<- op, w0-w3 changed 6189 GET_INST_OPCODE ip // extract opcode from rINST 6190 SET_VREG w0, w9 // vAA<- w0 6191 GOTO_OPCODE ip // jump to next instruction 6192 /* 10-12 instructions */ 6193 6194 6195/* ------------------------------ */ 6196 .balign 128 6197.L_op_div_int_lit8: /* 0xdb */ 6198/* File: arm64/op_div_int_lit8.S */ 6199/* File: arm64/binopLit8.S */ 6200 /* 6201 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6202 * that specifies an instruction that performs "result = w0 op w1". 6203 * This could be an ARM instruction or a function call. (If the result 6204 * comes back in a register other than w0, you can override "result".) 6205 * 6206 * You can override "extract" if the extraction of the literal value 6207 * from w3 to w1 is not the default "asr w1, w3, #8". The extraction 6208 * can be omitted completely if the shift is embedded in "instr". 6209 * 6210 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6211 * vCC (w1). Useful for integer division and modulus. 6212 * 6213 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6214 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6215 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6216 */ 6217 /* binop/lit8 vAA, vBB, #+CC */ 6218 FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) 6219 lsr w9, wINST, #8 // w9<- AA 6220 and w2, w3, #255 // w2<- BB 6221 GET_VREG w0, w2 // w0<- vBB 6222 asr w1, w3, #8 // optional; typically w1<- ssssssCC (sign extended) 6223 .if 1 6224 cbz w1, common_errDivideByZero 6225 .endif 6226 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6227 // optional op; may set condition codes 6228 sdiv w0, w0, w1 // w0<- op, w0-w3 changed 6229 GET_INST_OPCODE ip // extract opcode from rINST 6230 SET_VREG w0, w9 // vAA<- w0 6231 GOTO_OPCODE ip // jump to next instruction 6232 /* 10-12 instructions */ 6233 6234 6235/* ------------------------------ */ 6236 .balign 128 6237.L_op_rem_int_lit8: /* 0xdc */ 6238/* File: arm64/op_rem_int_lit8.S */ 6239/* File: arm64/binopLit8.S */ 6240 /* 6241 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6242 * that specifies an instruction that performs "result = w0 op w1". 6243 * This could be an ARM instruction or a function call. (If the result 6244 * comes back in a register other than w0, you can override "result".) 6245 * 6246 * You can override "extract" if the extraction of the literal value 6247 * from w3 to w1 is not the default "asr w1, w3, #8". The extraction 6248 * can be omitted completely if the shift is embedded in "instr". 6249 * 6250 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6251 * vCC (w1). Useful for integer division and modulus. 6252 * 6253 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6254 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6255 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6256 */ 6257 /* binop/lit8 vAA, vBB, #+CC */ 6258 FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) 6259 lsr w9, wINST, #8 // w9<- AA 6260 and w2, w3, #255 // w2<- BB 6261 GET_VREG w0, w2 // w0<- vBB 6262 asr w1, w3, #8 // optional; typically w1<- ssssssCC (sign extended) 6263 .if 1 6264 cbz w1, common_errDivideByZero 6265 .endif 6266 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6267 sdiv w3, w0, w1 // optional op; may set condition codes 6268 msub w0, w3, w1, w0 // w0<- op, w0-w3 changed 6269 GET_INST_OPCODE ip // extract opcode from rINST 6270 SET_VREG w0, w9 // vAA<- w0 6271 GOTO_OPCODE ip // jump to next instruction 6272 /* 10-12 instructions */ 6273 6274 6275/* ------------------------------ */ 6276 .balign 128 6277.L_op_and_int_lit8: /* 0xdd */ 6278/* File: arm64/op_and_int_lit8.S */ 6279/* File: arm64/binopLit8.S */ 6280 /* 6281 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6282 * that specifies an instruction that performs "result = w0 op w1". 6283 * This could be an ARM instruction or a function call. (If the result 6284 * comes back in a register other than w0, you can override "result".) 6285 * 6286 * You can override "extract" if the extraction of the literal value 6287 * from w3 to w1 is not the default "asr w1, w3, #8". The extraction 6288 * can be omitted completely if the shift is embedded in "instr". 6289 * 6290 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6291 * vCC (w1). Useful for integer division and modulus. 6292 * 6293 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6294 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6295 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6296 */ 6297 /* binop/lit8 vAA, vBB, #+CC */ 6298 FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) 6299 lsr w9, wINST, #8 // w9<- AA 6300 and w2, w3, #255 // w2<- BB 6301 GET_VREG w0, w2 // w0<- vBB 6302 // optional; typically w1<- ssssssCC (sign extended) 6303 .if 0 6304 cbz w1, common_errDivideByZero 6305 .endif 6306 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6307 // optional op; may set condition codes 6308 and w0, w0, w3, asr #8 // w0<- op, w0-w3 changed 6309 GET_INST_OPCODE ip // extract opcode from rINST 6310 SET_VREG w0, w9 // vAA<- w0 6311 GOTO_OPCODE ip // jump to next instruction 6312 /* 10-12 instructions */ 6313 6314 6315/* ------------------------------ */ 6316 .balign 128 6317.L_op_or_int_lit8: /* 0xde */ 6318/* File: arm64/op_or_int_lit8.S */ 6319/* File: arm64/binopLit8.S */ 6320 /* 6321 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6322 * that specifies an instruction that performs "result = w0 op w1". 6323 * This could be an ARM instruction or a function call. (If the result 6324 * comes back in a register other than w0, you can override "result".) 6325 * 6326 * You can override "extract" if the extraction of the literal value 6327 * from w3 to w1 is not the default "asr w1, w3, #8". The extraction 6328 * can be omitted completely if the shift is embedded in "instr". 6329 * 6330 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6331 * vCC (w1). Useful for integer division and modulus. 6332 * 6333 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6334 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6335 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6336 */ 6337 /* binop/lit8 vAA, vBB, #+CC */ 6338 FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) 6339 lsr w9, wINST, #8 // w9<- AA 6340 and w2, w3, #255 // w2<- BB 6341 GET_VREG w0, w2 // w0<- vBB 6342 // optional; typically w1<- ssssssCC (sign extended) 6343 .if 0 6344 cbz w1, common_errDivideByZero 6345 .endif 6346 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6347 // optional op; may set condition codes 6348 orr w0, w0, w3, asr #8 // w0<- op, w0-w3 changed 6349 GET_INST_OPCODE ip // extract opcode from rINST 6350 SET_VREG w0, w9 // vAA<- w0 6351 GOTO_OPCODE ip // jump to next instruction 6352 /* 10-12 instructions */ 6353 6354 6355/* ------------------------------ */ 6356 .balign 128 6357.L_op_xor_int_lit8: /* 0xdf */ 6358/* File: arm64/op_xor_int_lit8.S */ 6359/* File: arm64/binopLit8.S */ 6360 /* 6361 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6362 * that specifies an instruction that performs "result = w0 op w1". 6363 * This could be an ARM instruction or a function call. (If the result 6364 * comes back in a register other than w0, you can override "result".) 6365 * 6366 * You can override "extract" if the extraction of the literal value 6367 * from w3 to w1 is not the default "asr w1, w3, #8". The extraction 6368 * can be omitted completely if the shift is embedded in "instr". 6369 * 6370 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6371 * vCC (w1). Useful for integer division and modulus. 6372 * 6373 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6374 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6375 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6376 */ 6377 /* binop/lit8 vAA, vBB, #+CC */ 6378 FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) 6379 lsr w9, wINST, #8 // w9<- AA 6380 and w2, w3, #255 // w2<- BB 6381 GET_VREG w0, w2 // w0<- vBB 6382 // optional; typically w1<- ssssssCC (sign extended) 6383 .if 0 6384 cbz w1, common_errDivideByZero 6385 .endif 6386 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6387 // optional op; may set condition codes 6388 eor w0, w0, w3, asr #8 // w0<- op, w0-w3 changed 6389 GET_INST_OPCODE ip // extract opcode from rINST 6390 SET_VREG w0, w9 // vAA<- w0 6391 GOTO_OPCODE ip // jump to next instruction 6392 /* 10-12 instructions */ 6393 6394 6395/* ------------------------------ */ 6396 .balign 128 6397.L_op_shl_int_lit8: /* 0xe0 */ 6398/* File: arm64/op_shl_int_lit8.S */ 6399/* File: arm64/binopLit8.S */ 6400 /* 6401 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6402 * that specifies an instruction that performs "result = w0 op w1". 6403 * This could be an ARM instruction or a function call. (If the result 6404 * comes back in a register other than w0, you can override "result".) 6405 * 6406 * You can override "extract" if the extraction of the literal value 6407 * from w3 to w1 is not the default "asr w1, w3, #8". The extraction 6408 * can be omitted completely if the shift is embedded in "instr". 6409 * 6410 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6411 * vCC (w1). Useful for integer division and modulus. 6412 * 6413 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6414 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6415 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6416 */ 6417 /* binop/lit8 vAA, vBB, #+CC */ 6418 FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) 6419 lsr w9, wINST, #8 // w9<- AA 6420 and w2, w3, #255 // w2<- BB 6421 GET_VREG w0, w2 // w0<- vBB 6422 ubfx w1, w3, #8, #5 // optional; typically w1<- ssssssCC (sign extended) 6423 .if 0 6424 cbz w1, common_errDivideByZero 6425 .endif 6426 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6427 // optional op; may set condition codes 6428 lsl w0, w0, w1 // w0<- op, w0-w3 changed 6429 GET_INST_OPCODE ip // extract opcode from rINST 6430 SET_VREG w0, w9 // vAA<- w0 6431 GOTO_OPCODE ip // jump to next instruction 6432 /* 10-12 instructions */ 6433 6434 6435/* ------------------------------ */ 6436 .balign 128 6437.L_op_shr_int_lit8: /* 0xe1 */ 6438/* File: arm64/op_shr_int_lit8.S */ 6439/* File: arm64/binopLit8.S */ 6440 /* 6441 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6442 * that specifies an instruction that performs "result = w0 op w1". 6443 * This could be an ARM instruction or a function call. (If the result 6444 * comes back in a register other than w0, you can override "result".) 6445 * 6446 * You can override "extract" if the extraction of the literal value 6447 * from w3 to w1 is not the default "asr w1, w3, #8". The extraction 6448 * can be omitted completely if the shift is embedded in "instr". 6449 * 6450 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6451 * vCC (w1). Useful for integer division and modulus. 6452 * 6453 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6454 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6455 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6456 */ 6457 /* binop/lit8 vAA, vBB, #+CC */ 6458 FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) 6459 lsr w9, wINST, #8 // w9<- AA 6460 and w2, w3, #255 // w2<- BB 6461 GET_VREG w0, w2 // w0<- vBB 6462 ubfx w1, w3, #8, #5 // optional; typically w1<- ssssssCC (sign extended) 6463 .if 0 6464 cbz w1, common_errDivideByZero 6465 .endif 6466 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6467 // optional op; may set condition codes 6468 asr w0, w0, w1 // w0<- op, w0-w3 changed 6469 GET_INST_OPCODE ip // extract opcode from rINST 6470 SET_VREG w0, w9 // vAA<- w0 6471 GOTO_OPCODE ip // jump to next instruction 6472 /* 10-12 instructions */ 6473 6474 6475/* ------------------------------ */ 6476 .balign 128 6477.L_op_ushr_int_lit8: /* 0xe2 */ 6478/* File: arm64/op_ushr_int_lit8.S */ 6479/* File: arm64/binopLit8.S */ 6480 /* 6481 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6482 * that specifies an instruction that performs "result = w0 op w1". 6483 * This could be an ARM instruction or a function call. (If the result 6484 * comes back in a register other than w0, you can override "result".) 6485 * 6486 * You can override "extract" if the extraction of the literal value 6487 * from w3 to w1 is not the default "asr w1, w3, #8". The extraction 6488 * can be omitted completely if the shift is embedded in "instr". 6489 * 6490 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6491 * vCC (w1). Useful for integer division and modulus. 6492 * 6493 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6494 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6495 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6496 */ 6497 /* binop/lit8 vAA, vBB, #+CC */ 6498 FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) 6499 lsr w9, wINST, #8 // w9<- AA 6500 and w2, w3, #255 // w2<- BB 6501 GET_VREG w0, w2 // w0<- vBB 6502 ubfx w1, w3, #8, #5 // optional; typically w1<- ssssssCC (sign extended) 6503 .if 0 6504 cbz w1, common_errDivideByZero 6505 .endif 6506 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6507 // optional op; may set condition codes 6508 lsr w0, w0, w1 // w0<- op, w0-w3 changed 6509 GET_INST_OPCODE ip // extract opcode from rINST 6510 SET_VREG w0, w9 // vAA<- w0 6511 GOTO_OPCODE ip // jump to next instruction 6512 /* 10-12 instructions */ 6513 6514 6515/* ------------------------------ */ 6516 .balign 128 6517.L_op_iget_quick: /* 0xe3 */ 6518/* File: arm64/op_iget_quick.S */ 6519 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 6520 /* op vA, vB, offset//CCCC */ 6521 lsr w2, wINST, #12 // w2<- B 6522 FETCH w1, 1 // w1<- field byte offset 6523 GET_VREG w3, w2 // w3<- object we're operating on 6524 ubfx w2, wINST, #8, #4 // w2<- A 6525 cbz w3, common_errNullObject // object was null 6526 ldr w0, [x3, x1] // w0<- obj.field 6527 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6528 6529 SET_VREG w0, w2 // fp[A]<- w0 6530 GET_INST_OPCODE ip // extract opcode from rINST 6531 GOTO_OPCODE ip // jump to next instruction 6532 6533/* ------------------------------ */ 6534 .balign 128 6535.L_op_iget_wide_quick: /* 0xe4 */ 6536/* File: arm64/op_iget_wide_quick.S */ 6537 /* iget-wide-quick vA, vB, offset//CCCC */ 6538 lsr w2, wINST, #12 // w2<- B 6539 FETCH w4, 1 // w4<- field byte offset 6540 GET_VREG w3, w2 // w3<- object we're operating on 6541 ubfx w2, wINST, #8, #4 // w2<- A 6542 cbz w3, common_errNullObject // object was null 6543 ldr x0, [x3, x4] // x0<- obj.field 6544 FETCH_ADVANCE_INST 2 // advance rPC, load wINST 6545 SET_VREG_WIDE x0, w2 6546 GET_INST_OPCODE ip // extract opcode from wINST 6547 GOTO_OPCODE ip // jump to next instruction 6548 6549/* ------------------------------ */ 6550 .balign 128 6551.L_op_iget_object_quick: /* 0xe5 */ 6552/* File: arm64/op_iget_object_quick.S */ 6553 /* For: iget-object-quick */ 6554 /* op vA, vB, offset//CCCC */ 6555 lsr w2, wINST, #12 // w2<- B 6556 FETCH w1, 1 // w1<- field byte offset 6557 EXPORT_PC 6558 GET_VREG w0, w2 // w0<- object we're operating on 6559 bl artIGetObjectFromMterp // (obj, offset) 6560 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 6561 ubfx w2, wINST, #8, #4 // w2<- A 6562 PREFETCH_INST 2 6563 cbnz w3, MterpPossibleException // bail out 6564 SET_VREG_OBJECT w0, w2 // fp[A]<- w0 6565 ADVANCE 2 // advance rPC 6566 GET_INST_OPCODE ip // extract opcode from wINST 6567 GOTO_OPCODE ip // jump to next instruction 6568 6569/* ------------------------------ */ 6570 .balign 128 6571.L_op_iput_quick: /* 0xe6 */ 6572/* File: arm64/op_iput_quick.S */ 6573 /* For: iput-quick, iput-object-quick */ 6574 /* op vA, vB, offset//CCCC */ 6575 lsr w2, wINST, #12 // w2<- B 6576 FETCH w1, 1 // w1<- field byte offset 6577 GET_VREG w3, w2 // w3<- fp[B], the object pointer 6578 ubfx w2, wINST, #8, #4 // w2<- A 6579 cbz w3, common_errNullObject // object was null 6580 GET_VREG w0, w2 // w0<- fp[A] 6581 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6582 str w0, [x3, x1] // obj.field<- w0 6583 GET_INST_OPCODE ip // extract opcode from rINST 6584 GOTO_OPCODE ip // jump to next instruction 6585 6586/* ------------------------------ */ 6587 .balign 128 6588.L_op_iput_wide_quick: /* 0xe7 */ 6589/* File: arm64/op_iput_wide_quick.S */ 6590 /* iput-wide-quick vA, vB, offset//CCCC */ 6591 lsr w2, wINST, #12 // w2<- B 6592 FETCH w3, 1 // w3<- field byte offset 6593 GET_VREG w2, w2 // w2<- fp[B], the object pointer 6594 ubfx w0, wINST, #8, #4 // w0<- A 6595 cbz w2, common_errNullObject // object was null 6596 GET_VREG_WIDE x0, w0 // x0<- fp[A] 6597 FETCH_ADVANCE_INST 2 // advance rPC, load wINST 6598 str x0, [x2, x3] // obj.field<- x0 6599 GET_INST_OPCODE ip // extract opcode from wINST 6600 GOTO_OPCODE ip // jump to next instruction 6601 6602/* ------------------------------ */ 6603 .balign 128 6604.L_op_iput_object_quick: /* 0xe8 */ 6605/* File: arm64/op_iput_object_quick.S */ 6606 EXPORT_PC 6607 add x0, xFP, #OFF_FP_SHADOWFRAME 6608 mov x1, xPC 6609 mov w2, wINST 6610 bl MterpIputObjectQuick 6611 cbz w0, MterpException 6612 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6613 GET_INST_OPCODE ip // extract opcode from rINST 6614 GOTO_OPCODE ip // jump to next instruction 6615 6616/* ------------------------------ */ 6617 .balign 128 6618.L_op_invoke_virtual_quick: /* 0xe9 */ 6619/* File: arm64/op_invoke_virtual_quick.S */ 6620/* File: arm64/invoke.S */ 6621 /* 6622 * Generic invoke handler wrapper. 6623 */ 6624 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 6625 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 6626 .extern MterpInvokeVirtualQuick 6627 EXPORT_PC 6628 mov x0, xSELF 6629 add x1, xFP, #OFF_FP_SHADOWFRAME 6630 mov x2, xPC 6631 mov x3, xINST 6632 bl MterpInvokeVirtualQuick 6633 cbz w0, MterpException 6634 FETCH_ADVANCE_INST 3 6635 bl MterpShouldSwitchInterpreters 6636 cbnz w0, MterpFallback 6637 GET_INST_OPCODE ip 6638 GOTO_OPCODE ip 6639 6640 6641 6642/* ------------------------------ */ 6643 .balign 128 6644.L_op_invoke_virtual_range_quick: /* 0xea */ 6645/* File: arm64/op_invoke_virtual_range_quick.S */ 6646/* File: arm64/invoke.S */ 6647 /* 6648 * Generic invoke handler wrapper. 6649 */ 6650 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 6651 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 6652 .extern MterpInvokeVirtualQuickRange 6653 EXPORT_PC 6654 mov x0, xSELF 6655 add x1, xFP, #OFF_FP_SHADOWFRAME 6656 mov x2, xPC 6657 mov x3, xINST 6658 bl MterpInvokeVirtualQuickRange 6659 cbz w0, MterpException 6660 FETCH_ADVANCE_INST 3 6661 bl MterpShouldSwitchInterpreters 6662 cbnz w0, MterpFallback 6663 GET_INST_OPCODE ip 6664 GOTO_OPCODE ip 6665 6666 6667 6668/* ------------------------------ */ 6669 .balign 128 6670.L_op_iput_boolean_quick: /* 0xeb */ 6671/* File: arm64/op_iput_boolean_quick.S */ 6672/* File: arm64/op_iput_quick.S */ 6673 /* For: iput-quick, iput-object-quick */ 6674 /* op vA, vB, offset//CCCC */ 6675 lsr w2, wINST, #12 // w2<- B 6676 FETCH w1, 1 // w1<- field byte offset 6677 GET_VREG w3, w2 // w3<- fp[B], the object pointer 6678 ubfx w2, wINST, #8, #4 // w2<- A 6679 cbz w3, common_errNullObject // object was null 6680 GET_VREG w0, w2 // w0<- fp[A] 6681 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6682 strb w0, [x3, x1] // obj.field<- w0 6683 GET_INST_OPCODE ip // extract opcode from rINST 6684 GOTO_OPCODE ip // jump to next instruction 6685 6686 6687/* ------------------------------ */ 6688 .balign 128 6689.L_op_iput_byte_quick: /* 0xec */ 6690/* File: arm64/op_iput_byte_quick.S */ 6691/* File: arm64/op_iput_quick.S */ 6692 /* For: iput-quick, iput-object-quick */ 6693 /* op vA, vB, offset//CCCC */ 6694 lsr w2, wINST, #12 // w2<- B 6695 FETCH w1, 1 // w1<- field byte offset 6696 GET_VREG w3, w2 // w3<- fp[B], the object pointer 6697 ubfx w2, wINST, #8, #4 // w2<- A 6698 cbz w3, common_errNullObject // object was null 6699 GET_VREG w0, w2 // w0<- fp[A] 6700 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6701 strb w0, [x3, x1] // obj.field<- w0 6702 GET_INST_OPCODE ip // extract opcode from rINST 6703 GOTO_OPCODE ip // jump to next instruction 6704 6705 6706/* ------------------------------ */ 6707 .balign 128 6708.L_op_iput_char_quick: /* 0xed */ 6709/* File: arm64/op_iput_char_quick.S */ 6710/* File: arm64/op_iput_quick.S */ 6711 /* For: iput-quick, iput-object-quick */ 6712 /* op vA, vB, offset//CCCC */ 6713 lsr w2, wINST, #12 // w2<- B 6714 FETCH w1, 1 // w1<- field byte offset 6715 GET_VREG w3, w2 // w3<- fp[B], the object pointer 6716 ubfx w2, wINST, #8, #4 // w2<- A 6717 cbz w3, common_errNullObject // object was null 6718 GET_VREG w0, w2 // w0<- fp[A] 6719 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6720 strh w0, [x3, x1] // obj.field<- w0 6721 GET_INST_OPCODE ip // extract opcode from rINST 6722 GOTO_OPCODE ip // jump to next instruction 6723 6724 6725/* ------------------------------ */ 6726 .balign 128 6727.L_op_iput_short_quick: /* 0xee */ 6728/* File: arm64/op_iput_short_quick.S */ 6729/* File: arm64/op_iput_quick.S */ 6730 /* For: iput-quick, iput-object-quick */ 6731 /* op vA, vB, offset//CCCC */ 6732 lsr w2, wINST, #12 // w2<- B 6733 FETCH w1, 1 // w1<- field byte offset 6734 GET_VREG w3, w2 // w3<- fp[B], the object pointer 6735 ubfx w2, wINST, #8, #4 // w2<- A 6736 cbz w3, common_errNullObject // object was null 6737 GET_VREG w0, w2 // w0<- fp[A] 6738 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6739 strh w0, [x3, x1] // obj.field<- w0 6740 GET_INST_OPCODE ip // extract opcode from rINST 6741 GOTO_OPCODE ip // jump to next instruction 6742 6743 6744/* ------------------------------ */ 6745 .balign 128 6746.L_op_iget_boolean_quick: /* 0xef */ 6747/* File: arm64/op_iget_boolean_quick.S */ 6748/* File: arm64/op_iget_quick.S */ 6749 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 6750 /* op vA, vB, offset//CCCC */ 6751 lsr w2, wINST, #12 // w2<- B 6752 FETCH w1, 1 // w1<- field byte offset 6753 GET_VREG w3, w2 // w3<- object we're operating on 6754 ubfx w2, wINST, #8, #4 // w2<- A 6755 cbz w3, common_errNullObject // object was null 6756 ldrb w0, [x3, x1] // w0<- obj.field 6757 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6758 6759 SET_VREG w0, w2 // fp[A]<- w0 6760 GET_INST_OPCODE ip // extract opcode from rINST 6761 GOTO_OPCODE ip // jump to next instruction 6762 6763 6764/* ------------------------------ */ 6765 .balign 128 6766.L_op_iget_byte_quick: /* 0xf0 */ 6767/* File: arm64/op_iget_byte_quick.S */ 6768/* File: arm64/op_iget_quick.S */ 6769 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 6770 /* op vA, vB, offset//CCCC */ 6771 lsr w2, wINST, #12 // w2<- B 6772 FETCH w1, 1 // w1<- field byte offset 6773 GET_VREG w3, w2 // w3<- object we're operating on 6774 ubfx w2, wINST, #8, #4 // w2<- A 6775 cbz w3, common_errNullObject // object was null 6776 ldrsb w0, [x3, x1] // w0<- obj.field 6777 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6778 6779 SET_VREG w0, w2 // fp[A]<- w0 6780 GET_INST_OPCODE ip // extract opcode from rINST 6781 GOTO_OPCODE ip // jump to next instruction 6782 6783 6784/* ------------------------------ */ 6785 .balign 128 6786.L_op_iget_char_quick: /* 0xf1 */ 6787/* File: arm64/op_iget_char_quick.S */ 6788/* File: arm64/op_iget_quick.S */ 6789 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 6790 /* op vA, vB, offset//CCCC */ 6791 lsr w2, wINST, #12 // w2<- B 6792 FETCH w1, 1 // w1<- field byte offset 6793 GET_VREG w3, w2 // w3<- object we're operating on 6794 ubfx w2, wINST, #8, #4 // w2<- A 6795 cbz w3, common_errNullObject // object was null 6796 ldrh w0, [x3, x1] // w0<- obj.field 6797 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6798 6799 SET_VREG w0, w2 // fp[A]<- w0 6800 GET_INST_OPCODE ip // extract opcode from rINST 6801 GOTO_OPCODE ip // jump to next instruction 6802 6803 6804/* ------------------------------ */ 6805 .balign 128 6806.L_op_iget_short_quick: /* 0xf2 */ 6807/* File: arm64/op_iget_short_quick.S */ 6808/* File: arm64/op_iget_quick.S */ 6809 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 6810 /* op vA, vB, offset//CCCC */ 6811 lsr w2, wINST, #12 // w2<- B 6812 FETCH w1, 1 // w1<- field byte offset 6813 GET_VREG w3, w2 // w3<- object we're operating on 6814 ubfx w2, wINST, #8, #4 // w2<- A 6815 cbz w3, common_errNullObject // object was null 6816 ldrsh w0, [x3, x1] // w0<- obj.field 6817 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6818 6819 SET_VREG w0, w2 // fp[A]<- w0 6820 GET_INST_OPCODE ip // extract opcode from rINST 6821 GOTO_OPCODE ip // jump to next instruction 6822 6823 6824/* ------------------------------ */ 6825 .balign 128 6826.L_op_unused_f3: /* 0xf3 */ 6827/* File: arm64/op_unused_f3.S */ 6828/* File: arm64/unused.S */ 6829/* 6830 * Bail to reference interpreter to throw. 6831 */ 6832 b MterpFallback 6833 6834 6835/* ------------------------------ */ 6836 .balign 128 6837.L_op_unused_f4: /* 0xf4 */ 6838/* File: arm64/op_unused_f4.S */ 6839/* File: arm64/unused.S */ 6840/* 6841 * Bail to reference interpreter to throw. 6842 */ 6843 b MterpFallback 6844 6845 6846/* ------------------------------ */ 6847 .balign 128 6848.L_op_unused_f5: /* 0xf5 */ 6849/* File: arm64/op_unused_f5.S */ 6850/* File: arm64/unused.S */ 6851/* 6852 * Bail to reference interpreter to throw. 6853 */ 6854 b MterpFallback 6855 6856 6857/* ------------------------------ */ 6858 .balign 128 6859.L_op_unused_f6: /* 0xf6 */ 6860/* File: arm64/op_unused_f6.S */ 6861/* File: arm64/unused.S */ 6862/* 6863 * Bail to reference interpreter to throw. 6864 */ 6865 b MterpFallback 6866 6867 6868/* ------------------------------ */ 6869 .balign 128 6870.L_op_unused_f7: /* 0xf7 */ 6871/* File: arm64/op_unused_f7.S */ 6872/* File: arm64/unused.S */ 6873/* 6874 * Bail to reference interpreter to throw. 6875 */ 6876 b MterpFallback 6877 6878 6879/* ------------------------------ */ 6880 .balign 128 6881.L_op_unused_f8: /* 0xf8 */ 6882/* File: arm64/op_unused_f8.S */ 6883/* File: arm64/unused.S */ 6884/* 6885 * Bail to reference interpreter to throw. 6886 */ 6887 b MterpFallback 6888 6889 6890/* ------------------------------ */ 6891 .balign 128 6892.L_op_unused_f9: /* 0xf9 */ 6893/* File: arm64/op_unused_f9.S */ 6894/* File: arm64/unused.S */ 6895/* 6896 * Bail to reference interpreter to throw. 6897 */ 6898 b MterpFallback 6899 6900 6901/* ------------------------------ */ 6902 .balign 128 6903.L_op_invoke_polymorphic: /* 0xfa */ 6904/* Transfer stub to alternate interpreter */ 6905 b MterpFallback 6906 6907 6908/* ------------------------------ */ 6909 .balign 128 6910.L_op_invoke_polymorphic_range: /* 0xfb */ 6911/* Transfer stub to alternate interpreter */ 6912 b MterpFallback 6913 6914 6915/* ------------------------------ */ 6916 .balign 128 6917.L_op_invoke_custom: /* 0xfc */ 6918/* Transfer stub to alternate interpreter */ 6919 b MterpFallback 6920 6921 6922/* ------------------------------ */ 6923 .balign 128 6924.L_op_invoke_custom_range: /* 0xfd */ 6925/* Transfer stub to alternate interpreter */ 6926 b MterpFallback 6927 6928 6929/* ------------------------------ */ 6930 .balign 128 6931.L_op_unused_fe: /* 0xfe */ 6932/* File: arm64/op_unused_fe.S */ 6933/* File: arm64/unused.S */ 6934/* 6935 * Bail to reference interpreter to throw. 6936 */ 6937 b MterpFallback 6938 6939 6940/* ------------------------------ */ 6941 .balign 128 6942.L_op_unused_ff: /* 0xff */ 6943/* File: arm64/op_unused_ff.S */ 6944/* File: arm64/unused.S */ 6945/* 6946 * Bail to reference interpreter to throw. 6947 */ 6948 b MterpFallback 6949 6950 6951 .balign 128 6952 .size artMterpAsmInstructionStart, .-artMterpAsmInstructionStart 6953 .global artMterpAsmInstructionEnd 6954artMterpAsmInstructionEnd: 6955 6956/* 6957 * =========================================================================== 6958 * Sister implementations 6959 * =========================================================================== 6960 */ 6961 .global artMterpAsmSisterStart 6962 .type artMterpAsmSisterStart, %function 6963 .text 6964 .balign 4 6965artMterpAsmSisterStart: 6966 6967 .size artMterpAsmSisterStart, .-artMterpAsmSisterStart 6968 .global artMterpAsmSisterEnd 6969artMterpAsmSisterEnd: 6970 6971/* File: arm64/footer.S */ 6972/* 6973 * =========================================================================== 6974 * Common subroutines and data 6975 * =========================================================================== 6976 */ 6977 6978 6979/* 6980 * We've detected a condition that will result in an exception, but the exception 6981 * has not yet been thrown. Just bail out to the reference interpreter to deal with it. 6982 * TUNING: for consistency, we may want to just go ahead and handle these here. 6983 */ 6984common_errDivideByZero: 6985 EXPORT_PC 6986#if MTERP_LOGGING 6987 mov x0, xSELF 6988 add x1, xFP, #OFF_FP_SHADOWFRAME 6989 bl MterpLogDivideByZeroException 6990#endif 6991 b MterpCommonFallback 6992 6993common_errArrayIndex: 6994 EXPORT_PC 6995#if MTERP_LOGGING 6996 mov x0, xSELF 6997 add x1, xFP, #OFF_FP_SHADOWFRAME 6998 bl MterpLogArrayIndexException 6999#endif 7000 b MterpCommonFallback 7001 7002common_errNegativeArraySize: 7003 EXPORT_PC 7004#if MTERP_LOGGING 7005 mov x0, xSELF 7006 add x1, xFP, #OFF_FP_SHADOWFRAME 7007 bl MterpLogNegativeArraySizeException 7008#endif 7009 b MterpCommonFallback 7010 7011common_errNoSuchMethod: 7012 EXPORT_PC 7013#if MTERP_LOGGING 7014 mov x0, xSELF 7015 add x1, xFP, #OFF_FP_SHADOWFRAME 7016 bl MterpLogNoSuchMethodException 7017#endif 7018 b MterpCommonFallback 7019 7020common_errNullObject: 7021 EXPORT_PC 7022#if MTERP_LOGGING 7023 mov x0, xSELF 7024 add x1, xFP, #OFF_FP_SHADOWFRAME 7025 bl MterpLogNullObjectException 7026#endif 7027 b MterpCommonFallback 7028 7029common_exceptionThrown: 7030 EXPORT_PC 7031#if MTERP_LOGGING 7032 mov x0, xSELF 7033 add x1, xFP, #OFF_FP_SHADOWFRAME 7034 bl MterpLogExceptionThrownException 7035#endif 7036 b MterpCommonFallback 7037 7038MterpSuspendFallback: 7039 EXPORT_PC 7040#if MTERP_LOGGING 7041 mov x0, xSELF 7042 add x1, xFP, #OFF_FP_SHADOWFRAME 7043 ldr x2, [xSELF, #THREAD_FLAGS_OFFSET] 7044 bl MterpLogSuspendFallback 7045#endif 7046 b MterpCommonFallback 7047 7048/* 7049 * If we're here, something is out of the ordinary. If there is a pending 7050 * exception, handle it. Otherwise, roll back and retry with the reference 7051 * interpreter. 7052 */ 7053MterpPossibleException: 7054 ldr x0, [xSELF, #THREAD_EXCEPTION_OFFSET] 7055 cbz x0, MterpFallback // If not, fall back to reference interpreter. 7056 /* intentional fallthrough - handle pending exception. */ 7057/* 7058 * On return from a runtime helper routine, we've found a pending exception. 7059 * Can we handle it here - or need to bail out to caller? 7060 * 7061 */ 7062MterpException: 7063 mov x0, xSELF 7064 add x1, xFP, #OFF_FP_SHADOWFRAME 7065 bl MterpHandleException // (self, shadow_frame) 7066 cbz w0, MterpExceptionReturn // no local catch, back to caller. 7067 ldr x0, [xFP, #OFF_FP_CODE_ITEM] 7068 ldr w1, [xFP, #OFF_FP_DEX_PC] 7069 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] 7070 add xPC, x0, #CODEITEM_INSNS_OFFSET 7071 add xPC, xPC, x1, lsl #1 // generate new dex_pc_ptr 7072 /* Do we need to switch interpreters? */ 7073 bl MterpShouldSwitchInterpreters 7074 cbnz w0, MterpFallback 7075 /* resume execution at catch block */ 7076 EXPORT_PC 7077 FETCH_INST 7078 GET_INST_OPCODE ip 7079 GOTO_OPCODE ip 7080 /* NOTE: no fallthrough */ 7081/* 7082 * Common handling for branches with support for Jit profiling. 7083 * On entry: 7084 * wINST <= signed offset 7085 * wPROFILE <= signed hotness countdown (expanded to 32 bits) 7086 * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) 7087 * 7088 * We have quite a few different cases for branch profiling, OSR detection and 7089 * suspend check support here. 7090 * 7091 * Taken backward branches: 7092 * If profiling active, do hotness countdown and report if we hit zero. 7093 * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. 7094 * Is there a pending suspend request? If so, suspend. 7095 * 7096 * Taken forward branches and not-taken backward branches: 7097 * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. 7098 * 7099 * Our most common case is expected to be a taken backward branch with active jit profiling, 7100 * but no full OSR check and no pending suspend request. 7101 * Next most common case is not-taken branch with no full OSR check. 7102 * 7103 */ 7104MterpCommonTakenBranchNoFlags: 7105 cmp wINST, #0 7106 b.gt .L_forward_branch // don't add forward branches to hotness 7107 tbnz wPROFILE, #31, .L_no_count_backwards // go if negative 7108 subs wPROFILE, wPROFILE, #1 // countdown 7109 b.eq .L_add_batch // counted down to zero - report 7110.L_resume_backward_branch: 7111 ldr lr, [xSELF, #THREAD_FLAGS_OFFSET] 7112 add w2, wINST, wINST // w2<- byte offset 7113 FETCH_ADVANCE_INST_RB w2 // update rPC, load wINST 7114 REFRESH_IBASE 7115 ands lr, lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 7116 b.ne .L_suspend_request_pending 7117 GET_INST_OPCODE ip // extract opcode from wINST 7118 GOTO_OPCODE ip // jump to next instruction 7119 7120.L_suspend_request_pending: 7121 EXPORT_PC 7122 mov x0, xSELF 7123 bl MterpSuspendCheck // (self) 7124 cbnz x0, MterpFallback 7125 REFRESH_IBASE // might have changed during suspend 7126 GET_INST_OPCODE ip // extract opcode from wINST 7127 GOTO_OPCODE ip // jump to next instruction 7128 7129.L_no_count_backwards: 7130 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 7131 b.ne .L_resume_backward_branch 7132 mov x0, xSELF 7133 add x1, xFP, #OFF_FP_SHADOWFRAME 7134 mov x2, xINST 7135 EXPORT_PC 7136 bl MterpMaybeDoOnStackReplacement // (self, shadow_frame, offset) 7137 cbnz x0, MterpOnStackReplacement 7138 b .L_resume_backward_branch 7139 7140.L_forward_branch: 7141 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 7142 b.eq .L_check_osr_forward 7143.L_resume_forward_branch: 7144 add w2, wINST, wINST // w2<- byte offset 7145 FETCH_ADVANCE_INST_RB w2 // update rPC, load wINST 7146 GET_INST_OPCODE ip // extract opcode from wINST 7147 GOTO_OPCODE ip // jump to next instruction 7148 7149.L_check_osr_forward: 7150 mov x0, xSELF 7151 add x1, xFP, #OFF_FP_SHADOWFRAME 7152 mov x2, xINST 7153 EXPORT_PC 7154 bl MterpMaybeDoOnStackReplacement // (self, shadow_frame, offset) 7155 cbnz x0, MterpOnStackReplacement 7156 b .L_resume_forward_branch 7157 7158.L_add_batch: 7159 add x1, xFP, #OFF_FP_SHADOWFRAME 7160 strh wPROFILE, [x1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] 7161 ldr x0, [xFP, #OFF_FP_METHOD] 7162 mov x2, xSELF 7163 bl MterpAddHotnessBatch // (method, shadow_frame, self) 7164 mov wPROFILE, w0 // restore new hotness countdown to wPROFILE 7165 b .L_no_count_backwards 7166 7167/* 7168 * Entered from the conditional branch handlers when OSR check request active on 7169 * not-taken path. All Dalvik not-taken conditional branch offsets are 2. 7170 */ 7171.L_check_not_taken_osr: 7172 mov x0, xSELF 7173 add x1, xFP, #OFF_FP_SHADOWFRAME 7174 mov x2, #2 7175 EXPORT_PC 7176 bl MterpMaybeDoOnStackReplacement // (self, shadow_frame, offset) 7177 cbnz x0, MterpOnStackReplacement 7178 FETCH_ADVANCE_INST 2 7179 GET_INST_OPCODE ip // extract opcode from wINST 7180 GOTO_OPCODE ip // jump to next instruction 7181 7182 7183/* 7184 * Check for suspend check request. Assumes wINST already loaded, xPC advanced and 7185 * still needs to get the opcode and branch to it, and flags are in lr. 7186 */ 7187MterpCheckSuspendAndContinue: 7188 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh xIBASE 7189 ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 7190 b.ne check1 7191 GET_INST_OPCODE ip // extract opcode from wINST 7192 GOTO_OPCODE ip // jump to next instruction 7193check1: 7194 EXPORT_PC 7195 mov x0, xSELF 7196 bl MterpSuspendCheck // (self) 7197 cbnz x0, MterpFallback // Something in the environment changed, switch interpreters 7198 GET_INST_OPCODE ip // extract opcode from wINST 7199 GOTO_OPCODE ip // jump to next instruction 7200 7201/* 7202 * On-stack replacement has happened, and now we've returned from the compiled method. 7203 */ 7204MterpOnStackReplacement: 7205#if MTERP_LOGGING 7206 mov x0, xSELF 7207 add x1, xFP, #OFF_FP_SHADOWFRAME 7208 sxtw x2, wINST 7209 bl MterpLogOSR 7210#endif 7211 mov x0, #1 // Signal normal return 7212 b MterpDone 7213 7214/* 7215 * Bail out to reference interpreter. 7216 */ 7217MterpFallback: 7218 EXPORT_PC 7219#if MTERP_LOGGING 7220 mov x0, xSELF 7221 add x1, xFP, #OFF_FP_SHADOWFRAME 7222 bl MterpLogFallback 7223#endif 7224MterpCommonFallback: 7225 mov x0, #0 // signal retry with reference interpreter. 7226 b MterpDone 7227 7228/* 7229 * We pushed some registers on the stack in ExecuteMterpImpl, then saved 7230 * SP and LR. Here we restore SP, restore the registers, and then restore 7231 * LR to PC. 7232 * 7233 * On entry: 7234 * uint32_t* xFP (should still be live, pointer to base of vregs) 7235 */ 7236MterpExceptionReturn: 7237 mov x0, #1 // signal return to caller. 7238 b MterpDone 7239MterpReturn: 7240 ldr x2, [xFP, #OFF_FP_RESULT_REGISTER] 7241 str x0, [x2] 7242 mov x0, #1 // signal return to caller. 7243MterpDone: 7244/* 7245 * At this point, we expect wPROFILE to be non-zero. If negative, hotness is disabled or we're 7246 * checking for OSR. If greater than zero, we might have unreported hotness to register 7247 * (the difference between the ending wPROFILE and the cached hotness counter). wPROFILE 7248 * should only reach zero immediately after a hotness decrement, and is then reset to either 7249 * a negative special state or the new non-zero countdown value. 7250 */ 7251 cmp wPROFILE, #0 7252 bgt MterpProfileActive // if > 0, we may have some counts to report. 7253 .cfi_remember_state 7254 RESTORE_TWO_REGS fp, lr, 64 7255 RESTORE_TWO_REGS xPC, xFP, 48 7256 RESTORE_TWO_REGS xSELF, xINST, 32 7257 RESTORE_TWO_REGS xIBASE, xREFS, 16 7258 RESTORE_TWO_REGS_DECREASE_FRAME xPROFILE, x27, 80 7259 ret 7260 .cfi_restore_state // Reset unwind info so following code unwinds. 7261 .cfi_def_cfa_offset 80 // workaround for clang bug: 31975598 7262 7263MterpProfileActive: 7264 mov xINST, x0 // stash return value 7265 /* Report cached hotness counts */ 7266 ldr x0, [xFP, #OFF_FP_METHOD] 7267 add x1, xFP, #OFF_FP_SHADOWFRAME 7268 mov x2, xSELF 7269 strh wPROFILE, [x1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] 7270 bl MterpAddHotnessBatch // (method, shadow_frame, self) 7271 mov x0, xINST // restore return value 7272 RESTORE_TWO_REGS fp, lr, 64 7273 RESTORE_TWO_REGS xPC, xFP, 48 7274 RESTORE_TWO_REGS xSELF, xINST, 32 7275 RESTORE_TWO_REGS xIBASE, xREFS, 16 7276 RESTORE_TWO_REGS_DECREASE_FRAME xPROFILE, x27, 80 7277 ret 7278 7279 .cfi_endproc 7280 .size ExecuteMterpImpl, .-ExecuteMterpImpl 7281 7282 7283 7284 .global artMterpAsmAltInstructionStart 7285 .type artMterpAsmAltInstructionStart, %function 7286 .text 7287 7288artMterpAsmAltInstructionStart = .L_ALT_op_nop 7289/* ------------------------------ */ 7290 .balign 128 7291.L_ALT_op_nop: /* 0x00 */ 7292/* File: arm64/alt_stub.S */ 7293/* 7294 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7295 * any interesting requests and then jump to the real instruction 7296 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7297 */ 7298 .extern MterpCheckBefore 7299 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7300 adr lr, artMterpAsmInstructionStart + (0 * 128) // Addr of primary handler. 7301 mov x0, xSELF 7302 add x1, xFP, #OFF_FP_SHADOWFRAME 7303 mov x2, xPC 7304 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7305 7306/* ------------------------------ */ 7307 .balign 128 7308.L_ALT_op_move: /* 0x01 */ 7309/* File: arm64/alt_stub.S */ 7310/* 7311 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7312 * any interesting requests and then jump to the real instruction 7313 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7314 */ 7315 .extern MterpCheckBefore 7316 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7317 adr lr, artMterpAsmInstructionStart + (1 * 128) // Addr of primary handler. 7318 mov x0, xSELF 7319 add x1, xFP, #OFF_FP_SHADOWFRAME 7320 mov x2, xPC 7321 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7322 7323/* ------------------------------ */ 7324 .balign 128 7325.L_ALT_op_move_from16: /* 0x02 */ 7326/* File: arm64/alt_stub.S */ 7327/* 7328 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7329 * any interesting requests and then jump to the real instruction 7330 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7331 */ 7332 .extern MterpCheckBefore 7333 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7334 adr lr, artMterpAsmInstructionStart + (2 * 128) // Addr of primary handler. 7335 mov x0, xSELF 7336 add x1, xFP, #OFF_FP_SHADOWFRAME 7337 mov x2, xPC 7338 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7339 7340/* ------------------------------ */ 7341 .balign 128 7342.L_ALT_op_move_16: /* 0x03 */ 7343/* File: arm64/alt_stub.S */ 7344/* 7345 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7346 * any interesting requests and then jump to the real instruction 7347 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7348 */ 7349 .extern MterpCheckBefore 7350 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7351 adr lr, artMterpAsmInstructionStart + (3 * 128) // Addr of primary handler. 7352 mov x0, xSELF 7353 add x1, xFP, #OFF_FP_SHADOWFRAME 7354 mov x2, xPC 7355 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7356 7357/* ------------------------------ */ 7358 .balign 128 7359.L_ALT_op_move_wide: /* 0x04 */ 7360/* File: arm64/alt_stub.S */ 7361/* 7362 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7363 * any interesting requests and then jump to the real instruction 7364 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7365 */ 7366 .extern MterpCheckBefore 7367 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7368 adr lr, artMterpAsmInstructionStart + (4 * 128) // Addr of primary handler. 7369 mov x0, xSELF 7370 add x1, xFP, #OFF_FP_SHADOWFRAME 7371 mov x2, xPC 7372 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7373 7374/* ------------------------------ */ 7375 .balign 128 7376.L_ALT_op_move_wide_from16: /* 0x05 */ 7377/* File: arm64/alt_stub.S */ 7378/* 7379 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7380 * any interesting requests and then jump to the real instruction 7381 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7382 */ 7383 .extern MterpCheckBefore 7384 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7385 adr lr, artMterpAsmInstructionStart + (5 * 128) // Addr of primary handler. 7386 mov x0, xSELF 7387 add x1, xFP, #OFF_FP_SHADOWFRAME 7388 mov x2, xPC 7389 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7390 7391/* ------------------------------ */ 7392 .balign 128 7393.L_ALT_op_move_wide_16: /* 0x06 */ 7394/* File: arm64/alt_stub.S */ 7395/* 7396 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7397 * any interesting requests and then jump to the real instruction 7398 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7399 */ 7400 .extern MterpCheckBefore 7401 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7402 adr lr, artMterpAsmInstructionStart + (6 * 128) // Addr of primary handler. 7403 mov x0, xSELF 7404 add x1, xFP, #OFF_FP_SHADOWFRAME 7405 mov x2, xPC 7406 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7407 7408/* ------------------------------ */ 7409 .balign 128 7410.L_ALT_op_move_object: /* 0x07 */ 7411/* File: arm64/alt_stub.S */ 7412/* 7413 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7414 * any interesting requests and then jump to the real instruction 7415 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7416 */ 7417 .extern MterpCheckBefore 7418 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7419 adr lr, artMterpAsmInstructionStart + (7 * 128) // Addr of primary handler. 7420 mov x0, xSELF 7421 add x1, xFP, #OFF_FP_SHADOWFRAME 7422 mov x2, xPC 7423 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7424 7425/* ------------------------------ */ 7426 .balign 128 7427.L_ALT_op_move_object_from16: /* 0x08 */ 7428/* File: arm64/alt_stub.S */ 7429/* 7430 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7431 * any interesting requests and then jump to the real instruction 7432 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7433 */ 7434 .extern MterpCheckBefore 7435 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7436 adr lr, artMterpAsmInstructionStart + (8 * 128) // Addr of primary handler. 7437 mov x0, xSELF 7438 add x1, xFP, #OFF_FP_SHADOWFRAME 7439 mov x2, xPC 7440 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7441 7442/* ------------------------------ */ 7443 .balign 128 7444.L_ALT_op_move_object_16: /* 0x09 */ 7445/* File: arm64/alt_stub.S */ 7446/* 7447 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7448 * any interesting requests and then jump to the real instruction 7449 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7450 */ 7451 .extern MterpCheckBefore 7452 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7453 adr lr, artMterpAsmInstructionStart + (9 * 128) // Addr of primary handler. 7454 mov x0, xSELF 7455 add x1, xFP, #OFF_FP_SHADOWFRAME 7456 mov x2, xPC 7457 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7458 7459/* ------------------------------ */ 7460 .balign 128 7461.L_ALT_op_move_result: /* 0x0a */ 7462/* File: arm64/alt_stub.S */ 7463/* 7464 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7465 * any interesting requests and then jump to the real instruction 7466 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7467 */ 7468 .extern MterpCheckBefore 7469 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7470 adr lr, artMterpAsmInstructionStart + (10 * 128) // Addr of primary handler. 7471 mov x0, xSELF 7472 add x1, xFP, #OFF_FP_SHADOWFRAME 7473 mov x2, xPC 7474 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7475 7476/* ------------------------------ */ 7477 .balign 128 7478.L_ALT_op_move_result_wide: /* 0x0b */ 7479/* File: arm64/alt_stub.S */ 7480/* 7481 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7482 * any interesting requests and then jump to the real instruction 7483 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7484 */ 7485 .extern MterpCheckBefore 7486 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7487 adr lr, artMterpAsmInstructionStart + (11 * 128) // Addr of primary handler. 7488 mov x0, xSELF 7489 add x1, xFP, #OFF_FP_SHADOWFRAME 7490 mov x2, xPC 7491 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7492 7493/* ------------------------------ */ 7494 .balign 128 7495.L_ALT_op_move_result_object: /* 0x0c */ 7496/* File: arm64/alt_stub.S */ 7497/* 7498 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7499 * any interesting requests and then jump to the real instruction 7500 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7501 */ 7502 .extern MterpCheckBefore 7503 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7504 adr lr, artMterpAsmInstructionStart + (12 * 128) // Addr of primary handler. 7505 mov x0, xSELF 7506 add x1, xFP, #OFF_FP_SHADOWFRAME 7507 mov x2, xPC 7508 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7509 7510/* ------------------------------ */ 7511 .balign 128 7512.L_ALT_op_move_exception: /* 0x0d */ 7513/* File: arm64/alt_stub.S */ 7514/* 7515 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7516 * any interesting requests and then jump to the real instruction 7517 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7518 */ 7519 .extern MterpCheckBefore 7520 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7521 adr lr, artMterpAsmInstructionStart + (13 * 128) // Addr of primary handler. 7522 mov x0, xSELF 7523 add x1, xFP, #OFF_FP_SHADOWFRAME 7524 mov x2, xPC 7525 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7526 7527/* ------------------------------ */ 7528 .balign 128 7529.L_ALT_op_return_void: /* 0x0e */ 7530/* File: arm64/alt_stub.S */ 7531/* 7532 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7533 * any interesting requests and then jump to the real instruction 7534 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7535 */ 7536 .extern MterpCheckBefore 7537 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7538 adr lr, artMterpAsmInstructionStart + (14 * 128) // Addr of primary handler. 7539 mov x0, xSELF 7540 add x1, xFP, #OFF_FP_SHADOWFRAME 7541 mov x2, xPC 7542 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7543 7544/* ------------------------------ */ 7545 .balign 128 7546.L_ALT_op_return: /* 0x0f */ 7547/* File: arm64/alt_stub.S */ 7548/* 7549 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7550 * any interesting requests and then jump to the real instruction 7551 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7552 */ 7553 .extern MterpCheckBefore 7554 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7555 adr lr, artMterpAsmInstructionStart + (15 * 128) // Addr of primary handler. 7556 mov x0, xSELF 7557 add x1, xFP, #OFF_FP_SHADOWFRAME 7558 mov x2, xPC 7559 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7560 7561/* ------------------------------ */ 7562 .balign 128 7563.L_ALT_op_return_wide: /* 0x10 */ 7564/* File: arm64/alt_stub.S */ 7565/* 7566 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7567 * any interesting requests and then jump to the real instruction 7568 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7569 */ 7570 .extern MterpCheckBefore 7571 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7572 adr lr, artMterpAsmInstructionStart + (16 * 128) // Addr of primary handler. 7573 mov x0, xSELF 7574 add x1, xFP, #OFF_FP_SHADOWFRAME 7575 mov x2, xPC 7576 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7577 7578/* ------------------------------ */ 7579 .balign 128 7580.L_ALT_op_return_object: /* 0x11 */ 7581/* File: arm64/alt_stub.S */ 7582/* 7583 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7584 * any interesting requests and then jump to the real instruction 7585 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7586 */ 7587 .extern MterpCheckBefore 7588 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7589 adr lr, artMterpAsmInstructionStart + (17 * 128) // Addr of primary handler. 7590 mov x0, xSELF 7591 add x1, xFP, #OFF_FP_SHADOWFRAME 7592 mov x2, xPC 7593 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7594 7595/* ------------------------------ */ 7596 .balign 128 7597.L_ALT_op_const_4: /* 0x12 */ 7598/* File: arm64/alt_stub.S */ 7599/* 7600 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7601 * any interesting requests and then jump to the real instruction 7602 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7603 */ 7604 .extern MterpCheckBefore 7605 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7606 adr lr, artMterpAsmInstructionStart + (18 * 128) // Addr of primary handler. 7607 mov x0, xSELF 7608 add x1, xFP, #OFF_FP_SHADOWFRAME 7609 mov x2, xPC 7610 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7611 7612/* ------------------------------ */ 7613 .balign 128 7614.L_ALT_op_const_16: /* 0x13 */ 7615/* File: arm64/alt_stub.S */ 7616/* 7617 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7618 * any interesting requests and then jump to the real instruction 7619 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7620 */ 7621 .extern MterpCheckBefore 7622 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7623 adr lr, artMterpAsmInstructionStart + (19 * 128) // Addr of primary handler. 7624 mov x0, xSELF 7625 add x1, xFP, #OFF_FP_SHADOWFRAME 7626 mov x2, xPC 7627 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7628 7629/* ------------------------------ */ 7630 .balign 128 7631.L_ALT_op_const: /* 0x14 */ 7632/* File: arm64/alt_stub.S */ 7633/* 7634 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7635 * any interesting requests and then jump to the real instruction 7636 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7637 */ 7638 .extern MterpCheckBefore 7639 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7640 adr lr, artMterpAsmInstructionStart + (20 * 128) // Addr of primary handler. 7641 mov x0, xSELF 7642 add x1, xFP, #OFF_FP_SHADOWFRAME 7643 mov x2, xPC 7644 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7645 7646/* ------------------------------ */ 7647 .balign 128 7648.L_ALT_op_const_high16: /* 0x15 */ 7649/* File: arm64/alt_stub.S */ 7650/* 7651 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7652 * any interesting requests and then jump to the real instruction 7653 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7654 */ 7655 .extern MterpCheckBefore 7656 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7657 adr lr, artMterpAsmInstructionStart + (21 * 128) // Addr of primary handler. 7658 mov x0, xSELF 7659 add x1, xFP, #OFF_FP_SHADOWFRAME 7660 mov x2, xPC 7661 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7662 7663/* ------------------------------ */ 7664 .balign 128 7665.L_ALT_op_const_wide_16: /* 0x16 */ 7666/* File: arm64/alt_stub.S */ 7667/* 7668 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7669 * any interesting requests and then jump to the real instruction 7670 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7671 */ 7672 .extern MterpCheckBefore 7673 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7674 adr lr, artMterpAsmInstructionStart + (22 * 128) // Addr of primary handler. 7675 mov x0, xSELF 7676 add x1, xFP, #OFF_FP_SHADOWFRAME 7677 mov x2, xPC 7678 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7679 7680/* ------------------------------ */ 7681 .balign 128 7682.L_ALT_op_const_wide_32: /* 0x17 */ 7683/* File: arm64/alt_stub.S */ 7684/* 7685 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7686 * any interesting requests and then jump to the real instruction 7687 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7688 */ 7689 .extern MterpCheckBefore 7690 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7691 adr lr, artMterpAsmInstructionStart + (23 * 128) // Addr of primary handler. 7692 mov x0, xSELF 7693 add x1, xFP, #OFF_FP_SHADOWFRAME 7694 mov x2, xPC 7695 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7696 7697/* ------------------------------ */ 7698 .balign 128 7699.L_ALT_op_const_wide: /* 0x18 */ 7700/* File: arm64/alt_stub.S */ 7701/* 7702 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7703 * any interesting requests and then jump to the real instruction 7704 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7705 */ 7706 .extern MterpCheckBefore 7707 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7708 adr lr, artMterpAsmInstructionStart + (24 * 128) // Addr of primary handler. 7709 mov x0, xSELF 7710 add x1, xFP, #OFF_FP_SHADOWFRAME 7711 mov x2, xPC 7712 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7713 7714/* ------------------------------ */ 7715 .balign 128 7716.L_ALT_op_const_wide_high16: /* 0x19 */ 7717/* File: arm64/alt_stub.S */ 7718/* 7719 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7720 * any interesting requests and then jump to the real instruction 7721 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7722 */ 7723 .extern MterpCheckBefore 7724 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7725 adr lr, artMterpAsmInstructionStart + (25 * 128) // Addr of primary handler. 7726 mov x0, xSELF 7727 add x1, xFP, #OFF_FP_SHADOWFRAME 7728 mov x2, xPC 7729 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7730 7731/* ------------------------------ */ 7732 .balign 128 7733.L_ALT_op_const_string: /* 0x1a */ 7734/* File: arm64/alt_stub.S */ 7735/* 7736 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7737 * any interesting requests and then jump to the real instruction 7738 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7739 */ 7740 .extern MterpCheckBefore 7741 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7742 adr lr, artMterpAsmInstructionStart + (26 * 128) // Addr of primary handler. 7743 mov x0, xSELF 7744 add x1, xFP, #OFF_FP_SHADOWFRAME 7745 mov x2, xPC 7746 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7747 7748/* ------------------------------ */ 7749 .balign 128 7750.L_ALT_op_const_string_jumbo: /* 0x1b */ 7751/* File: arm64/alt_stub.S */ 7752/* 7753 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7754 * any interesting requests and then jump to the real instruction 7755 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7756 */ 7757 .extern MterpCheckBefore 7758 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7759 adr lr, artMterpAsmInstructionStart + (27 * 128) // Addr of primary handler. 7760 mov x0, xSELF 7761 add x1, xFP, #OFF_FP_SHADOWFRAME 7762 mov x2, xPC 7763 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7764 7765/* ------------------------------ */ 7766 .balign 128 7767.L_ALT_op_const_class: /* 0x1c */ 7768/* File: arm64/alt_stub.S */ 7769/* 7770 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7771 * any interesting requests and then jump to the real instruction 7772 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7773 */ 7774 .extern MterpCheckBefore 7775 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7776 adr lr, artMterpAsmInstructionStart + (28 * 128) // Addr of primary handler. 7777 mov x0, xSELF 7778 add x1, xFP, #OFF_FP_SHADOWFRAME 7779 mov x2, xPC 7780 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7781 7782/* ------------------------------ */ 7783 .balign 128 7784.L_ALT_op_monitor_enter: /* 0x1d */ 7785/* File: arm64/alt_stub.S */ 7786/* 7787 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7788 * any interesting requests and then jump to the real instruction 7789 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7790 */ 7791 .extern MterpCheckBefore 7792 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7793 adr lr, artMterpAsmInstructionStart + (29 * 128) // Addr of primary handler. 7794 mov x0, xSELF 7795 add x1, xFP, #OFF_FP_SHADOWFRAME 7796 mov x2, xPC 7797 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7798 7799/* ------------------------------ */ 7800 .balign 128 7801.L_ALT_op_monitor_exit: /* 0x1e */ 7802/* File: arm64/alt_stub.S */ 7803/* 7804 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7805 * any interesting requests and then jump to the real instruction 7806 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7807 */ 7808 .extern MterpCheckBefore 7809 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7810 adr lr, artMterpAsmInstructionStart + (30 * 128) // Addr of primary handler. 7811 mov x0, xSELF 7812 add x1, xFP, #OFF_FP_SHADOWFRAME 7813 mov x2, xPC 7814 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7815 7816/* ------------------------------ */ 7817 .balign 128 7818.L_ALT_op_check_cast: /* 0x1f */ 7819/* File: arm64/alt_stub.S */ 7820/* 7821 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7822 * any interesting requests and then jump to the real instruction 7823 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7824 */ 7825 .extern MterpCheckBefore 7826 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7827 adr lr, artMterpAsmInstructionStart + (31 * 128) // Addr of primary handler. 7828 mov x0, xSELF 7829 add x1, xFP, #OFF_FP_SHADOWFRAME 7830 mov x2, xPC 7831 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7832 7833/* ------------------------------ */ 7834 .balign 128 7835.L_ALT_op_instance_of: /* 0x20 */ 7836/* File: arm64/alt_stub.S */ 7837/* 7838 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7839 * any interesting requests and then jump to the real instruction 7840 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7841 */ 7842 .extern MterpCheckBefore 7843 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7844 adr lr, artMterpAsmInstructionStart + (32 * 128) // Addr of primary handler. 7845 mov x0, xSELF 7846 add x1, xFP, #OFF_FP_SHADOWFRAME 7847 mov x2, xPC 7848 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7849 7850/* ------------------------------ */ 7851 .balign 128 7852.L_ALT_op_array_length: /* 0x21 */ 7853/* File: arm64/alt_stub.S */ 7854/* 7855 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7856 * any interesting requests and then jump to the real instruction 7857 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7858 */ 7859 .extern MterpCheckBefore 7860 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7861 adr lr, artMterpAsmInstructionStart + (33 * 128) // Addr of primary handler. 7862 mov x0, xSELF 7863 add x1, xFP, #OFF_FP_SHADOWFRAME 7864 mov x2, xPC 7865 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7866 7867/* ------------------------------ */ 7868 .balign 128 7869.L_ALT_op_new_instance: /* 0x22 */ 7870/* File: arm64/alt_stub.S */ 7871/* 7872 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7873 * any interesting requests and then jump to the real instruction 7874 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7875 */ 7876 .extern MterpCheckBefore 7877 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7878 adr lr, artMterpAsmInstructionStart + (34 * 128) // Addr of primary handler. 7879 mov x0, xSELF 7880 add x1, xFP, #OFF_FP_SHADOWFRAME 7881 mov x2, xPC 7882 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7883 7884/* ------------------------------ */ 7885 .balign 128 7886.L_ALT_op_new_array: /* 0x23 */ 7887/* File: arm64/alt_stub.S */ 7888/* 7889 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7890 * any interesting requests and then jump to the real instruction 7891 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7892 */ 7893 .extern MterpCheckBefore 7894 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7895 adr lr, artMterpAsmInstructionStart + (35 * 128) // Addr of primary handler. 7896 mov x0, xSELF 7897 add x1, xFP, #OFF_FP_SHADOWFRAME 7898 mov x2, xPC 7899 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7900 7901/* ------------------------------ */ 7902 .balign 128 7903.L_ALT_op_filled_new_array: /* 0x24 */ 7904/* File: arm64/alt_stub.S */ 7905/* 7906 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7907 * any interesting requests and then jump to the real instruction 7908 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7909 */ 7910 .extern MterpCheckBefore 7911 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7912 adr lr, artMterpAsmInstructionStart + (36 * 128) // Addr of primary handler. 7913 mov x0, xSELF 7914 add x1, xFP, #OFF_FP_SHADOWFRAME 7915 mov x2, xPC 7916 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7917 7918/* ------------------------------ */ 7919 .balign 128 7920.L_ALT_op_filled_new_array_range: /* 0x25 */ 7921/* File: arm64/alt_stub.S */ 7922/* 7923 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7924 * any interesting requests and then jump to the real instruction 7925 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7926 */ 7927 .extern MterpCheckBefore 7928 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7929 adr lr, artMterpAsmInstructionStart + (37 * 128) // Addr of primary handler. 7930 mov x0, xSELF 7931 add x1, xFP, #OFF_FP_SHADOWFRAME 7932 mov x2, xPC 7933 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7934 7935/* ------------------------------ */ 7936 .balign 128 7937.L_ALT_op_fill_array_data: /* 0x26 */ 7938/* File: arm64/alt_stub.S */ 7939/* 7940 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7941 * any interesting requests and then jump to the real instruction 7942 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7943 */ 7944 .extern MterpCheckBefore 7945 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7946 adr lr, artMterpAsmInstructionStart + (38 * 128) // Addr of primary handler. 7947 mov x0, xSELF 7948 add x1, xFP, #OFF_FP_SHADOWFRAME 7949 mov x2, xPC 7950 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7951 7952/* ------------------------------ */ 7953 .balign 128 7954.L_ALT_op_throw: /* 0x27 */ 7955/* File: arm64/alt_stub.S */ 7956/* 7957 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7958 * any interesting requests and then jump to the real instruction 7959 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7960 */ 7961 .extern MterpCheckBefore 7962 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7963 adr lr, artMterpAsmInstructionStart + (39 * 128) // Addr of primary handler. 7964 mov x0, xSELF 7965 add x1, xFP, #OFF_FP_SHADOWFRAME 7966 mov x2, xPC 7967 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7968 7969/* ------------------------------ */ 7970 .balign 128 7971.L_ALT_op_goto: /* 0x28 */ 7972/* File: arm64/alt_stub.S */ 7973/* 7974 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7975 * any interesting requests and then jump to the real instruction 7976 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7977 */ 7978 .extern MterpCheckBefore 7979 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7980 adr lr, artMterpAsmInstructionStart + (40 * 128) // Addr of primary handler. 7981 mov x0, xSELF 7982 add x1, xFP, #OFF_FP_SHADOWFRAME 7983 mov x2, xPC 7984 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 7985 7986/* ------------------------------ */ 7987 .balign 128 7988.L_ALT_op_goto_16: /* 0x29 */ 7989/* File: arm64/alt_stub.S */ 7990/* 7991 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7992 * any interesting requests and then jump to the real instruction 7993 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7994 */ 7995 .extern MterpCheckBefore 7996 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7997 adr lr, artMterpAsmInstructionStart + (41 * 128) // Addr of primary handler. 7998 mov x0, xSELF 7999 add x1, xFP, #OFF_FP_SHADOWFRAME 8000 mov x2, xPC 8001 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8002 8003/* ------------------------------ */ 8004 .balign 128 8005.L_ALT_op_goto_32: /* 0x2a */ 8006/* File: arm64/alt_stub.S */ 8007/* 8008 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8009 * any interesting requests and then jump to the real instruction 8010 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8011 */ 8012 .extern MterpCheckBefore 8013 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8014 adr lr, artMterpAsmInstructionStart + (42 * 128) // Addr of primary handler. 8015 mov x0, xSELF 8016 add x1, xFP, #OFF_FP_SHADOWFRAME 8017 mov x2, xPC 8018 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8019 8020/* ------------------------------ */ 8021 .balign 128 8022.L_ALT_op_packed_switch: /* 0x2b */ 8023/* File: arm64/alt_stub.S */ 8024/* 8025 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8026 * any interesting requests and then jump to the real instruction 8027 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8028 */ 8029 .extern MterpCheckBefore 8030 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8031 adr lr, artMterpAsmInstructionStart + (43 * 128) // Addr of primary handler. 8032 mov x0, xSELF 8033 add x1, xFP, #OFF_FP_SHADOWFRAME 8034 mov x2, xPC 8035 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8036 8037/* ------------------------------ */ 8038 .balign 128 8039.L_ALT_op_sparse_switch: /* 0x2c */ 8040/* File: arm64/alt_stub.S */ 8041/* 8042 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8043 * any interesting requests and then jump to the real instruction 8044 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8045 */ 8046 .extern MterpCheckBefore 8047 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8048 adr lr, artMterpAsmInstructionStart + (44 * 128) // Addr of primary handler. 8049 mov x0, xSELF 8050 add x1, xFP, #OFF_FP_SHADOWFRAME 8051 mov x2, xPC 8052 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8053 8054/* ------------------------------ */ 8055 .balign 128 8056.L_ALT_op_cmpl_float: /* 0x2d */ 8057/* File: arm64/alt_stub.S */ 8058/* 8059 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8060 * any interesting requests and then jump to the real instruction 8061 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8062 */ 8063 .extern MterpCheckBefore 8064 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8065 adr lr, artMterpAsmInstructionStart + (45 * 128) // Addr of primary handler. 8066 mov x0, xSELF 8067 add x1, xFP, #OFF_FP_SHADOWFRAME 8068 mov x2, xPC 8069 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8070 8071/* ------------------------------ */ 8072 .balign 128 8073.L_ALT_op_cmpg_float: /* 0x2e */ 8074/* File: arm64/alt_stub.S */ 8075/* 8076 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8077 * any interesting requests and then jump to the real instruction 8078 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8079 */ 8080 .extern MterpCheckBefore 8081 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8082 adr lr, artMterpAsmInstructionStart + (46 * 128) // Addr of primary handler. 8083 mov x0, xSELF 8084 add x1, xFP, #OFF_FP_SHADOWFRAME 8085 mov x2, xPC 8086 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8087 8088/* ------------------------------ */ 8089 .balign 128 8090.L_ALT_op_cmpl_double: /* 0x2f */ 8091/* File: arm64/alt_stub.S */ 8092/* 8093 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8094 * any interesting requests and then jump to the real instruction 8095 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8096 */ 8097 .extern MterpCheckBefore 8098 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8099 adr lr, artMterpAsmInstructionStart + (47 * 128) // Addr of primary handler. 8100 mov x0, xSELF 8101 add x1, xFP, #OFF_FP_SHADOWFRAME 8102 mov x2, xPC 8103 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8104 8105/* ------------------------------ */ 8106 .balign 128 8107.L_ALT_op_cmpg_double: /* 0x30 */ 8108/* File: arm64/alt_stub.S */ 8109/* 8110 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8111 * any interesting requests and then jump to the real instruction 8112 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8113 */ 8114 .extern MterpCheckBefore 8115 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8116 adr lr, artMterpAsmInstructionStart + (48 * 128) // Addr of primary handler. 8117 mov x0, xSELF 8118 add x1, xFP, #OFF_FP_SHADOWFRAME 8119 mov x2, xPC 8120 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8121 8122/* ------------------------------ */ 8123 .balign 128 8124.L_ALT_op_cmp_long: /* 0x31 */ 8125/* File: arm64/alt_stub.S */ 8126/* 8127 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8128 * any interesting requests and then jump to the real instruction 8129 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8130 */ 8131 .extern MterpCheckBefore 8132 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8133 adr lr, artMterpAsmInstructionStart + (49 * 128) // Addr of primary handler. 8134 mov x0, xSELF 8135 add x1, xFP, #OFF_FP_SHADOWFRAME 8136 mov x2, xPC 8137 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8138 8139/* ------------------------------ */ 8140 .balign 128 8141.L_ALT_op_if_eq: /* 0x32 */ 8142/* File: arm64/alt_stub.S */ 8143/* 8144 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8145 * any interesting requests and then jump to the real instruction 8146 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8147 */ 8148 .extern MterpCheckBefore 8149 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8150 adr lr, artMterpAsmInstructionStart + (50 * 128) // Addr of primary handler. 8151 mov x0, xSELF 8152 add x1, xFP, #OFF_FP_SHADOWFRAME 8153 mov x2, xPC 8154 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8155 8156/* ------------------------------ */ 8157 .balign 128 8158.L_ALT_op_if_ne: /* 0x33 */ 8159/* File: arm64/alt_stub.S */ 8160/* 8161 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8162 * any interesting requests and then jump to the real instruction 8163 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8164 */ 8165 .extern MterpCheckBefore 8166 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8167 adr lr, artMterpAsmInstructionStart + (51 * 128) // Addr of primary handler. 8168 mov x0, xSELF 8169 add x1, xFP, #OFF_FP_SHADOWFRAME 8170 mov x2, xPC 8171 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8172 8173/* ------------------------------ */ 8174 .balign 128 8175.L_ALT_op_if_lt: /* 0x34 */ 8176/* File: arm64/alt_stub.S */ 8177/* 8178 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8179 * any interesting requests and then jump to the real instruction 8180 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8181 */ 8182 .extern MterpCheckBefore 8183 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8184 adr lr, artMterpAsmInstructionStart + (52 * 128) // Addr of primary handler. 8185 mov x0, xSELF 8186 add x1, xFP, #OFF_FP_SHADOWFRAME 8187 mov x2, xPC 8188 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8189 8190/* ------------------------------ */ 8191 .balign 128 8192.L_ALT_op_if_ge: /* 0x35 */ 8193/* File: arm64/alt_stub.S */ 8194/* 8195 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8196 * any interesting requests and then jump to the real instruction 8197 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8198 */ 8199 .extern MterpCheckBefore 8200 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8201 adr lr, artMterpAsmInstructionStart + (53 * 128) // Addr of primary handler. 8202 mov x0, xSELF 8203 add x1, xFP, #OFF_FP_SHADOWFRAME 8204 mov x2, xPC 8205 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8206 8207/* ------------------------------ */ 8208 .balign 128 8209.L_ALT_op_if_gt: /* 0x36 */ 8210/* File: arm64/alt_stub.S */ 8211/* 8212 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8213 * any interesting requests and then jump to the real instruction 8214 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8215 */ 8216 .extern MterpCheckBefore 8217 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8218 adr lr, artMterpAsmInstructionStart + (54 * 128) // Addr of primary handler. 8219 mov x0, xSELF 8220 add x1, xFP, #OFF_FP_SHADOWFRAME 8221 mov x2, xPC 8222 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8223 8224/* ------------------------------ */ 8225 .balign 128 8226.L_ALT_op_if_le: /* 0x37 */ 8227/* File: arm64/alt_stub.S */ 8228/* 8229 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8230 * any interesting requests and then jump to the real instruction 8231 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8232 */ 8233 .extern MterpCheckBefore 8234 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8235 adr lr, artMterpAsmInstructionStart + (55 * 128) // Addr of primary handler. 8236 mov x0, xSELF 8237 add x1, xFP, #OFF_FP_SHADOWFRAME 8238 mov x2, xPC 8239 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8240 8241/* ------------------------------ */ 8242 .balign 128 8243.L_ALT_op_if_eqz: /* 0x38 */ 8244/* File: arm64/alt_stub.S */ 8245/* 8246 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8247 * any interesting requests and then jump to the real instruction 8248 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8249 */ 8250 .extern MterpCheckBefore 8251 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8252 adr lr, artMterpAsmInstructionStart + (56 * 128) // Addr of primary handler. 8253 mov x0, xSELF 8254 add x1, xFP, #OFF_FP_SHADOWFRAME 8255 mov x2, xPC 8256 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8257 8258/* ------------------------------ */ 8259 .balign 128 8260.L_ALT_op_if_nez: /* 0x39 */ 8261/* File: arm64/alt_stub.S */ 8262/* 8263 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8264 * any interesting requests and then jump to the real instruction 8265 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8266 */ 8267 .extern MterpCheckBefore 8268 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8269 adr lr, artMterpAsmInstructionStart + (57 * 128) // Addr of primary handler. 8270 mov x0, xSELF 8271 add x1, xFP, #OFF_FP_SHADOWFRAME 8272 mov x2, xPC 8273 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8274 8275/* ------------------------------ */ 8276 .balign 128 8277.L_ALT_op_if_ltz: /* 0x3a */ 8278/* File: arm64/alt_stub.S */ 8279/* 8280 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8281 * any interesting requests and then jump to the real instruction 8282 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8283 */ 8284 .extern MterpCheckBefore 8285 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8286 adr lr, artMterpAsmInstructionStart + (58 * 128) // Addr of primary handler. 8287 mov x0, xSELF 8288 add x1, xFP, #OFF_FP_SHADOWFRAME 8289 mov x2, xPC 8290 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8291 8292/* ------------------------------ */ 8293 .balign 128 8294.L_ALT_op_if_gez: /* 0x3b */ 8295/* File: arm64/alt_stub.S */ 8296/* 8297 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8298 * any interesting requests and then jump to the real instruction 8299 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8300 */ 8301 .extern MterpCheckBefore 8302 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8303 adr lr, artMterpAsmInstructionStart + (59 * 128) // Addr of primary handler. 8304 mov x0, xSELF 8305 add x1, xFP, #OFF_FP_SHADOWFRAME 8306 mov x2, xPC 8307 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8308 8309/* ------------------------------ */ 8310 .balign 128 8311.L_ALT_op_if_gtz: /* 0x3c */ 8312/* File: arm64/alt_stub.S */ 8313/* 8314 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8315 * any interesting requests and then jump to the real instruction 8316 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8317 */ 8318 .extern MterpCheckBefore 8319 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8320 adr lr, artMterpAsmInstructionStart + (60 * 128) // Addr of primary handler. 8321 mov x0, xSELF 8322 add x1, xFP, #OFF_FP_SHADOWFRAME 8323 mov x2, xPC 8324 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8325 8326/* ------------------------------ */ 8327 .balign 128 8328.L_ALT_op_if_lez: /* 0x3d */ 8329/* File: arm64/alt_stub.S */ 8330/* 8331 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8332 * any interesting requests and then jump to the real instruction 8333 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8334 */ 8335 .extern MterpCheckBefore 8336 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8337 adr lr, artMterpAsmInstructionStart + (61 * 128) // Addr of primary handler. 8338 mov x0, xSELF 8339 add x1, xFP, #OFF_FP_SHADOWFRAME 8340 mov x2, xPC 8341 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8342 8343/* ------------------------------ */ 8344 .balign 128 8345.L_ALT_op_unused_3e: /* 0x3e */ 8346/* File: arm64/alt_stub.S */ 8347/* 8348 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8349 * any interesting requests and then jump to the real instruction 8350 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8351 */ 8352 .extern MterpCheckBefore 8353 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8354 adr lr, artMterpAsmInstructionStart + (62 * 128) // Addr of primary handler. 8355 mov x0, xSELF 8356 add x1, xFP, #OFF_FP_SHADOWFRAME 8357 mov x2, xPC 8358 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8359 8360/* ------------------------------ */ 8361 .balign 128 8362.L_ALT_op_unused_3f: /* 0x3f */ 8363/* File: arm64/alt_stub.S */ 8364/* 8365 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8366 * any interesting requests and then jump to the real instruction 8367 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8368 */ 8369 .extern MterpCheckBefore 8370 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8371 adr lr, artMterpAsmInstructionStart + (63 * 128) // Addr of primary handler. 8372 mov x0, xSELF 8373 add x1, xFP, #OFF_FP_SHADOWFRAME 8374 mov x2, xPC 8375 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8376 8377/* ------------------------------ */ 8378 .balign 128 8379.L_ALT_op_unused_40: /* 0x40 */ 8380/* File: arm64/alt_stub.S */ 8381/* 8382 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8383 * any interesting requests and then jump to the real instruction 8384 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8385 */ 8386 .extern MterpCheckBefore 8387 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8388 adr lr, artMterpAsmInstructionStart + (64 * 128) // Addr of primary handler. 8389 mov x0, xSELF 8390 add x1, xFP, #OFF_FP_SHADOWFRAME 8391 mov x2, xPC 8392 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8393 8394/* ------------------------------ */ 8395 .balign 128 8396.L_ALT_op_unused_41: /* 0x41 */ 8397/* File: arm64/alt_stub.S */ 8398/* 8399 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8400 * any interesting requests and then jump to the real instruction 8401 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8402 */ 8403 .extern MterpCheckBefore 8404 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8405 adr lr, artMterpAsmInstructionStart + (65 * 128) // Addr of primary handler. 8406 mov x0, xSELF 8407 add x1, xFP, #OFF_FP_SHADOWFRAME 8408 mov x2, xPC 8409 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8410 8411/* ------------------------------ */ 8412 .balign 128 8413.L_ALT_op_unused_42: /* 0x42 */ 8414/* File: arm64/alt_stub.S */ 8415/* 8416 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8417 * any interesting requests and then jump to the real instruction 8418 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8419 */ 8420 .extern MterpCheckBefore 8421 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8422 adr lr, artMterpAsmInstructionStart + (66 * 128) // Addr of primary handler. 8423 mov x0, xSELF 8424 add x1, xFP, #OFF_FP_SHADOWFRAME 8425 mov x2, xPC 8426 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8427 8428/* ------------------------------ */ 8429 .balign 128 8430.L_ALT_op_unused_43: /* 0x43 */ 8431/* File: arm64/alt_stub.S */ 8432/* 8433 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8434 * any interesting requests and then jump to the real instruction 8435 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8436 */ 8437 .extern MterpCheckBefore 8438 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8439 adr lr, artMterpAsmInstructionStart + (67 * 128) // Addr of primary handler. 8440 mov x0, xSELF 8441 add x1, xFP, #OFF_FP_SHADOWFRAME 8442 mov x2, xPC 8443 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8444 8445/* ------------------------------ */ 8446 .balign 128 8447.L_ALT_op_aget: /* 0x44 */ 8448/* File: arm64/alt_stub.S */ 8449/* 8450 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8451 * any interesting requests and then jump to the real instruction 8452 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8453 */ 8454 .extern MterpCheckBefore 8455 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8456 adr lr, artMterpAsmInstructionStart + (68 * 128) // Addr of primary handler. 8457 mov x0, xSELF 8458 add x1, xFP, #OFF_FP_SHADOWFRAME 8459 mov x2, xPC 8460 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8461 8462/* ------------------------------ */ 8463 .balign 128 8464.L_ALT_op_aget_wide: /* 0x45 */ 8465/* File: arm64/alt_stub.S */ 8466/* 8467 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8468 * any interesting requests and then jump to the real instruction 8469 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8470 */ 8471 .extern MterpCheckBefore 8472 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8473 adr lr, artMterpAsmInstructionStart + (69 * 128) // Addr of primary handler. 8474 mov x0, xSELF 8475 add x1, xFP, #OFF_FP_SHADOWFRAME 8476 mov x2, xPC 8477 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8478 8479/* ------------------------------ */ 8480 .balign 128 8481.L_ALT_op_aget_object: /* 0x46 */ 8482/* File: arm64/alt_stub.S */ 8483/* 8484 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8485 * any interesting requests and then jump to the real instruction 8486 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8487 */ 8488 .extern MterpCheckBefore 8489 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8490 adr lr, artMterpAsmInstructionStart + (70 * 128) // Addr of primary handler. 8491 mov x0, xSELF 8492 add x1, xFP, #OFF_FP_SHADOWFRAME 8493 mov x2, xPC 8494 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8495 8496/* ------------------------------ */ 8497 .balign 128 8498.L_ALT_op_aget_boolean: /* 0x47 */ 8499/* File: arm64/alt_stub.S */ 8500/* 8501 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8502 * any interesting requests and then jump to the real instruction 8503 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8504 */ 8505 .extern MterpCheckBefore 8506 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8507 adr lr, artMterpAsmInstructionStart + (71 * 128) // Addr of primary handler. 8508 mov x0, xSELF 8509 add x1, xFP, #OFF_FP_SHADOWFRAME 8510 mov x2, xPC 8511 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8512 8513/* ------------------------------ */ 8514 .balign 128 8515.L_ALT_op_aget_byte: /* 0x48 */ 8516/* File: arm64/alt_stub.S */ 8517/* 8518 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8519 * any interesting requests and then jump to the real instruction 8520 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8521 */ 8522 .extern MterpCheckBefore 8523 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8524 adr lr, artMterpAsmInstructionStart + (72 * 128) // Addr of primary handler. 8525 mov x0, xSELF 8526 add x1, xFP, #OFF_FP_SHADOWFRAME 8527 mov x2, xPC 8528 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8529 8530/* ------------------------------ */ 8531 .balign 128 8532.L_ALT_op_aget_char: /* 0x49 */ 8533/* File: arm64/alt_stub.S */ 8534/* 8535 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8536 * any interesting requests and then jump to the real instruction 8537 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8538 */ 8539 .extern MterpCheckBefore 8540 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8541 adr lr, artMterpAsmInstructionStart + (73 * 128) // Addr of primary handler. 8542 mov x0, xSELF 8543 add x1, xFP, #OFF_FP_SHADOWFRAME 8544 mov x2, xPC 8545 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8546 8547/* ------------------------------ */ 8548 .balign 128 8549.L_ALT_op_aget_short: /* 0x4a */ 8550/* File: arm64/alt_stub.S */ 8551/* 8552 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8553 * any interesting requests and then jump to the real instruction 8554 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8555 */ 8556 .extern MterpCheckBefore 8557 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8558 adr lr, artMterpAsmInstructionStart + (74 * 128) // Addr of primary handler. 8559 mov x0, xSELF 8560 add x1, xFP, #OFF_FP_SHADOWFRAME 8561 mov x2, xPC 8562 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8563 8564/* ------------------------------ */ 8565 .balign 128 8566.L_ALT_op_aput: /* 0x4b */ 8567/* File: arm64/alt_stub.S */ 8568/* 8569 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8570 * any interesting requests and then jump to the real instruction 8571 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8572 */ 8573 .extern MterpCheckBefore 8574 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8575 adr lr, artMterpAsmInstructionStart + (75 * 128) // Addr of primary handler. 8576 mov x0, xSELF 8577 add x1, xFP, #OFF_FP_SHADOWFRAME 8578 mov x2, xPC 8579 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8580 8581/* ------------------------------ */ 8582 .balign 128 8583.L_ALT_op_aput_wide: /* 0x4c */ 8584/* File: arm64/alt_stub.S */ 8585/* 8586 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8587 * any interesting requests and then jump to the real instruction 8588 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8589 */ 8590 .extern MterpCheckBefore 8591 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8592 adr lr, artMterpAsmInstructionStart + (76 * 128) // Addr of primary handler. 8593 mov x0, xSELF 8594 add x1, xFP, #OFF_FP_SHADOWFRAME 8595 mov x2, xPC 8596 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8597 8598/* ------------------------------ */ 8599 .balign 128 8600.L_ALT_op_aput_object: /* 0x4d */ 8601/* File: arm64/alt_stub.S */ 8602/* 8603 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8604 * any interesting requests and then jump to the real instruction 8605 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8606 */ 8607 .extern MterpCheckBefore 8608 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8609 adr lr, artMterpAsmInstructionStart + (77 * 128) // Addr of primary handler. 8610 mov x0, xSELF 8611 add x1, xFP, #OFF_FP_SHADOWFRAME 8612 mov x2, xPC 8613 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8614 8615/* ------------------------------ */ 8616 .balign 128 8617.L_ALT_op_aput_boolean: /* 0x4e */ 8618/* File: arm64/alt_stub.S */ 8619/* 8620 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8621 * any interesting requests and then jump to the real instruction 8622 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8623 */ 8624 .extern MterpCheckBefore 8625 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8626 adr lr, artMterpAsmInstructionStart + (78 * 128) // Addr of primary handler. 8627 mov x0, xSELF 8628 add x1, xFP, #OFF_FP_SHADOWFRAME 8629 mov x2, xPC 8630 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8631 8632/* ------------------------------ */ 8633 .balign 128 8634.L_ALT_op_aput_byte: /* 0x4f */ 8635/* File: arm64/alt_stub.S */ 8636/* 8637 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8638 * any interesting requests and then jump to the real instruction 8639 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8640 */ 8641 .extern MterpCheckBefore 8642 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8643 adr lr, artMterpAsmInstructionStart + (79 * 128) // Addr of primary handler. 8644 mov x0, xSELF 8645 add x1, xFP, #OFF_FP_SHADOWFRAME 8646 mov x2, xPC 8647 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8648 8649/* ------------------------------ */ 8650 .balign 128 8651.L_ALT_op_aput_char: /* 0x50 */ 8652/* File: arm64/alt_stub.S */ 8653/* 8654 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8655 * any interesting requests and then jump to the real instruction 8656 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8657 */ 8658 .extern MterpCheckBefore 8659 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8660 adr lr, artMterpAsmInstructionStart + (80 * 128) // Addr of primary handler. 8661 mov x0, xSELF 8662 add x1, xFP, #OFF_FP_SHADOWFRAME 8663 mov x2, xPC 8664 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8665 8666/* ------------------------------ */ 8667 .balign 128 8668.L_ALT_op_aput_short: /* 0x51 */ 8669/* File: arm64/alt_stub.S */ 8670/* 8671 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8672 * any interesting requests and then jump to the real instruction 8673 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8674 */ 8675 .extern MterpCheckBefore 8676 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8677 adr lr, artMterpAsmInstructionStart + (81 * 128) // Addr of primary handler. 8678 mov x0, xSELF 8679 add x1, xFP, #OFF_FP_SHADOWFRAME 8680 mov x2, xPC 8681 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8682 8683/* ------------------------------ */ 8684 .balign 128 8685.L_ALT_op_iget: /* 0x52 */ 8686/* File: arm64/alt_stub.S */ 8687/* 8688 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8689 * any interesting requests and then jump to the real instruction 8690 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8691 */ 8692 .extern MterpCheckBefore 8693 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8694 adr lr, artMterpAsmInstructionStart + (82 * 128) // Addr of primary handler. 8695 mov x0, xSELF 8696 add x1, xFP, #OFF_FP_SHADOWFRAME 8697 mov x2, xPC 8698 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8699 8700/* ------------------------------ */ 8701 .balign 128 8702.L_ALT_op_iget_wide: /* 0x53 */ 8703/* File: arm64/alt_stub.S */ 8704/* 8705 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8706 * any interesting requests and then jump to the real instruction 8707 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8708 */ 8709 .extern MterpCheckBefore 8710 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8711 adr lr, artMterpAsmInstructionStart + (83 * 128) // Addr of primary handler. 8712 mov x0, xSELF 8713 add x1, xFP, #OFF_FP_SHADOWFRAME 8714 mov x2, xPC 8715 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8716 8717/* ------------------------------ */ 8718 .balign 128 8719.L_ALT_op_iget_object: /* 0x54 */ 8720/* File: arm64/alt_stub.S */ 8721/* 8722 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8723 * any interesting requests and then jump to the real instruction 8724 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8725 */ 8726 .extern MterpCheckBefore 8727 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8728 adr lr, artMterpAsmInstructionStart + (84 * 128) // Addr of primary handler. 8729 mov x0, xSELF 8730 add x1, xFP, #OFF_FP_SHADOWFRAME 8731 mov x2, xPC 8732 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8733 8734/* ------------------------------ */ 8735 .balign 128 8736.L_ALT_op_iget_boolean: /* 0x55 */ 8737/* File: arm64/alt_stub.S */ 8738/* 8739 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8740 * any interesting requests and then jump to the real instruction 8741 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8742 */ 8743 .extern MterpCheckBefore 8744 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8745 adr lr, artMterpAsmInstructionStart + (85 * 128) // Addr of primary handler. 8746 mov x0, xSELF 8747 add x1, xFP, #OFF_FP_SHADOWFRAME 8748 mov x2, xPC 8749 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8750 8751/* ------------------------------ */ 8752 .balign 128 8753.L_ALT_op_iget_byte: /* 0x56 */ 8754/* File: arm64/alt_stub.S */ 8755/* 8756 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8757 * any interesting requests and then jump to the real instruction 8758 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8759 */ 8760 .extern MterpCheckBefore 8761 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8762 adr lr, artMterpAsmInstructionStart + (86 * 128) // Addr of primary handler. 8763 mov x0, xSELF 8764 add x1, xFP, #OFF_FP_SHADOWFRAME 8765 mov x2, xPC 8766 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8767 8768/* ------------------------------ */ 8769 .balign 128 8770.L_ALT_op_iget_char: /* 0x57 */ 8771/* File: arm64/alt_stub.S */ 8772/* 8773 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8774 * any interesting requests and then jump to the real instruction 8775 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8776 */ 8777 .extern MterpCheckBefore 8778 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8779 adr lr, artMterpAsmInstructionStart + (87 * 128) // Addr of primary handler. 8780 mov x0, xSELF 8781 add x1, xFP, #OFF_FP_SHADOWFRAME 8782 mov x2, xPC 8783 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8784 8785/* ------------------------------ */ 8786 .balign 128 8787.L_ALT_op_iget_short: /* 0x58 */ 8788/* File: arm64/alt_stub.S */ 8789/* 8790 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8791 * any interesting requests and then jump to the real instruction 8792 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8793 */ 8794 .extern MterpCheckBefore 8795 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8796 adr lr, artMterpAsmInstructionStart + (88 * 128) // Addr of primary handler. 8797 mov x0, xSELF 8798 add x1, xFP, #OFF_FP_SHADOWFRAME 8799 mov x2, xPC 8800 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8801 8802/* ------------------------------ */ 8803 .balign 128 8804.L_ALT_op_iput: /* 0x59 */ 8805/* File: arm64/alt_stub.S */ 8806/* 8807 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8808 * any interesting requests and then jump to the real instruction 8809 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8810 */ 8811 .extern MterpCheckBefore 8812 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8813 adr lr, artMterpAsmInstructionStart + (89 * 128) // Addr of primary handler. 8814 mov x0, xSELF 8815 add x1, xFP, #OFF_FP_SHADOWFRAME 8816 mov x2, xPC 8817 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8818 8819/* ------------------------------ */ 8820 .balign 128 8821.L_ALT_op_iput_wide: /* 0x5a */ 8822/* File: arm64/alt_stub.S */ 8823/* 8824 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8825 * any interesting requests and then jump to the real instruction 8826 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8827 */ 8828 .extern MterpCheckBefore 8829 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8830 adr lr, artMterpAsmInstructionStart + (90 * 128) // Addr of primary handler. 8831 mov x0, xSELF 8832 add x1, xFP, #OFF_FP_SHADOWFRAME 8833 mov x2, xPC 8834 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8835 8836/* ------------------------------ */ 8837 .balign 128 8838.L_ALT_op_iput_object: /* 0x5b */ 8839/* File: arm64/alt_stub.S */ 8840/* 8841 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8842 * any interesting requests and then jump to the real instruction 8843 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8844 */ 8845 .extern MterpCheckBefore 8846 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8847 adr lr, artMterpAsmInstructionStart + (91 * 128) // Addr of primary handler. 8848 mov x0, xSELF 8849 add x1, xFP, #OFF_FP_SHADOWFRAME 8850 mov x2, xPC 8851 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8852 8853/* ------------------------------ */ 8854 .balign 128 8855.L_ALT_op_iput_boolean: /* 0x5c */ 8856/* File: arm64/alt_stub.S */ 8857/* 8858 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8859 * any interesting requests and then jump to the real instruction 8860 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8861 */ 8862 .extern MterpCheckBefore 8863 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8864 adr lr, artMterpAsmInstructionStart + (92 * 128) // Addr of primary handler. 8865 mov x0, xSELF 8866 add x1, xFP, #OFF_FP_SHADOWFRAME 8867 mov x2, xPC 8868 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8869 8870/* ------------------------------ */ 8871 .balign 128 8872.L_ALT_op_iput_byte: /* 0x5d */ 8873/* File: arm64/alt_stub.S */ 8874/* 8875 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8876 * any interesting requests and then jump to the real instruction 8877 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8878 */ 8879 .extern MterpCheckBefore 8880 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8881 adr lr, artMterpAsmInstructionStart + (93 * 128) // Addr of primary handler. 8882 mov x0, xSELF 8883 add x1, xFP, #OFF_FP_SHADOWFRAME 8884 mov x2, xPC 8885 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8886 8887/* ------------------------------ */ 8888 .balign 128 8889.L_ALT_op_iput_char: /* 0x5e */ 8890/* File: arm64/alt_stub.S */ 8891/* 8892 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8893 * any interesting requests and then jump to the real instruction 8894 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8895 */ 8896 .extern MterpCheckBefore 8897 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8898 adr lr, artMterpAsmInstructionStart + (94 * 128) // Addr of primary handler. 8899 mov x0, xSELF 8900 add x1, xFP, #OFF_FP_SHADOWFRAME 8901 mov x2, xPC 8902 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8903 8904/* ------------------------------ */ 8905 .balign 128 8906.L_ALT_op_iput_short: /* 0x5f */ 8907/* File: arm64/alt_stub.S */ 8908/* 8909 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8910 * any interesting requests and then jump to the real instruction 8911 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8912 */ 8913 .extern MterpCheckBefore 8914 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8915 adr lr, artMterpAsmInstructionStart + (95 * 128) // Addr of primary handler. 8916 mov x0, xSELF 8917 add x1, xFP, #OFF_FP_SHADOWFRAME 8918 mov x2, xPC 8919 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8920 8921/* ------------------------------ */ 8922 .balign 128 8923.L_ALT_op_sget: /* 0x60 */ 8924/* File: arm64/alt_stub.S */ 8925/* 8926 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8927 * any interesting requests and then jump to the real instruction 8928 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8929 */ 8930 .extern MterpCheckBefore 8931 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8932 adr lr, artMterpAsmInstructionStart + (96 * 128) // Addr of primary handler. 8933 mov x0, xSELF 8934 add x1, xFP, #OFF_FP_SHADOWFRAME 8935 mov x2, xPC 8936 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8937 8938/* ------------------------------ */ 8939 .balign 128 8940.L_ALT_op_sget_wide: /* 0x61 */ 8941/* File: arm64/alt_stub.S */ 8942/* 8943 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8944 * any interesting requests and then jump to the real instruction 8945 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8946 */ 8947 .extern MterpCheckBefore 8948 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8949 adr lr, artMterpAsmInstructionStart + (97 * 128) // Addr of primary handler. 8950 mov x0, xSELF 8951 add x1, xFP, #OFF_FP_SHADOWFRAME 8952 mov x2, xPC 8953 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8954 8955/* ------------------------------ */ 8956 .balign 128 8957.L_ALT_op_sget_object: /* 0x62 */ 8958/* File: arm64/alt_stub.S */ 8959/* 8960 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8961 * any interesting requests and then jump to the real instruction 8962 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8963 */ 8964 .extern MterpCheckBefore 8965 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8966 adr lr, artMterpAsmInstructionStart + (98 * 128) // Addr of primary handler. 8967 mov x0, xSELF 8968 add x1, xFP, #OFF_FP_SHADOWFRAME 8969 mov x2, xPC 8970 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8971 8972/* ------------------------------ */ 8973 .balign 128 8974.L_ALT_op_sget_boolean: /* 0x63 */ 8975/* File: arm64/alt_stub.S */ 8976/* 8977 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8978 * any interesting requests and then jump to the real instruction 8979 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8980 */ 8981 .extern MterpCheckBefore 8982 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8983 adr lr, artMterpAsmInstructionStart + (99 * 128) // Addr of primary handler. 8984 mov x0, xSELF 8985 add x1, xFP, #OFF_FP_SHADOWFRAME 8986 mov x2, xPC 8987 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 8988 8989/* ------------------------------ */ 8990 .balign 128 8991.L_ALT_op_sget_byte: /* 0x64 */ 8992/* File: arm64/alt_stub.S */ 8993/* 8994 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8995 * any interesting requests and then jump to the real instruction 8996 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8997 */ 8998 .extern MterpCheckBefore 8999 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9000 adr lr, artMterpAsmInstructionStart + (100 * 128) // Addr of primary handler. 9001 mov x0, xSELF 9002 add x1, xFP, #OFF_FP_SHADOWFRAME 9003 mov x2, xPC 9004 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9005 9006/* ------------------------------ */ 9007 .balign 128 9008.L_ALT_op_sget_char: /* 0x65 */ 9009/* File: arm64/alt_stub.S */ 9010/* 9011 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9012 * any interesting requests and then jump to the real instruction 9013 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9014 */ 9015 .extern MterpCheckBefore 9016 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9017 adr lr, artMterpAsmInstructionStart + (101 * 128) // Addr of primary handler. 9018 mov x0, xSELF 9019 add x1, xFP, #OFF_FP_SHADOWFRAME 9020 mov x2, xPC 9021 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9022 9023/* ------------------------------ */ 9024 .balign 128 9025.L_ALT_op_sget_short: /* 0x66 */ 9026/* File: arm64/alt_stub.S */ 9027/* 9028 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9029 * any interesting requests and then jump to the real instruction 9030 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9031 */ 9032 .extern MterpCheckBefore 9033 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9034 adr lr, artMterpAsmInstructionStart + (102 * 128) // Addr of primary handler. 9035 mov x0, xSELF 9036 add x1, xFP, #OFF_FP_SHADOWFRAME 9037 mov x2, xPC 9038 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9039 9040/* ------------------------------ */ 9041 .balign 128 9042.L_ALT_op_sput: /* 0x67 */ 9043/* File: arm64/alt_stub.S */ 9044/* 9045 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9046 * any interesting requests and then jump to the real instruction 9047 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9048 */ 9049 .extern MterpCheckBefore 9050 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9051 adr lr, artMterpAsmInstructionStart + (103 * 128) // Addr of primary handler. 9052 mov x0, xSELF 9053 add x1, xFP, #OFF_FP_SHADOWFRAME 9054 mov x2, xPC 9055 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9056 9057/* ------------------------------ */ 9058 .balign 128 9059.L_ALT_op_sput_wide: /* 0x68 */ 9060/* File: arm64/alt_stub.S */ 9061/* 9062 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9063 * any interesting requests and then jump to the real instruction 9064 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9065 */ 9066 .extern MterpCheckBefore 9067 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9068 adr lr, artMterpAsmInstructionStart + (104 * 128) // Addr of primary handler. 9069 mov x0, xSELF 9070 add x1, xFP, #OFF_FP_SHADOWFRAME 9071 mov x2, xPC 9072 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9073 9074/* ------------------------------ */ 9075 .balign 128 9076.L_ALT_op_sput_object: /* 0x69 */ 9077/* File: arm64/alt_stub.S */ 9078/* 9079 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9080 * any interesting requests and then jump to the real instruction 9081 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9082 */ 9083 .extern MterpCheckBefore 9084 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9085 adr lr, artMterpAsmInstructionStart + (105 * 128) // Addr of primary handler. 9086 mov x0, xSELF 9087 add x1, xFP, #OFF_FP_SHADOWFRAME 9088 mov x2, xPC 9089 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9090 9091/* ------------------------------ */ 9092 .balign 128 9093.L_ALT_op_sput_boolean: /* 0x6a */ 9094/* File: arm64/alt_stub.S */ 9095/* 9096 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9097 * any interesting requests and then jump to the real instruction 9098 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9099 */ 9100 .extern MterpCheckBefore 9101 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9102 adr lr, artMterpAsmInstructionStart + (106 * 128) // Addr of primary handler. 9103 mov x0, xSELF 9104 add x1, xFP, #OFF_FP_SHADOWFRAME 9105 mov x2, xPC 9106 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9107 9108/* ------------------------------ */ 9109 .balign 128 9110.L_ALT_op_sput_byte: /* 0x6b */ 9111/* File: arm64/alt_stub.S */ 9112/* 9113 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9114 * any interesting requests and then jump to the real instruction 9115 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9116 */ 9117 .extern MterpCheckBefore 9118 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9119 adr lr, artMterpAsmInstructionStart + (107 * 128) // Addr of primary handler. 9120 mov x0, xSELF 9121 add x1, xFP, #OFF_FP_SHADOWFRAME 9122 mov x2, xPC 9123 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9124 9125/* ------------------------------ */ 9126 .balign 128 9127.L_ALT_op_sput_char: /* 0x6c */ 9128/* File: arm64/alt_stub.S */ 9129/* 9130 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9131 * any interesting requests and then jump to the real instruction 9132 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9133 */ 9134 .extern MterpCheckBefore 9135 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9136 adr lr, artMterpAsmInstructionStart + (108 * 128) // Addr of primary handler. 9137 mov x0, xSELF 9138 add x1, xFP, #OFF_FP_SHADOWFRAME 9139 mov x2, xPC 9140 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9141 9142/* ------------------------------ */ 9143 .balign 128 9144.L_ALT_op_sput_short: /* 0x6d */ 9145/* File: arm64/alt_stub.S */ 9146/* 9147 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9148 * any interesting requests and then jump to the real instruction 9149 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9150 */ 9151 .extern MterpCheckBefore 9152 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9153 adr lr, artMterpAsmInstructionStart + (109 * 128) // Addr of primary handler. 9154 mov x0, xSELF 9155 add x1, xFP, #OFF_FP_SHADOWFRAME 9156 mov x2, xPC 9157 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9158 9159/* ------------------------------ */ 9160 .balign 128 9161.L_ALT_op_invoke_virtual: /* 0x6e */ 9162/* File: arm64/alt_stub.S */ 9163/* 9164 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9165 * any interesting requests and then jump to the real instruction 9166 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9167 */ 9168 .extern MterpCheckBefore 9169 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9170 adr lr, artMterpAsmInstructionStart + (110 * 128) // Addr of primary handler. 9171 mov x0, xSELF 9172 add x1, xFP, #OFF_FP_SHADOWFRAME 9173 mov x2, xPC 9174 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9175 9176/* ------------------------------ */ 9177 .balign 128 9178.L_ALT_op_invoke_super: /* 0x6f */ 9179/* File: arm64/alt_stub.S */ 9180/* 9181 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9182 * any interesting requests and then jump to the real instruction 9183 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9184 */ 9185 .extern MterpCheckBefore 9186 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9187 adr lr, artMterpAsmInstructionStart + (111 * 128) // Addr of primary handler. 9188 mov x0, xSELF 9189 add x1, xFP, #OFF_FP_SHADOWFRAME 9190 mov x2, xPC 9191 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9192 9193/* ------------------------------ */ 9194 .balign 128 9195.L_ALT_op_invoke_direct: /* 0x70 */ 9196/* File: arm64/alt_stub.S */ 9197/* 9198 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9199 * any interesting requests and then jump to the real instruction 9200 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9201 */ 9202 .extern MterpCheckBefore 9203 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9204 adr lr, artMterpAsmInstructionStart + (112 * 128) // Addr of primary handler. 9205 mov x0, xSELF 9206 add x1, xFP, #OFF_FP_SHADOWFRAME 9207 mov x2, xPC 9208 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9209 9210/* ------------------------------ */ 9211 .balign 128 9212.L_ALT_op_invoke_static: /* 0x71 */ 9213/* File: arm64/alt_stub.S */ 9214/* 9215 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9216 * any interesting requests and then jump to the real instruction 9217 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9218 */ 9219 .extern MterpCheckBefore 9220 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9221 adr lr, artMterpAsmInstructionStart + (113 * 128) // Addr of primary handler. 9222 mov x0, xSELF 9223 add x1, xFP, #OFF_FP_SHADOWFRAME 9224 mov x2, xPC 9225 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9226 9227/* ------------------------------ */ 9228 .balign 128 9229.L_ALT_op_invoke_interface: /* 0x72 */ 9230/* File: arm64/alt_stub.S */ 9231/* 9232 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9233 * any interesting requests and then jump to the real instruction 9234 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9235 */ 9236 .extern MterpCheckBefore 9237 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9238 adr lr, artMterpAsmInstructionStart + (114 * 128) // Addr of primary handler. 9239 mov x0, xSELF 9240 add x1, xFP, #OFF_FP_SHADOWFRAME 9241 mov x2, xPC 9242 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9243 9244/* ------------------------------ */ 9245 .balign 128 9246.L_ALT_op_return_void_no_barrier: /* 0x73 */ 9247/* File: arm64/alt_stub.S */ 9248/* 9249 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9250 * any interesting requests and then jump to the real instruction 9251 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9252 */ 9253 .extern MterpCheckBefore 9254 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9255 adr lr, artMterpAsmInstructionStart + (115 * 128) // Addr of primary handler. 9256 mov x0, xSELF 9257 add x1, xFP, #OFF_FP_SHADOWFRAME 9258 mov x2, xPC 9259 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9260 9261/* ------------------------------ */ 9262 .balign 128 9263.L_ALT_op_invoke_virtual_range: /* 0x74 */ 9264/* File: arm64/alt_stub.S */ 9265/* 9266 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9267 * any interesting requests and then jump to the real instruction 9268 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9269 */ 9270 .extern MterpCheckBefore 9271 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9272 adr lr, artMterpAsmInstructionStart + (116 * 128) // Addr of primary handler. 9273 mov x0, xSELF 9274 add x1, xFP, #OFF_FP_SHADOWFRAME 9275 mov x2, xPC 9276 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9277 9278/* ------------------------------ */ 9279 .balign 128 9280.L_ALT_op_invoke_super_range: /* 0x75 */ 9281/* File: arm64/alt_stub.S */ 9282/* 9283 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9284 * any interesting requests and then jump to the real instruction 9285 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9286 */ 9287 .extern MterpCheckBefore 9288 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9289 adr lr, artMterpAsmInstructionStart + (117 * 128) // Addr of primary handler. 9290 mov x0, xSELF 9291 add x1, xFP, #OFF_FP_SHADOWFRAME 9292 mov x2, xPC 9293 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9294 9295/* ------------------------------ */ 9296 .balign 128 9297.L_ALT_op_invoke_direct_range: /* 0x76 */ 9298/* File: arm64/alt_stub.S */ 9299/* 9300 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9301 * any interesting requests and then jump to the real instruction 9302 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9303 */ 9304 .extern MterpCheckBefore 9305 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9306 adr lr, artMterpAsmInstructionStart + (118 * 128) // Addr of primary handler. 9307 mov x0, xSELF 9308 add x1, xFP, #OFF_FP_SHADOWFRAME 9309 mov x2, xPC 9310 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9311 9312/* ------------------------------ */ 9313 .balign 128 9314.L_ALT_op_invoke_static_range: /* 0x77 */ 9315/* File: arm64/alt_stub.S */ 9316/* 9317 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9318 * any interesting requests and then jump to the real instruction 9319 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9320 */ 9321 .extern MterpCheckBefore 9322 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9323 adr lr, artMterpAsmInstructionStart + (119 * 128) // Addr of primary handler. 9324 mov x0, xSELF 9325 add x1, xFP, #OFF_FP_SHADOWFRAME 9326 mov x2, xPC 9327 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9328 9329/* ------------------------------ */ 9330 .balign 128 9331.L_ALT_op_invoke_interface_range: /* 0x78 */ 9332/* File: arm64/alt_stub.S */ 9333/* 9334 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9335 * any interesting requests and then jump to the real instruction 9336 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9337 */ 9338 .extern MterpCheckBefore 9339 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9340 adr lr, artMterpAsmInstructionStart + (120 * 128) // Addr of primary handler. 9341 mov x0, xSELF 9342 add x1, xFP, #OFF_FP_SHADOWFRAME 9343 mov x2, xPC 9344 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9345 9346/* ------------------------------ */ 9347 .balign 128 9348.L_ALT_op_unused_79: /* 0x79 */ 9349/* File: arm64/alt_stub.S */ 9350/* 9351 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9352 * any interesting requests and then jump to the real instruction 9353 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9354 */ 9355 .extern MterpCheckBefore 9356 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9357 adr lr, artMterpAsmInstructionStart + (121 * 128) // Addr of primary handler. 9358 mov x0, xSELF 9359 add x1, xFP, #OFF_FP_SHADOWFRAME 9360 mov x2, xPC 9361 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9362 9363/* ------------------------------ */ 9364 .balign 128 9365.L_ALT_op_unused_7a: /* 0x7a */ 9366/* File: arm64/alt_stub.S */ 9367/* 9368 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9369 * any interesting requests and then jump to the real instruction 9370 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9371 */ 9372 .extern MterpCheckBefore 9373 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9374 adr lr, artMterpAsmInstructionStart + (122 * 128) // Addr of primary handler. 9375 mov x0, xSELF 9376 add x1, xFP, #OFF_FP_SHADOWFRAME 9377 mov x2, xPC 9378 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9379 9380/* ------------------------------ */ 9381 .balign 128 9382.L_ALT_op_neg_int: /* 0x7b */ 9383/* File: arm64/alt_stub.S */ 9384/* 9385 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9386 * any interesting requests and then jump to the real instruction 9387 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9388 */ 9389 .extern MterpCheckBefore 9390 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9391 adr lr, artMterpAsmInstructionStart + (123 * 128) // Addr of primary handler. 9392 mov x0, xSELF 9393 add x1, xFP, #OFF_FP_SHADOWFRAME 9394 mov x2, xPC 9395 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9396 9397/* ------------------------------ */ 9398 .balign 128 9399.L_ALT_op_not_int: /* 0x7c */ 9400/* File: arm64/alt_stub.S */ 9401/* 9402 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9403 * any interesting requests and then jump to the real instruction 9404 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9405 */ 9406 .extern MterpCheckBefore 9407 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9408 adr lr, artMterpAsmInstructionStart + (124 * 128) // Addr of primary handler. 9409 mov x0, xSELF 9410 add x1, xFP, #OFF_FP_SHADOWFRAME 9411 mov x2, xPC 9412 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9413 9414/* ------------------------------ */ 9415 .balign 128 9416.L_ALT_op_neg_long: /* 0x7d */ 9417/* File: arm64/alt_stub.S */ 9418/* 9419 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9420 * any interesting requests and then jump to the real instruction 9421 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9422 */ 9423 .extern MterpCheckBefore 9424 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9425 adr lr, artMterpAsmInstructionStart + (125 * 128) // Addr of primary handler. 9426 mov x0, xSELF 9427 add x1, xFP, #OFF_FP_SHADOWFRAME 9428 mov x2, xPC 9429 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9430 9431/* ------------------------------ */ 9432 .balign 128 9433.L_ALT_op_not_long: /* 0x7e */ 9434/* File: arm64/alt_stub.S */ 9435/* 9436 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9437 * any interesting requests and then jump to the real instruction 9438 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9439 */ 9440 .extern MterpCheckBefore 9441 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9442 adr lr, artMterpAsmInstructionStart + (126 * 128) // Addr of primary handler. 9443 mov x0, xSELF 9444 add x1, xFP, #OFF_FP_SHADOWFRAME 9445 mov x2, xPC 9446 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9447 9448/* ------------------------------ */ 9449 .balign 128 9450.L_ALT_op_neg_float: /* 0x7f */ 9451/* File: arm64/alt_stub.S */ 9452/* 9453 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9454 * any interesting requests and then jump to the real instruction 9455 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9456 */ 9457 .extern MterpCheckBefore 9458 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9459 adr lr, artMterpAsmInstructionStart + (127 * 128) // Addr of primary handler. 9460 mov x0, xSELF 9461 add x1, xFP, #OFF_FP_SHADOWFRAME 9462 mov x2, xPC 9463 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9464 9465/* ------------------------------ */ 9466 .balign 128 9467.L_ALT_op_neg_double: /* 0x80 */ 9468/* File: arm64/alt_stub.S */ 9469/* 9470 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9471 * any interesting requests and then jump to the real instruction 9472 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9473 */ 9474 .extern MterpCheckBefore 9475 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9476 adr lr, artMterpAsmInstructionStart + (128 * 128) // Addr of primary handler. 9477 mov x0, xSELF 9478 add x1, xFP, #OFF_FP_SHADOWFRAME 9479 mov x2, xPC 9480 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9481 9482/* ------------------------------ */ 9483 .balign 128 9484.L_ALT_op_int_to_long: /* 0x81 */ 9485/* File: arm64/alt_stub.S */ 9486/* 9487 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9488 * any interesting requests and then jump to the real instruction 9489 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9490 */ 9491 .extern MterpCheckBefore 9492 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9493 adr lr, artMterpAsmInstructionStart + (129 * 128) // Addr of primary handler. 9494 mov x0, xSELF 9495 add x1, xFP, #OFF_FP_SHADOWFRAME 9496 mov x2, xPC 9497 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9498 9499/* ------------------------------ */ 9500 .balign 128 9501.L_ALT_op_int_to_float: /* 0x82 */ 9502/* File: arm64/alt_stub.S */ 9503/* 9504 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9505 * any interesting requests and then jump to the real instruction 9506 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9507 */ 9508 .extern MterpCheckBefore 9509 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9510 adr lr, artMterpAsmInstructionStart + (130 * 128) // Addr of primary handler. 9511 mov x0, xSELF 9512 add x1, xFP, #OFF_FP_SHADOWFRAME 9513 mov x2, xPC 9514 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9515 9516/* ------------------------------ */ 9517 .balign 128 9518.L_ALT_op_int_to_double: /* 0x83 */ 9519/* File: arm64/alt_stub.S */ 9520/* 9521 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9522 * any interesting requests and then jump to the real instruction 9523 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9524 */ 9525 .extern MterpCheckBefore 9526 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9527 adr lr, artMterpAsmInstructionStart + (131 * 128) // Addr of primary handler. 9528 mov x0, xSELF 9529 add x1, xFP, #OFF_FP_SHADOWFRAME 9530 mov x2, xPC 9531 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9532 9533/* ------------------------------ */ 9534 .balign 128 9535.L_ALT_op_long_to_int: /* 0x84 */ 9536/* File: arm64/alt_stub.S */ 9537/* 9538 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9539 * any interesting requests and then jump to the real instruction 9540 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9541 */ 9542 .extern MterpCheckBefore 9543 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9544 adr lr, artMterpAsmInstructionStart + (132 * 128) // Addr of primary handler. 9545 mov x0, xSELF 9546 add x1, xFP, #OFF_FP_SHADOWFRAME 9547 mov x2, xPC 9548 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9549 9550/* ------------------------------ */ 9551 .balign 128 9552.L_ALT_op_long_to_float: /* 0x85 */ 9553/* File: arm64/alt_stub.S */ 9554/* 9555 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9556 * any interesting requests and then jump to the real instruction 9557 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9558 */ 9559 .extern MterpCheckBefore 9560 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9561 adr lr, artMterpAsmInstructionStart + (133 * 128) // Addr of primary handler. 9562 mov x0, xSELF 9563 add x1, xFP, #OFF_FP_SHADOWFRAME 9564 mov x2, xPC 9565 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9566 9567/* ------------------------------ */ 9568 .balign 128 9569.L_ALT_op_long_to_double: /* 0x86 */ 9570/* File: arm64/alt_stub.S */ 9571/* 9572 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9573 * any interesting requests and then jump to the real instruction 9574 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9575 */ 9576 .extern MterpCheckBefore 9577 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9578 adr lr, artMterpAsmInstructionStart + (134 * 128) // Addr of primary handler. 9579 mov x0, xSELF 9580 add x1, xFP, #OFF_FP_SHADOWFRAME 9581 mov x2, xPC 9582 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9583 9584/* ------------------------------ */ 9585 .balign 128 9586.L_ALT_op_float_to_int: /* 0x87 */ 9587/* File: arm64/alt_stub.S */ 9588/* 9589 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9590 * any interesting requests and then jump to the real instruction 9591 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9592 */ 9593 .extern MterpCheckBefore 9594 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9595 adr lr, artMterpAsmInstructionStart + (135 * 128) // Addr of primary handler. 9596 mov x0, xSELF 9597 add x1, xFP, #OFF_FP_SHADOWFRAME 9598 mov x2, xPC 9599 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9600 9601/* ------------------------------ */ 9602 .balign 128 9603.L_ALT_op_float_to_long: /* 0x88 */ 9604/* File: arm64/alt_stub.S */ 9605/* 9606 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9607 * any interesting requests and then jump to the real instruction 9608 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9609 */ 9610 .extern MterpCheckBefore 9611 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9612 adr lr, artMterpAsmInstructionStart + (136 * 128) // Addr of primary handler. 9613 mov x0, xSELF 9614 add x1, xFP, #OFF_FP_SHADOWFRAME 9615 mov x2, xPC 9616 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9617 9618/* ------------------------------ */ 9619 .balign 128 9620.L_ALT_op_float_to_double: /* 0x89 */ 9621/* File: arm64/alt_stub.S */ 9622/* 9623 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9624 * any interesting requests and then jump to the real instruction 9625 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9626 */ 9627 .extern MterpCheckBefore 9628 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9629 adr lr, artMterpAsmInstructionStart + (137 * 128) // Addr of primary handler. 9630 mov x0, xSELF 9631 add x1, xFP, #OFF_FP_SHADOWFRAME 9632 mov x2, xPC 9633 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9634 9635/* ------------------------------ */ 9636 .balign 128 9637.L_ALT_op_double_to_int: /* 0x8a */ 9638/* File: arm64/alt_stub.S */ 9639/* 9640 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9641 * any interesting requests and then jump to the real instruction 9642 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9643 */ 9644 .extern MterpCheckBefore 9645 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9646 adr lr, artMterpAsmInstructionStart + (138 * 128) // Addr of primary handler. 9647 mov x0, xSELF 9648 add x1, xFP, #OFF_FP_SHADOWFRAME 9649 mov x2, xPC 9650 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9651 9652/* ------------------------------ */ 9653 .balign 128 9654.L_ALT_op_double_to_long: /* 0x8b */ 9655/* File: arm64/alt_stub.S */ 9656/* 9657 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9658 * any interesting requests and then jump to the real instruction 9659 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9660 */ 9661 .extern MterpCheckBefore 9662 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9663 adr lr, artMterpAsmInstructionStart + (139 * 128) // Addr of primary handler. 9664 mov x0, xSELF 9665 add x1, xFP, #OFF_FP_SHADOWFRAME 9666 mov x2, xPC 9667 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9668 9669/* ------------------------------ */ 9670 .balign 128 9671.L_ALT_op_double_to_float: /* 0x8c */ 9672/* File: arm64/alt_stub.S */ 9673/* 9674 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9675 * any interesting requests and then jump to the real instruction 9676 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9677 */ 9678 .extern MterpCheckBefore 9679 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9680 adr lr, artMterpAsmInstructionStart + (140 * 128) // Addr of primary handler. 9681 mov x0, xSELF 9682 add x1, xFP, #OFF_FP_SHADOWFRAME 9683 mov x2, xPC 9684 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9685 9686/* ------------------------------ */ 9687 .balign 128 9688.L_ALT_op_int_to_byte: /* 0x8d */ 9689/* File: arm64/alt_stub.S */ 9690/* 9691 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9692 * any interesting requests and then jump to the real instruction 9693 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9694 */ 9695 .extern MterpCheckBefore 9696 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9697 adr lr, artMterpAsmInstructionStart + (141 * 128) // Addr of primary handler. 9698 mov x0, xSELF 9699 add x1, xFP, #OFF_FP_SHADOWFRAME 9700 mov x2, xPC 9701 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9702 9703/* ------------------------------ */ 9704 .balign 128 9705.L_ALT_op_int_to_char: /* 0x8e */ 9706/* File: arm64/alt_stub.S */ 9707/* 9708 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9709 * any interesting requests and then jump to the real instruction 9710 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9711 */ 9712 .extern MterpCheckBefore 9713 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9714 adr lr, artMterpAsmInstructionStart + (142 * 128) // Addr of primary handler. 9715 mov x0, xSELF 9716 add x1, xFP, #OFF_FP_SHADOWFRAME 9717 mov x2, xPC 9718 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9719 9720/* ------------------------------ */ 9721 .balign 128 9722.L_ALT_op_int_to_short: /* 0x8f */ 9723/* File: arm64/alt_stub.S */ 9724/* 9725 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9726 * any interesting requests and then jump to the real instruction 9727 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9728 */ 9729 .extern MterpCheckBefore 9730 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9731 adr lr, artMterpAsmInstructionStart + (143 * 128) // Addr of primary handler. 9732 mov x0, xSELF 9733 add x1, xFP, #OFF_FP_SHADOWFRAME 9734 mov x2, xPC 9735 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9736 9737/* ------------------------------ */ 9738 .balign 128 9739.L_ALT_op_add_int: /* 0x90 */ 9740/* File: arm64/alt_stub.S */ 9741/* 9742 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9743 * any interesting requests and then jump to the real instruction 9744 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9745 */ 9746 .extern MterpCheckBefore 9747 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9748 adr lr, artMterpAsmInstructionStart + (144 * 128) // Addr of primary handler. 9749 mov x0, xSELF 9750 add x1, xFP, #OFF_FP_SHADOWFRAME 9751 mov x2, xPC 9752 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9753 9754/* ------------------------------ */ 9755 .balign 128 9756.L_ALT_op_sub_int: /* 0x91 */ 9757/* File: arm64/alt_stub.S */ 9758/* 9759 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9760 * any interesting requests and then jump to the real instruction 9761 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9762 */ 9763 .extern MterpCheckBefore 9764 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9765 adr lr, artMterpAsmInstructionStart + (145 * 128) // Addr of primary handler. 9766 mov x0, xSELF 9767 add x1, xFP, #OFF_FP_SHADOWFRAME 9768 mov x2, xPC 9769 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9770 9771/* ------------------------------ */ 9772 .balign 128 9773.L_ALT_op_mul_int: /* 0x92 */ 9774/* File: arm64/alt_stub.S */ 9775/* 9776 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9777 * any interesting requests and then jump to the real instruction 9778 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9779 */ 9780 .extern MterpCheckBefore 9781 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9782 adr lr, artMterpAsmInstructionStart + (146 * 128) // Addr of primary handler. 9783 mov x0, xSELF 9784 add x1, xFP, #OFF_FP_SHADOWFRAME 9785 mov x2, xPC 9786 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9787 9788/* ------------------------------ */ 9789 .balign 128 9790.L_ALT_op_div_int: /* 0x93 */ 9791/* File: arm64/alt_stub.S */ 9792/* 9793 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9794 * any interesting requests and then jump to the real instruction 9795 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9796 */ 9797 .extern MterpCheckBefore 9798 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9799 adr lr, artMterpAsmInstructionStart + (147 * 128) // Addr of primary handler. 9800 mov x0, xSELF 9801 add x1, xFP, #OFF_FP_SHADOWFRAME 9802 mov x2, xPC 9803 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9804 9805/* ------------------------------ */ 9806 .balign 128 9807.L_ALT_op_rem_int: /* 0x94 */ 9808/* File: arm64/alt_stub.S */ 9809/* 9810 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9811 * any interesting requests and then jump to the real instruction 9812 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9813 */ 9814 .extern MterpCheckBefore 9815 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9816 adr lr, artMterpAsmInstructionStart + (148 * 128) // Addr of primary handler. 9817 mov x0, xSELF 9818 add x1, xFP, #OFF_FP_SHADOWFRAME 9819 mov x2, xPC 9820 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9821 9822/* ------------------------------ */ 9823 .balign 128 9824.L_ALT_op_and_int: /* 0x95 */ 9825/* File: arm64/alt_stub.S */ 9826/* 9827 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9828 * any interesting requests and then jump to the real instruction 9829 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9830 */ 9831 .extern MterpCheckBefore 9832 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9833 adr lr, artMterpAsmInstructionStart + (149 * 128) // Addr of primary handler. 9834 mov x0, xSELF 9835 add x1, xFP, #OFF_FP_SHADOWFRAME 9836 mov x2, xPC 9837 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9838 9839/* ------------------------------ */ 9840 .balign 128 9841.L_ALT_op_or_int: /* 0x96 */ 9842/* File: arm64/alt_stub.S */ 9843/* 9844 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9845 * any interesting requests and then jump to the real instruction 9846 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9847 */ 9848 .extern MterpCheckBefore 9849 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9850 adr lr, artMterpAsmInstructionStart + (150 * 128) // Addr of primary handler. 9851 mov x0, xSELF 9852 add x1, xFP, #OFF_FP_SHADOWFRAME 9853 mov x2, xPC 9854 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9855 9856/* ------------------------------ */ 9857 .balign 128 9858.L_ALT_op_xor_int: /* 0x97 */ 9859/* File: arm64/alt_stub.S */ 9860/* 9861 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9862 * any interesting requests and then jump to the real instruction 9863 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9864 */ 9865 .extern MterpCheckBefore 9866 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9867 adr lr, artMterpAsmInstructionStart + (151 * 128) // Addr of primary handler. 9868 mov x0, xSELF 9869 add x1, xFP, #OFF_FP_SHADOWFRAME 9870 mov x2, xPC 9871 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9872 9873/* ------------------------------ */ 9874 .balign 128 9875.L_ALT_op_shl_int: /* 0x98 */ 9876/* File: arm64/alt_stub.S */ 9877/* 9878 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9879 * any interesting requests and then jump to the real instruction 9880 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9881 */ 9882 .extern MterpCheckBefore 9883 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9884 adr lr, artMterpAsmInstructionStart + (152 * 128) // Addr of primary handler. 9885 mov x0, xSELF 9886 add x1, xFP, #OFF_FP_SHADOWFRAME 9887 mov x2, xPC 9888 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9889 9890/* ------------------------------ */ 9891 .balign 128 9892.L_ALT_op_shr_int: /* 0x99 */ 9893/* File: arm64/alt_stub.S */ 9894/* 9895 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9896 * any interesting requests and then jump to the real instruction 9897 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9898 */ 9899 .extern MterpCheckBefore 9900 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9901 adr lr, artMterpAsmInstructionStart + (153 * 128) // Addr of primary handler. 9902 mov x0, xSELF 9903 add x1, xFP, #OFF_FP_SHADOWFRAME 9904 mov x2, xPC 9905 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9906 9907/* ------------------------------ */ 9908 .balign 128 9909.L_ALT_op_ushr_int: /* 0x9a */ 9910/* File: arm64/alt_stub.S */ 9911/* 9912 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9913 * any interesting requests and then jump to the real instruction 9914 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9915 */ 9916 .extern MterpCheckBefore 9917 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9918 adr lr, artMterpAsmInstructionStart + (154 * 128) // Addr of primary handler. 9919 mov x0, xSELF 9920 add x1, xFP, #OFF_FP_SHADOWFRAME 9921 mov x2, xPC 9922 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9923 9924/* ------------------------------ */ 9925 .balign 128 9926.L_ALT_op_add_long: /* 0x9b */ 9927/* File: arm64/alt_stub.S */ 9928/* 9929 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9930 * any interesting requests and then jump to the real instruction 9931 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9932 */ 9933 .extern MterpCheckBefore 9934 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9935 adr lr, artMterpAsmInstructionStart + (155 * 128) // Addr of primary handler. 9936 mov x0, xSELF 9937 add x1, xFP, #OFF_FP_SHADOWFRAME 9938 mov x2, xPC 9939 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9940 9941/* ------------------------------ */ 9942 .balign 128 9943.L_ALT_op_sub_long: /* 0x9c */ 9944/* File: arm64/alt_stub.S */ 9945/* 9946 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9947 * any interesting requests and then jump to the real instruction 9948 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9949 */ 9950 .extern MterpCheckBefore 9951 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9952 adr lr, artMterpAsmInstructionStart + (156 * 128) // Addr of primary handler. 9953 mov x0, xSELF 9954 add x1, xFP, #OFF_FP_SHADOWFRAME 9955 mov x2, xPC 9956 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9957 9958/* ------------------------------ */ 9959 .balign 128 9960.L_ALT_op_mul_long: /* 0x9d */ 9961/* File: arm64/alt_stub.S */ 9962/* 9963 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9964 * any interesting requests and then jump to the real instruction 9965 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9966 */ 9967 .extern MterpCheckBefore 9968 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9969 adr lr, artMterpAsmInstructionStart + (157 * 128) // Addr of primary handler. 9970 mov x0, xSELF 9971 add x1, xFP, #OFF_FP_SHADOWFRAME 9972 mov x2, xPC 9973 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9974 9975/* ------------------------------ */ 9976 .balign 128 9977.L_ALT_op_div_long: /* 0x9e */ 9978/* File: arm64/alt_stub.S */ 9979/* 9980 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9981 * any interesting requests and then jump to the real instruction 9982 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9983 */ 9984 .extern MterpCheckBefore 9985 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9986 adr lr, artMterpAsmInstructionStart + (158 * 128) // Addr of primary handler. 9987 mov x0, xSELF 9988 add x1, xFP, #OFF_FP_SHADOWFRAME 9989 mov x2, xPC 9990 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 9991 9992/* ------------------------------ */ 9993 .balign 128 9994.L_ALT_op_rem_long: /* 0x9f */ 9995/* File: arm64/alt_stub.S */ 9996/* 9997 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9998 * any interesting requests and then jump to the real instruction 9999 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10000 */ 10001 .extern MterpCheckBefore 10002 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10003 adr lr, artMterpAsmInstructionStart + (159 * 128) // Addr of primary handler. 10004 mov x0, xSELF 10005 add x1, xFP, #OFF_FP_SHADOWFRAME 10006 mov x2, xPC 10007 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10008 10009/* ------------------------------ */ 10010 .balign 128 10011.L_ALT_op_and_long: /* 0xa0 */ 10012/* File: arm64/alt_stub.S */ 10013/* 10014 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10015 * any interesting requests and then jump to the real instruction 10016 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10017 */ 10018 .extern MterpCheckBefore 10019 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10020 adr lr, artMterpAsmInstructionStart + (160 * 128) // Addr of primary handler. 10021 mov x0, xSELF 10022 add x1, xFP, #OFF_FP_SHADOWFRAME 10023 mov x2, xPC 10024 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10025 10026/* ------------------------------ */ 10027 .balign 128 10028.L_ALT_op_or_long: /* 0xa1 */ 10029/* File: arm64/alt_stub.S */ 10030/* 10031 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10032 * any interesting requests and then jump to the real instruction 10033 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10034 */ 10035 .extern MterpCheckBefore 10036 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10037 adr lr, artMterpAsmInstructionStart + (161 * 128) // Addr of primary handler. 10038 mov x0, xSELF 10039 add x1, xFP, #OFF_FP_SHADOWFRAME 10040 mov x2, xPC 10041 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10042 10043/* ------------------------------ */ 10044 .balign 128 10045.L_ALT_op_xor_long: /* 0xa2 */ 10046/* File: arm64/alt_stub.S */ 10047/* 10048 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10049 * any interesting requests and then jump to the real instruction 10050 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10051 */ 10052 .extern MterpCheckBefore 10053 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10054 adr lr, artMterpAsmInstructionStart + (162 * 128) // Addr of primary handler. 10055 mov x0, xSELF 10056 add x1, xFP, #OFF_FP_SHADOWFRAME 10057 mov x2, xPC 10058 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10059 10060/* ------------------------------ */ 10061 .balign 128 10062.L_ALT_op_shl_long: /* 0xa3 */ 10063/* File: arm64/alt_stub.S */ 10064/* 10065 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10066 * any interesting requests and then jump to the real instruction 10067 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10068 */ 10069 .extern MterpCheckBefore 10070 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10071 adr lr, artMterpAsmInstructionStart + (163 * 128) // Addr of primary handler. 10072 mov x0, xSELF 10073 add x1, xFP, #OFF_FP_SHADOWFRAME 10074 mov x2, xPC 10075 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10076 10077/* ------------------------------ */ 10078 .balign 128 10079.L_ALT_op_shr_long: /* 0xa4 */ 10080/* File: arm64/alt_stub.S */ 10081/* 10082 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10083 * any interesting requests and then jump to the real instruction 10084 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10085 */ 10086 .extern MterpCheckBefore 10087 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10088 adr lr, artMterpAsmInstructionStart + (164 * 128) // Addr of primary handler. 10089 mov x0, xSELF 10090 add x1, xFP, #OFF_FP_SHADOWFRAME 10091 mov x2, xPC 10092 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10093 10094/* ------------------------------ */ 10095 .balign 128 10096.L_ALT_op_ushr_long: /* 0xa5 */ 10097/* File: arm64/alt_stub.S */ 10098/* 10099 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10100 * any interesting requests and then jump to the real instruction 10101 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10102 */ 10103 .extern MterpCheckBefore 10104 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10105 adr lr, artMterpAsmInstructionStart + (165 * 128) // Addr of primary handler. 10106 mov x0, xSELF 10107 add x1, xFP, #OFF_FP_SHADOWFRAME 10108 mov x2, xPC 10109 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10110 10111/* ------------------------------ */ 10112 .balign 128 10113.L_ALT_op_add_float: /* 0xa6 */ 10114/* File: arm64/alt_stub.S */ 10115/* 10116 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10117 * any interesting requests and then jump to the real instruction 10118 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10119 */ 10120 .extern MterpCheckBefore 10121 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10122 adr lr, artMterpAsmInstructionStart + (166 * 128) // Addr of primary handler. 10123 mov x0, xSELF 10124 add x1, xFP, #OFF_FP_SHADOWFRAME 10125 mov x2, xPC 10126 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10127 10128/* ------------------------------ */ 10129 .balign 128 10130.L_ALT_op_sub_float: /* 0xa7 */ 10131/* File: arm64/alt_stub.S */ 10132/* 10133 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10134 * any interesting requests and then jump to the real instruction 10135 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10136 */ 10137 .extern MterpCheckBefore 10138 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10139 adr lr, artMterpAsmInstructionStart + (167 * 128) // Addr of primary handler. 10140 mov x0, xSELF 10141 add x1, xFP, #OFF_FP_SHADOWFRAME 10142 mov x2, xPC 10143 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10144 10145/* ------------------------------ */ 10146 .balign 128 10147.L_ALT_op_mul_float: /* 0xa8 */ 10148/* File: arm64/alt_stub.S */ 10149/* 10150 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10151 * any interesting requests and then jump to the real instruction 10152 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10153 */ 10154 .extern MterpCheckBefore 10155 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10156 adr lr, artMterpAsmInstructionStart + (168 * 128) // Addr of primary handler. 10157 mov x0, xSELF 10158 add x1, xFP, #OFF_FP_SHADOWFRAME 10159 mov x2, xPC 10160 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10161 10162/* ------------------------------ */ 10163 .balign 128 10164.L_ALT_op_div_float: /* 0xa9 */ 10165/* File: arm64/alt_stub.S */ 10166/* 10167 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10168 * any interesting requests and then jump to the real instruction 10169 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10170 */ 10171 .extern MterpCheckBefore 10172 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10173 adr lr, artMterpAsmInstructionStart + (169 * 128) // Addr of primary handler. 10174 mov x0, xSELF 10175 add x1, xFP, #OFF_FP_SHADOWFRAME 10176 mov x2, xPC 10177 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10178 10179/* ------------------------------ */ 10180 .balign 128 10181.L_ALT_op_rem_float: /* 0xaa */ 10182/* File: arm64/alt_stub.S */ 10183/* 10184 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10185 * any interesting requests and then jump to the real instruction 10186 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10187 */ 10188 .extern MterpCheckBefore 10189 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10190 adr lr, artMterpAsmInstructionStart + (170 * 128) // Addr of primary handler. 10191 mov x0, xSELF 10192 add x1, xFP, #OFF_FP_SHADOWFRAME 10193 mov x2, xPC 10194 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10195 10196/* ------------------------------ */ 10197 .balign 128 10198.L_ALT_op_add_double: /* 0xab */ 10199/* File: arm64/alt_stub.S */ 10200/* 10201 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10202 * any interesting requests and then jump to the real instruction 10203 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10204 */ 10205 .extern MterpCheckBefore 10206 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10207 adr lr, artMterpAsmInstructionStart + (171 * 128) // Addr of primary handler. 10208 mov x0, xSELF 10209 add x1, xFP, #OFF_FP_SHADOWFRAME 10210 mov x2, xPC 10211 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10212 10213/* ------------------------------ */ 10214 .balign 128 10215.L_ALT_op_sub_double: /* 0xac */ 10216/* File: arm64/alt_stub.S */ 10217/* 10218 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10219 * any interesting requests and then jump to the real instruction 10220 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10221 */ 10222 .extern MterpCheckBefore 10223 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10224 adr lr, artMterpAsmInstructionStart + (172 * 128) // Addr of primary handler. 10225 mov x0, xSELF 10226 add x1, xFP, #OFF_FP_SHADOWFRAME 10227 mov x2, xPC 10228 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10229 10230/* ------------------------------ */ 10231 .balign 128 10232.L_ALT_op_mul_double: /* 0xad */ 10233/* File: arm64/alt_stub.S */ 10234/* 10235 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10236 * any interesting requests and then jump to the real instruction 10237 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10238 */ 10239 .extern MterpCheckBefore 10240 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10241 adr lr, artMterpAsmInstructionStart + (173 * 128) // Addr of primary handler. 10242 mov x0, xSELF 10243 add x1, xFP, #OFF_FP_SHADOWFRAME 10244 mov x2, xPC 10245 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10246 10247/* ------------------------------ */ 10248 .balign 128 10249.L_ALT_op_div_double: /* 0xae */ 10250/* File: arm64/alt_stub.S */ 10251/* 10252 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10253 * any interesting requests and then jump to the real instruction 10254 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10255 */ 10256 .extern MterpCheckBefore 10257 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10258 adr lr, artMterpAsmInstructionStart + (174 * 128) // Addr of primary handler. 10259 mov x0, xSELF 10260 add x1, xFP, #OFF_FP_SHADOWFRAME 10261 mov x2, xPC 10262 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10263 10264/* ------------------------------ */ 10265 .balign 128 10266.L_ALT_op_rem_double: /* 0xaf */ 10267/* File: arm64/alt_stub.S */ 10268/* 10269 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10270 * any interesting requests and then jump to the real instruction 10271 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10272 */ 10273 .extern MterpCheckBefore 10274 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10275 adr lr, artMterpAsmInstructionStart + (175 * 128) // Addr of primary handler. 10276 mov x0, xSELF 10277 add x1, xFP, #OFF_FP_SHADOWFRAME 10278 mov x2, xPC 10279 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10280 10281/* ------------------------------ */ 10282 .balign 128 10283.L_ALT_op_add_int_2addr: /* 0xb0 */ 10284/* File: arm64/alt_stub.S */ 10285/* 10286 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10287 * any interesting requests and then jump to the real instruction 10288 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10289 */ 10290 .extern MterpCheckBefore 10291 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10292 adr lr, artMterpAsmInstructionStart + (176 * 128) // Addr of primary handler. 10293 mov x0, xSELF 10294 add x1, xFP, #OFF_FP_SHADOWFRAME 10295 mov x2, xPC 10296 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10297 10298/* ------------------------------ */ 10299 .balign 128 10300.L_ALT_op_sub_int_2addr: /* 0xb1 */ 10301/* File: arm64/alt_stub.S */ 10302/* 10303 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10304 * any interesting requests and then jump to the real instruction 10305 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10306 */ 10307 .extern MterpCheckBefore 10308 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10309 adr lr, artMterpAsmInstructionStart + (177 * 128) // Addr of primary handler. 10310 mov x0, xSELF 10311 add x1, xFP, #OFF_FP_SHADOWFRAME 10312 mov x2, xPC 10313 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10314 10315/* ------------------------------ */ 10316 .balign 128 10317.L_ALT_op_mul_int_2addr: /* 0xb2 */ 10318/* File: arm64/alt_stub.S */ 10319/* 10320 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10321 * any interesting requests and then jump to the real instruction 10322 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10323 */ 10324 .extern MterpCheckBefore 10325 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10326 adr lr, artMterpAsmInstructionStart + (178 * 128) // Addr of primary handler. 10327 mov x0, xSELF 10328 add x1, xFP, #OFF_FP_SHADOWFRAME 10329 mov x2, xPC 10330 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10331 10332/* ------------------------------ */ 10333 .balign 128 10334.L_ALT_op_div_int_2addr: /* 0xb3 */ 10335/* File: arm64/alt_stub.S */ 10336/* 10337 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10338 * any interesting requests and then jump to the real instruction 10339 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10340 */ 10341 .extern MterpCheckBefore 10342 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10343 adr lr, artMterpAsmInstructionStart + (179 * 128) // Addr of primary handler. 10344 mov x0, xSELF 10345 add x1, xFP, #OFF_FP_SHADOWFRAME 10346 mov x2, xPC 10347 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10348 10349/* ------------------------------ */ 10350 .balign 128 10351.L_ALT_op_rem_int_2addr: /* 0xb4 */ 10352/* File: arm64/alt_stub.S */ 10353/* 10354 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10355 * any interesting requests and then jump to the real instruction 10356 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10357 */ 10358 .extern MterpCheckBefore 10359 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10360 adr lr, artMterpAsmInstructionStart + (180 * 128) // Addr of primary handler. 10361 mov x0, xSELF 10362 add x1, xFP, #OFF_FP_SHADOWFRAME 10363 mov x2, xPC 10364 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10365 10366/* ------------------------------ */ 10367 .balign 128 10368.L_ALT_op_and_int_2addr: /* 0xb5 */ 10369/* File: arm64/alt_stub.S */ 10370/* 10371 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10372 * any interesting requests and then jump to the real instruction 10373 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10374 */ 10375 .extern MterpCheckBefore 10376 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10377 adr lr, artMterpAsmInstructionStart + (181 * 128) // Addr of primary handler. 10378 mov x0, xSELF 10379 add x1, xFP, #OFF_FP_SHADOWFRAME 10380 mov x2, xPC 10381 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10382 10383/* ------------------------------ */ 10384 .balign 128 10385.L_ALT_op_or_int_2addr: /* 0xb6 */ 10386/* File: arm64/alt_stub.S */ 10387/* 10388 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10389 * any interesting requests and then jump to the real instruction 10390 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10391 */ 10392 .extern MterpCheckBefore 10393 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10394 adr lr, artMterpAsmInstructionStart + (182 * 128) // Addr of primary handler. 10395 mov x0, xSELF 10396 add x1, xFP, #OFF_FP_SHADOWFRAME 10397 mov x2, xPC 10398 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10399 10400/* ------------------------------ */ 10401 .balign 128 10402.L_ALT_op_xor_int_2addr: /* 0xb7 */ 10403/* File: arm64/alt_stub.S */ 10404/* 10405 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10406 * any interesting requests and then jump to the real instruction 10407 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10408 */ 10409 .extern MterpCheckBefore 10410 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10411 adr lr, artMterpAsmInstructionStart + (183 * 128) // Addr of primary handler. 10412 mov x0, xSELF 10413 add x1, xFP, #OFF_FP_SHADOWFRAME 10414 mov x2, xPC 10415 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10416 10417/* ------------------------------ */ 10418 .balign 128 10419.L_ALT_op_shl_int_2addr: /* 0xb8 */ 10420/* File: arm64/alt_stub.S */ 10421/* 10422 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10423 * any interesting requests and then jump to the real instruction 10424 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10425 */ 10426 .extern MterpCheckBefore 10427 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10428 adr lr, artMterpAsmInstructionStart + (184 * 128) // Addr of primary handler. 10429 mov x0, xSELF 10430 add x1, xFP, #OFF_FP_SHADOWFRAME 10431 mov x2, xPC 10432 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10433 10434/* ------------------------------ */ 10435 .balign 128 10436.L_ALT_op_shr_int_2addr: /* 0xb9 */ 10437/* File: arm64/alt_stub.S */ 10438/* 10439 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10440 * any interesting requests and then jump to the real instruction 10441 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10442 */ 10443 .extern MterpCheckBefore 10444 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10445 adr lr, artMterpAsmInstructionStart + (185 * 128) // Addr of primary handler. 10446 mov x0, xSELF 10447 add x1, xFP, #OFF_FP_SHADOWFRAME 10448 mov x2, xPC 10449 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10450 10451/* ------------------------------ */ 10452 .balign 128 10453.L_ALT_op_ushr_int_2addr: /* 0xba */ 10454/* File: arm64/alt_stub.S */ 10455/* 10456 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10457 * any interesting requests and then jump to the real instruction 10458 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10459 */ 10460 .extern MterpCheckBefore 10461 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10462 adr lr, artMterpAsmInstructionStart + (186 * 128) // Addr of primary handler. 10463 mov x0, xSELF 10464 add x1, xFP, #OFF_FP_SHADOWFRAME 10465 mov x2, xPC 10466 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10467 10468/* ------------------------------ */ 10469 .balign 128 10470.L_ALT_op_add_long_2addr: /* 0xbb */ 10471/* File: arm64/alt_stub.S */ 10472/* 10473 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10474 * any interesting requests and then jump to the real instruction 10475 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10476 */ 10477 .extern MterpCheckBefore 10478 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10479 adr lr, artMterpAsmInstructionStart + (187 * 128) // Addr of primary handler. 10480 mov x0, xSELF 10481 add x1, xFP, #OFF_FP_SHADOWFRAME 10482 mov x2, xPC 10483 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10484 10485/* ------------------------------ */ 10486 .balign 128 10487.L_ALT_op_sub_long_2addr: /* 0xbc */ 10488/* File: arm64/alt_stub.S */ 10489/* 10490 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10491 * any interesting requests and then jump to the real instruction 10492 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10493 */ 10494 .extern MterpCheckBefore 10495 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10496 adr lr, artMterpAsmInstructionStart + (188 * 128) // Addr of primary handler. 10497 mov x0, xSELF 10498 add x1, xFP, #OFF_FP_SHADOWFRAME 10499 mov x2, xPC 10500 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10501 10502/* ------------------------------ */ 10503 .balign 128 10504.L_ALT_op_mul_long_2addr: /* 0xbd */ 10505/* File: arm64/alt_stub.S */ 10506/* 10507 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10508 * any interesting requests and then jump to the real instruction 10509 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10510 */ 10511 .extern MterpCheckBefore 10512 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10513 adr lr, artMterpAsmInstructionStart + (189 * 128) // Addr of primary handler. 10514 mov x0, xSELF 10515 add x1, xFP, #OFF_FP_SHADOWFRAME 10516 mov x2, xPC 10517 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10518 10519/* ------------------------------ */ 10520 .balign 128 10521.L_ALT_op_div_long_2addr: /* 0xbe */ 10522/* File: arm64/alt_stub.S */ 10523/* 10524 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10525 * any interesting requests and then jump to the real instruction 10526 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10527 */ 10528 .extern MterpCheckBefore 10529 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10530 adr lr, artMterpAsmInstructionStart + (190 * 128) // Addr of primary handler. 10531 mov x0, xSELF 10532 add x1, xFP, #OFF_FP_SHADOWFRAME 10533 mov x2, xPC 10534 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10535 10536/* ------------------------------ */ 10537 .balign 128 10538.L_ALT_op_rem_long_2addr: /* 0xbf */ 10539/* File: arm64/alt_stub.S */ 10540/* 10541 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10542 * any interesting requests and then jump to the real instruction 10543 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10544 */ 10545 .extern MterpCheckBefore 10546 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10547 adr lr, artMterpAsmInstructionStart + (191 * 128) // Addr of primary handler. 10548 mov x0, xSELF 10549 add x1, xFP, #OFF_FP_SHADOWFRAME 10550 mov x2, xPC 10551 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10552 10553/* ------------------------------ */ 10554 .balign 128 10555.L_ALT_op_and_long_2addr: /* 0xc0 */ 10556/* File: arm64/alt_stub.S */ 10557/* 10558 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10559 * any interesting requests and then jump to the real instruction 10560 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10561 */ 10562 .extern MterpCheckBefore 10563 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10564 adr lr, artMterpAsmInstructionStart + (192 * 128) // Addr of primary handler. 10565 mov x0, xSELF 10566 add x1, xFP, #OFF_FP_SHADOWFRAME 10567 mov x2, xPC 10568 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10569 10570/* ------------------------------ */ 10571 .balign 128 10572.L_ALT_op_or_long_2addr: /* 0xc1 */ 10573/* File: arm64/alt_stub.S */ 10574/* 10575 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10576 * any interesting requests and then jump to the real instruction 10577 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10578 */ 10579 .extern MterpCheckBefore 10580 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10581 adr lr, artMterpAsmInstructionStart + (193 * 128) // Addr of primary handler. 10582 mov x0, xSELF 10583 add x1, xFP, #OFF_FP_SHADOWFRAME 10584 mov x2, xPC 10585 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10586 10587/* ------------------------------ */ 10588 .balign 128 10589.L_ALT_op_xor_long_2addr: /* 0xc2 */ 10590/* File: arm64/alt_stub.S */ 10591/* 10592 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10593 * any interesting requests and then jump to the real instruction 10594 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10595 */ 10596 .extern MterpCheckBefore 10597 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10598 adr lr, artMterpAsmInstructionStart + (194 * 128) // Addr of primary handler. 10599 mov x0, xSELF 10600 add x1, xFP, #OFF_FP_SHADOWFRAME 10601 mov x2, xPC 10602 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10603 10604/* ------------------------------ */ 10605 .balign 128 10606.L_ALT_op_shl_long_2addr: /* 0xc3 */ 10607/* File: arm64/alt_stub.S */ 10608/* 10609 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10610 * any interesting requests and then jump to the real instruction 10611 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10612 */ 10613 .extern MterpCheckBefore 10614 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10615 adr lr, artMterpAsmInstructionStart + (195 * 128) // Addr of primary handler. 10616 mov x0, xSELF 10617 add x1, xFP, #OFF_FP_SHADOWFRAME 10618 mov x2, xPC 10619 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10620 10621/* ------------------------------ */ 10622 .balign 128 10623.L_ALT_op_shr_long_2addr: /* 0xc4 */ 10624/* File: arm64/alt_stub.S */ 10625/* 10626 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10627 * any interesting requests and then jump to the real instruction 10628 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10629 */ 10630 .extern MterpCheckBefore 10631 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10632 adr lr, artMterpAsmInstructionStart + (196 * 128) // Addr of primary handler. 10633 mov x0, xSELF 10634 add x1, xFP, #OFF_FP_SHADOWFRAME 10635 mov x2, xPC 10636 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10637 10638/* ------------------------------ */ 10639 .balign 128 10640.L_ALT_op_ushr_long_2addr: /* 0xc5 */ 10641/* File: arm64/alt_stub.S */ 10642/* 10643 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10644 * any interesting requests and then jump to the real instruction 10645 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10646 */ 10647 .extern MterpCheckBefore 10648 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10649 adr lr, artMterpAsmInstructionStart + (197 * 128) // Addr of primary handler. 10650 mov x0, xSELF 10651 add x1, xFP, #OFF_FP_SHADOWFRAME 10652 mov x2, xPC 10653 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10654 10655/* ------------------------------ */ 10656 .balign 128 10657.L_ALT_op_add_float_2addr: /* 0xc6 */ 10658/* File: arm64/alt_stub.S */ 10659/* 10660 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10661 * any interesting requests and then jump to the real instruction 10662 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10663 */ 10664 .extern MterpCheckBefore 10665 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10666 adr lr, artMterpAsmInstructionStart + (198 * 128) // Addr of primary handler. 10667 mov x0, xSELF 10668 add x1, xFP, #OFF_FP_SHADOWFRAME 10669 mov x2, xPC 10670 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10671 10672/* ------------------------------ */ 10673 .balign 128 10674.L_ALT_op_sub_float_2addr: /* 0xc7 */ 10675/* File: arm64/alt_stub.S */ 10676/* 10677 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10678 * any interesting requests and then jump to the real instruction 10679 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10680 */ 10681 .extern MterpCheckBefore 10682 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10683 adr lr, artMterpAsmInstructionStart + (199 * 128) // Addr of primary handler. 10684 mov x0, xSELF 10685 add x1, xFP, #OFF_FP_SHADOWFRAME 10686 mov x2, xPC 10687 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10688 10689/* ------------------------------ */ 10690 .balign 128 10691.L_ALT_op_mul_float_2addr: /* 0xc8 */ 10692/* File: arm64/alt_stub.S */ 10693/* 10694 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10695 * any interesting requests and then jump to the real instruction 10696 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10697 */ 10698 .extern MterpCheckBefore 10699 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10700 adr lr, artMterpAsmInstructionStart + (200 * 128) // Addr of primary handler. 10701 mov x0, xSELF 10702 add x1, xFP, #OFF_FP_SHADOWFRAME 10703 mov x2, xPC 10704 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10705 10706/* ------------------------------ */ 10707 .balign 128 10708.L_ALT_op_div_float_2addr: /* 0xc9 */ 10709/* File: arm64/alt_stub.S */ 10710/* 10711 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10712 * any interesting requests and then jump to the real instruction 10713 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10714 */ 10715 .extern MterpCheckBefore 10716 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10717 adr lr, artMterpAsmInstructionStart + (201 * 128) // Addr of primary handler. 10718 mov x0, xSELF 10719 add x1, xFP, #OFF_FP_SHADOWFRAME 10720 mov x2, xPC 10721 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10722 10723/* ------------------------------ */ 10724 .balign 128 10725.L_ALT_op_rem_float_2addr: /* 0xca */ 10726/* File: arm64/alt_stub.S */ 10727/* 10728 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10729 * any interesting requests and then jump to the real instruction 10730 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10731 */ 10732 .extern MterpCheckBefore 10733 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10734 adr lr, artMterpAsmInstructionStart + (202 * 128) // Addr of primary handler. 10735 mov x0, xSELF 10736 add x1, xFP, #OFF_FP_SHADOWFRAME 10737 mov x2, xPC 10738 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10739 10740/* ------------------------------ */ 10741 .balign 128 10742.L_ALT_op_add_double_2addr: /* 0xcb */ 10743/* File: arm64/alt_stub.S */ 10744/* 10745 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10746 * any interesting requests and then jump to the real instruction 10747 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10748 */ 10749 .extern MterpCheckBefore 10750 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10751 adr lr, artMterpAsmInstructionStart + (203 * 128) // Addr of primary handler. 10752 mov x0, xSELF 10753 add x1, xFP, #OFF_FP_SHADOWFRAME 10754 mov x2, xPC 10755 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10756 10757/* ------------------------------ */ 10758 .balign 128 10759.L_ALT_op_sub_double_2addr: /* 0xcc */ 10760/* File: arm64/alt_stub.S */ 10761/* 10762 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10763 * any interesting requests and then jump to the real instruction 10764 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10765 */ 10766 .extern MterpCheckBefore 10767 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10768 adr lr, artMterpAsmInstructionStart + (204 * 128) // Addr of primary handler. 10769 mov x0, xSELF 10770 add x1, xFP, #OFF_FP_SHADOWFRAME 10771 mov x2, xPC 10772 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10773 10774/* ------------------------------ */ 10775 .balign 128 10776.L_ALT_op_mul_double_2addr: /* 0xcd */ 10777/* File: arm64/alt_stub.S */ 10778/* 10779 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10780 * any interesting requests and then jump to the real instruction 10781 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10782 */ 10783 .extern MterpCheckBefore 10784 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10785 adr lr, artMterpAsmInstructionStart + (205 * 128) // Addr of primary handler. 10786 mov x0, xSELF 10787 add x1, xFP, #OFF_FP_SHADOWFRAME 10788 mov x2, xPC 10789 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10790 10791/* ------------------------------ */ 10792 .balign 128 10793.L_ALT_op_div_double_2addr: /* 0xce */ 10794/* File: arm64/alt_stub.S */ 10795/* 10796 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10797 * any interesting requests and then jump to the real instruction 10798 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10799 */ 10800 .extern MterpCheckBefore 10801 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10802 adr lr, artMterpAsmInstructionStart + (206 * 128) // Addr of primary handler. 10803 mov x0, xSELF 10804 add x1, xFP, #OFF_FP_SHADOWFRAME 10805 mov x2, xPC 10806 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10807 10808/* ------------------------------ */ 10809 .balign 128 10810.L_ALT_op_rem_double_2addr: /* 0xcf */ 10811/* File: arm64/alt_stub.S */ 10812/* 10813 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10814 * any interesting requests and then jump to the real instruction 10815 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10816 */ 10817 .extern MterpCheckBefore 10818 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10819 adr lr, artMterpAsmInstructionStart + (207 * 128) // Addr of primary handler. 10820 mov x0, xSELF 10821 add x1, xFP, #OFF_FP_SHADOWFRAME 10822 mov x2, xPC 10823 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10824 10825/* ------------------------------ */ 10826 .balign 128 10827.L_ALT_op_add_int_lit16: /* 0xd0 */ 10828/* File: arm64/alt_stub.S */ 10829/* 10830 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10831 * any interesting requests and then jump to the real instruction 10832 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10833 */ 10834 .extern MterpCheckBefore 10835 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10836 adr lr, artMterpAsmInstructionStart + (208 * 128) // Addr of primary handler. 10837 mov x0, xSELF 10838 add x1, xFP, #OFF_FP_SHADOWFRAME 10839 mov x2, xPC 10840 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10841 10842/* ------------------------------ */ 10843 .balign 128 10844.L_ALT_op_rsub_int: /* 0xd1 */ 10845/* File: arm64/alt_stub.S */ 10846/* 10847 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10848 * any interesting requests and then jump to the real instruction 10849 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10850 */ 10851 .extern MterpCheckBefore 10852 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10853 adr lr, artMterpAsmInstructionStart + (209 * 128) // Addr of primary handler. 10854 mov x0, xSELF 10855 add x1, xFP, #OFF_FP_SHADOWFRAME 10856 mov x2, xPC 10857 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10858 10859/* ------------------------------ */ 10860 .balign 128 10861.L_ALT_op_mul_int_lit16: /* 0xd2 */ 10862/* File: arm64/alt_stub.S */ 10863/* 10864 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10865 * any interesting requests and then jump to the real instruction 10866 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10867 */ 10868 .extern MterpCheckBefore 10869 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10870 adr lr, artMterpAsmInstructionStart + (210 * 128) // Addr of primary handler. 10871 mov x0, xSELF 10872 add x1, xFP, #OFF_FP_SHADOWFRAME 10873 mov x2, xPC 10874 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10875 10876/* ------------------------------ */ 10877 .balign 128 10878.L_ALT_op_div_int_lit16: /* 0xd3 */ 10879/* File: arm64/alt_stub.S */ 10880/* 10881 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10882 * any interesting requests and then jump to the real instruction 10883 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10884 */ 10885 .extern MterpCheckBefore 10886 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10887 adr lr, artMterpAsmInstructionStart + (211 * 128) // Addr of primary handler. 10888 mov x0, xSELF 10889 add x1, xFP, #OFF_FP_SHADOWFRAME 10890 mov x2, xPC 10891 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10892 10893/* ------------------------------ */ 10894 .balign 128 10895.L_ALT_op_rem_int_lit16: /* 0xd4 */ 10896/* File: arm64/alt_stub.S */ 10897/* 10898 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10899 * any interesting requests and then jump to the real instruction 10900 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10901 */ 10902 .extern MterpCheckBefore 10903 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10904 adr lr, artMterpAsmInstructionStart + (212 * 128) // Addr of primary handler. 10905 mov x0, xSELF 10906 add x1, xFP, #OFF_FP_SHADOWFRAME 10907 mov x2, xPC 10908 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10909 10910/* ------------------------------ */ 10911 .balign 128 10912.L_ALT_op_and_int_lit16: /* 0xd5 */ 10913/* File: arm64/alt_stub.S */ 10914/* 10915 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10916 * any interesting requests and then jump to the real instruction 10917 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10918 */ 10919 .extern MterpCheckBefore 10920 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10921 adr lr, artMterpAsmInstructionStart + (213 * 128) // Addr of primary handler. 10922 mov x0, xSELF 10923 add x1, xFP, #OFF_FP_SHADOWFRAME 10924 mov x2, xPC 10925 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10926 10927/* ------------------------------ */ 10928 .balign 128 10929.L_ALT_op_or_int_lit16: /* 0xd6 */ 10930/* File: arm64/alt_stub.S */ 10931/* 10932 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10933 * any interesting requests and then jump to the real instruction 10934 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10935 */ 10936 .extern MterpCheckBefore 10937 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10938 adr lr, artMterpAsmInstructionStart + (214 * 128) // Addr of primary handler. 10939 mov x0, xSELF 10940 add x1, xFP, #OFF_FP_SHADOWFRAME 10941 mov x2, xPC 10942 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10943 10944/* ------------------------------ */ 10945 .balign 128 10946.L_ALT_op_xor_int_lit16: /* 0xd7 */ 10947/* File: arm64/alt_stub.S */ 10948/* 10949 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10950 * any interesting requests and then jump to the real instruction 10951 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10952 */ 10953 .extern MterpCheckBefore 10954 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10955 adr lr, artMterpAsmInstructionStart + (215 * 128) // Addr of primary handler. 10956 mov x0, xSELF 10957 add x1, xFP, #OFF_FP_SHADOWFRAME 10958 mov x2, xPC 10959 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10960 10961/* ------------------------------ */ 10962 .balign 128 10963.L_ALT_op_add_int_lit8: /* 0xd8 */ 10964/* File: arm64/alt_stub.S */ 10965/* 10966 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10967 * any interesting requests and then jump to the real instruction 10968 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10969 */ 10970 .extern MterpCheckBefore 10971 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10972 adr lr, artMterpAsmInstructionStart + (216 * 128) // Addr of primary handler. 10973 mov x0, xSELF 10974 add x1, xFP, #OFF_FP_SHADOWFRAME 10975 mov x2, xPC 10976 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10977 10978/* ------------------------------ */ 10979 .balign 128 10980.L_ALT_op_rsub_int_lit8: /* 0xd9 */ 10981/* File: arm64/alt_stub.S */ 10982/* 10983 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10984 * any interesting requests and then jump to the real instruction 10985 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10986 */ 10987 .extern MterpCheckBefore 10988 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10989 adr lr, artMterpAsmInstructionStart + (217 * 128) // Addr of primary handler. 10990 mov x0, xSELF 10991 add x1, xFP, #OFF_FP_SHADOWFRAME 10992 mov x2, xPC 10993 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 10994 10995/* ------------------------------ */ 10996 .balign 128 10997.L_ALT_op_mul_int_lit8: /* 0xda */ 10998/* File: arm64/alt_stub.S */ 10999/* 11000 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11001 * any interesting requests and then jump to the real instruction 11002 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11003 */ 11004 .extern MterpCheckBefore 11005 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11006 adr lr, artMterpAsmInstructionStart + (218 * 128) // Addr of primary handler. 11007 mov x0, xSELF 11008 add x1, xFP, #OFF_FP_SHADOWFRAME 11009 mov x2, xPC 11010 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11011 11012/* ------------------------------ */ 11013 .balign 128 11014.L_ALT_op_div_int_lit8: /* 0xdb */ 11015/* File: arm64/alt_stub.S */ 11016/* 11017 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11018 * any interesting requests and then jump to the real instruction 11019 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11020 */ 11021 .extern MterpCheckBefore 11022 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11023 adr lr, artMterpAsmInstructionStart + (219 * 128) // Addr of primary handler. 11024 mov x0, xSELF 11025 add x1, xFP, #OFF_FP_SHADOWFRAME 11026 mov x2, xPC 11027 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11028 11029/* ------------------------------ */ 11030 .balign 128 11031.L_ALT_op_rem_int_lit8: /* 0xdc */ 11032/* File: arm64/alt_stub.S */ 11033/* 11034 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11035 * any interesting requests and then jump to the real instruction 11036 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11037 */ 11038 .extern MterpCheckBefore 11039 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11040 adr lr, artMterpAsmInstructionStart + (220 * 128) // Addr of primary handler. 11041 mov x0, xSELF 11042 add x1, xFP, #OFF_FP_SHADOWFRAME 11043 mov x2, xPC 11044 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11045 11046/* ------------------------------ */ 11047 .balign 128 11048.L_ALT_op_and_int_lit8: /* 0xdd */ 11049/* File: arm64/alt_stub.S */ 11050/* 11051 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11052 * any interesting requests and then jump to the real instruction 11053 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11054 */ 11055 .extern MterpCheckBefore 11056 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11057 adr lr, artMterpAsmInstructionStart + (221 * 128) // Addr of primary handler. 11058 mov x0, xSELF 11059 add x1, xFP, #OFF_FP_SHADOWFRAME 11060 mov x2, xPC 11061 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11062 11063/* ------------------------------ */ 11064 .balign 128 11065.L_ALT_op_or_int_lit8: /* 0xde */ 11066/* File: arm64/alt_stub.S */ 11067/* 11068 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11069 * any interesting requests and then jump to the real instruction 11070 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11071 */ 11072 .extern MterpCheckBefore 11073 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11074 adr lr, artMterpAsmInstructionStart + (222 * 128) // Addr of primary handler. 11075 mov x0, xSELF 11076 add x1, xFP, #OFF_FP_SHADOWFRAME 11077 mov x2, xPC 11078 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11079 11080/* ------------------------------ */ 11081 .balign 128 11082.L_ALT_op_xor_int_lit8: /* 0xdf */ 11083/* File: arm64/alt_stub.S */ 11084/* 11085 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11086 * any interesting requests and then jump to the real instruction 11087 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11088 */ 11089 .extern MterpCheckBefore 11090 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11091 adr lr, artMterpAsmInstructionStart + (223 * 128) // Addr of primary handler. 11092 mov x0, xSELF 11093 add x1, xFP, #OFF_FP_SHADOWFRAME 11094 mov x2, xPC 11095 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11096 11097/* ------------------------------ */ 11098 .balign 128 11099.L_ALT_op_shl_int_lit8: /* 0xe0 */ 11100/* File: arm64/alt_stub.S */ 11101/* 11102 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11103 * any interesting requests and then jump to the real instruction 11104 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11105 */ 11106 .extern MterpCheckBefore 11107 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11108 adr lr, artMterpAsmInstructionStart + (224 * 128) // Addr of primary handler. 11109 mov x0, xSELF 11110 add x1, xFP, #OFF_FP_SHADOWFRAME 11111 mov x2, xPC 11112 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11113 11114/* ------------------------------ */ 11115 .balign 128 11116.L_ALT_op_shr_int_lit8: /* 0xe1 */ 11117/* File: arm64/alt_stub.S */ 11118/* 11119 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11120 * any interesting requests and then jump to the real instruction 11121 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11122 */ 11123 .extern MterpCheckBefore 11124 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11125 adr lr, artMterpAsmInstructionStart + (225 * 128) // Addr of primary handler. 11126 mov x0, xSELF 11127 add x1, xFP, #OFF_FP_SHADOWFRAME 11128 mov x2, xPC 11129 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11130 11131/* ------------------------------ */ 11132 .balign 128 11133.L_ALT_op_ushr_int_lit8: /* 0xe2 */ 11134/* File: arm64/alt_stub.S */ 11135/* 11136 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11137 * any interesting requests and then jump to the real instruction 11138 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11139 */ 11140 .extern MterpCheckBefore 11141 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11142 adr lr, artMterpAsmInstructionStart + (226 * 128) // Addr of primary handler. 11143 mov x0, xSELF 11144 add x1, xFP, #OFF_FP_SHADOWFRAME 11145 mov x2, xPC 11146 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11147 11148/* ------------------------------ */ 11149 .balign 128 11150.L_ALT_op_iget_quick: /* 0xe3 */ 11151/* File: arm64/alt_stub.S */ 11152/* 11153 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11154 * any interesting requests and then jump to the real instruction 11155 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11156 */ 11157 .extern MterpCheckBefore 11158 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11159 adr lr, artMterpAsmInstructionStart + (227 * 128) // Addr of primary handler. 11160 mov x0, xSELF 11161 add x1, xFP, #OFF_FP_SHADOWFRAME 11162 mov x2, xPC 11163 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11164 11165/* ------------------------------ */ 11166 .balign 128 11167.L_ALT_op_iget_wide_quick: /* 0xe4 */ 11168/* File: arm64/alt_stub.S */ 11169/* 11170 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11171 * any interesting requests and then jump to the real instruction 11172 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11173 */ 11174 .extern MterpCheckBefore 11175 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11176 adr lr, artMterpAsmInstructionStart + (228 * 128) // Addr of primary handler. 11177 mov x0, xSELF 11178 add x1, xFP, #OFF_FP_SHADOWFRAME 11179 mov x2, xPC 11180 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11181 11182/* ------------------------------ */ 11183 .balign 128 11184.L_ALT_op_iget_object_quick: /* 0xe5 */ 11185/* File: arm64/alt_stub.S */ 11186/* 11187 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11188 * any interesting requests and then jump to the real instruction 11189 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11190 */ 11191 .extern MterpCheckBefore 11192 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11193 adr lr, artMterpAsmInstructionStart + (229 * 128) // Addr of primary handler. 11194 mov x0, xSELF 11195 add x1, xFP, #OFF_FP_SHADOWFRAME 11196 mov x2, xPC 11197 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11198 11199/* ------------------------------ */ 11200 .balign 128 11201.L_ALT_op_iput_quick: /* 0xe6 */ 11202/* File: arm64/alt_stub.S */ 11203/* 11204 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11205 * any interesting requests and then jump to the real instruction 11206 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11207 */ 11208 .extern MterpCheckBefore 11209 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11210 adr lr, artMterpAsmInstructionStart + (230 * 128) // Addr of primary handler. 11211 mov x0, xSELF 11212 add x1, xFP, #OFF_FP_SHADOWFRAME 11213 mov x2, xPC 11214 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11215 11216/* ------------------------------ */ 11217 .balign 128 11218.L_ALT_op_iput_wide_quick: /* 0xe7 */ 11219/* File: arm64/alt_stub.S */ 11220/* 11221 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11222 * any interesting requests and then jump to the real instruction 11223 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11224 */ 11225 .extern MterpCheckBefore 11226 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11227 adr lr, artMterpAsmInstructionStart + (231 * 128) // Addr of primary handler. 11228 mov x0, xSELF 11229 add x1, xFP, #OFF_FP_SHADOWFRAME 11230 mov x2, xPC 11231 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11232 11233/* ------------------------------ */ 11234 .balign 128 11235.L_ALT_op_iput_object_quick: /* 0xe8 */ 11236/* File: arm64/alt_stub.S */ 11237/* 11238 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11239 * any interesting requests and then jump to the real instruction 11240 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11241 */ 11242 .extern MterpCheckBefore 11243 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11244 adr lr, artMterpAsmInstructionStart + (232 * 128) // Addr of primary handler. 11245 mov x0, xSELF 11246 add x1, xFP, #OFF_FP_SHADOWFRAME 11247 mov x2, xPC 11248 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11249 11250/* ------------------------------ */ 11251 .balign 128 11252.L_ALT_op_invoke_virtual_quick: /* 0xe9 */ 11253/* File: arm64/alt_stub.S */ 11254/* 11255 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11256 * any interesting requests and then jump to the real instruction 11257 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11258 */ 11259 .extern MterpCheckBefore 11260 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11261 adr lr, artMterpAsmInstructionStart + (233 * 128) // Addr of primary handler. 11262 mov x0, xSELF 11263 add x1, xFP, #OFF_FP_SHADOWFRAME 11264 mov x2, xPC 11265 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11266 11267/* ------------------------------ */ 11268 .balign 128 11269.L_ALT_op_invoke_virtual_range_quick: /* 0xea */ 11270/* File: arm64/alt_stub.S */ 11271/* 11272 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11273 * any interesting requests and then jump to the real instruction 11274 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11275 */ 11276 .extern MterpCheckBefore 11277 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11278 adr lr, artMterpAsmInstructionStart + (234 * 128) // Addr of primary handler. 11279 mov x0, xSELF 11280 add x1, xFP, #OFF_FP_SHADOWFRAME 11281 mov x2, xPC 11282 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11283 11284/* ------------------------------ */ 11285 .balign 128 11286.L_ALT_op_iput_boolean_quick: /* 0xeb */ 11287/* File: arm64/alt_stub.S */ 11288/* 11289 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11290 * any interesting requests and then jump to the real instruction 11291 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11292 */ 11293 .extern MterpCheckBefore 11294 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11295 adr lr, artMterpAsmInstructionStart + (235 * 128) // Addr of primary handler. 11296 mov x0, xSELF 11297 add x1, xFP, #OFF_FP_SHADOWFRAME 11298 mov x2, xPC 11299 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11300 11301/* ------------------------------ */ 11302 .balign 128 11303.L_ALT_op_iput_byte_quick: /* 0xec */ 11304/* File: arm64/alt_stub.S */ 11305/* 11306 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11307 * any interesting requests and then jump to the real instruction 11308 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11309 */ 11310 .extern MterpCheckBefore 11311 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11312 adr lr, artMterpAsmInstructionStart + (236 * 128) // Addr of primary handler. 11313 mov x0, xSELF 11314 add x1, xFP, #OFF_FP_SHADOWFRAME 11315 mov x2, xPC 11316 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11317 11318/* ------------------------------ */ 11319 .balign 128 11320.L_ALT_op_iput_char_quick: /* 0xed */ 11321/* File: arm64/alt_stub.S */ 11322/* 11323 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11324 * any interesting requests and then jump to the real instruction 11325 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11326 */ 11327 .extern MterpCheckBefore 11328 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11329 adr lr, artMterpAsmInstructionStart + (237 * 128) // Addr of primary handler. 11330 mov x0, xSELF 11331 add x1, xFP, #OFF_FP_SHADOWFRAME 11332 mov x2, xPC 11333 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11334 11335/* ------------------------------ */ 11336 .balign 128 11337.L_ALT_op_iput_short_quick: /* 0xee */ 11338/* File: arm64/alt_stub.S */ 11339/* 11340 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11341 * any interesting requests and then jump to the real instruction 11342 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11343 */ 11344 .extern MterpCheckBefore 11345 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11346 adr lr, artMterpAsmInstructionStart + (238 * 128) // Addr of primary handler. 11347 mov x0, xSELF 11348 add x1, xFP, #OFF_FP_SHADOWFRAME 11349 mov x2, xPC 11350 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11351 11352/* ------------------------------ */ 11353 .balign 128 11354.L_ALT_op_iget_boolean_quick: /* 0xef */ 11355/* File: arm64/alt_stub.S */ 11356/* 11357 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11358 * any interesting requests and then jump to the real instruction 11359 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11360 */ 11361 .extern MterpCheckBefore 11362 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11363 adr lr, artMterpAsmInstructionStart + (239 * 128) // Addr of primary handler. 11364 mov x0, xSELF 11365 add x1, xFP, #OFF_FP_SHADOWFRAME 11366 mov x2, xPC 11367 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11368 11369/* ------------------------------ */ 11370 .balign 128 11371.L_ALT_op_iget_byte_quick: /* 0xf0 */ 11372/* File: arm64/alt_stub.S */ 11373/* 11374 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11375 * any interesting requests and then jump to the real instruction 11376 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11377 */ 11378 .extern MterpCheckBefore 11379 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11380 adr lr, artMterpAsmInstructionStart + (240 * 128) // Addr of primary handler. 11381 mov x0, xSELF 11382 add x1, xFP, #OFF_FP_SHADOWFRAME 11383 mov x2, xPC 11384 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11385 11386/* ------------------------------ */ 11387 .balign 128 11388.L_ALT_op_iget_char_quick: /* 0xf1 */ 11389/* File: arm64/alt_stub.S */ 11390/* 11391 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11392 * any interesting requests and then jump to the real instruction 11393 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11394 */ 11395 .extern MterpCheckBefore 11396 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11397 adr lr, artMterpAsmInstructionStart + (241 * 128) // Addr of primary handler. 11398 mov x0, xSELF 11399 add x1, xFP, #OFF_FP_SHADOWFRAME 11400 mov x2, xPC 11401 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11402 11403/* ------------------------------ */ 11404 .balign 128 11405.L_ALT_op_iget_short_quick: /* 0xf2 */ 11406/* File: arm64/alt_stub.S */ 11407/* 11408 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11409 * any interesting requests and then jump to the real instruction 11410 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11411 */ 11412 .extern MterpCheckBefore 11413 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11414 adr lr, artMterpAsmInstructionStart + (242 * 128) // Addr of primary handler. 11415 mov x0, xSELF 11416 add x1, xFP, #OFF_FP_SHADOWFRAME 11417 mov x2, xPC 11418 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11419 11420/* ------------------------------ */ 11421 .balign 128 11422.L_ALT_op_unused_f3: /* 0xf3 */ 11423/* File: arm64/alt_stub.S */ 11424/* 11425 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11426 * any interesting requests and then jump to the real instruction 11427 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11428 */ 11429 .extern MterpCheckBefore 11430 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11431 adr lr, artMterpAsmInstructionStart + (243 * 128) // Addr of primary handler. 11432 mov x0, xSELF 11433 add x1, xFP, #OFF_FP_SHADOWFRAME 11434 mov x2, xPC 11435 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11436 11437/* ------------------------------ */ 11438 .balign 128 11439.L_ALT_op_unused_f4: /* 0xf4 */ 11440/* File: arm64/alt_stub.S */ 11441/* 11442 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11443 * any interesting requests and then jump to the real instruction 11444 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11445 */ 11446 .extern MterpCheckBefore 11447 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11448 adr lr, artMterpAsmInstructionStart + (244 * 128) // Addr of primary handler. 11449 mov x0, xSELF 11450 add x1, xFP, #OFF_FP_SHADOWFRAME 11451 mov x2, xPC 11452 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11453 11454/* ------------------------------ */ 11455 .balign 128 11456.L_ALT_op_unused_f5: /* 0xf5 */ 11457/* File: arm64/alt_stub.S */ 11458/* 11459 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11460 * any interesting requests and then jump to the real instruction 11461 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11462 */ 11463 .extern MterpCheckBefore 11464 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11465 adr lr, artMterpAsmInstructionStart + (245 * 128) // Addr of primary handler. 11466 mov x0, xSELF 11467 add x1, xFP, #OFF_FP_SHADOWFRAME 11468 mov x2, xPC 11469 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11470 11471/* ------------------------------ */ 11472 .balign 128 11473.L_ALT_op_unused_f6: /* 0xf6 */ 11474/* File: arm64/alt_stub.S */ 11475/* 11476 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11477 * any interesting requests and then jump to the real instruction 11478 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11479 */ 11480 .extern MterpCheckBefore 11481 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11482 adr lr, artMterpAsmInstructionStart + (246 * 128) // Addr of primary handler. 11483 mov x0, xSELF 11484 add x1, xFP, #OFF_FP_SHADOWFRAME 11485 mov x2, xPC 11486 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11487 11488/* ------------------------------ */ 11489 .balign 128 11490.L_ALT_op_unused_f7: /* 0xf7 */ 11491/* File: arm64/alt_stub.S */ 11492/* 11493 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11494 * any interesting requests and then jump to the real instruction 11495 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11496 */ 11497 .extern MterpCheckBefore 11498 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11499 adr lr, artMterpAsmInstructionStart + (247 * 128) // Addr of primary handler. 11500 mov x0, xSELF 11501 add x1, xFP, #OFF_FP_SHADOWFRAME 11502 mov x2, xPC 11503 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11504 11505/* ------------------------------ */ 11506 .balign 128 11507.L_ALT_op_unused_f8: /* 0xf8 */ 11508/* File: arm64/alt_stub.S */ 11509/* 11510 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11511 * any interesting requests and then jump to the real instruction 11512 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11513 */ 11514 .extern MterpCheckBefore 11515 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11516 adr lr, artMterpAsmInstructionStart + (248 * 128) // Addr of primary handler. 11517 mov x0, xSELF 11518 add x1, xFP, #OFF_FP_SHADOWFRAME 11519 mov x2, xPC 11520 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11521 11522/* ------------------------------ */ 11523 .balign 128 11524.L_ALT_op_unused_f9: /* 0xf9 */ 11525/* File: arm64/alt_stub.S */ 11526/* 11527 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11528 * any interesting requests and then jump to the real instruction 11529 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11530 */ 11531 .extern MterpCheckBefore 11532 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11533 adr lr, artMterpAsmInstructionStart + (249 * 128) // Addr of primary handler. 11534 mov x0, xSELF 11535 add x1, xFP, #OFF_FP_SHADOWFRAME 11536 mov x2, xPC 11537 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11538 11539/* ------------------------------ */ 11540 .balign 128 11541.L_ALT_op_invoke_polymorphic: /* 0xfa */ 11542/* File: arm64/alt_stub.S */ 11543/* 11544 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11545 * any interesting requests and then jump to the real instruction 11546 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11547 */ 11548 .extern MterpCheckBefore 11549 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11550 adr lr, artMterpAsmInstructionStart + (250 * 128) // Addr of primary handler. 11551 mov x0, xSELF 11552 add x1, xFP, #OFF_FP_SHADOWFRAME 11553 mov x2, xPC 11554 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11555 11556/* ------------------------------ */ 11557 .balign 128 11558.L_ALT_op_invoke_polymorphic_range: /* 0xfb */ 11559/* File: arm64/alt_stub.S */ 11560/* 11561 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11562 * any interesting requests and then jump to the real instruction 11563 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11564 */ 11565 .extern MterpCheckBefore 11566 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11567 adr lr, artMterpAsmInstructionStart + (251 * 128) // Addr of primary handler. 11568 mov x0, xSELF 11569 add x1, xFP, #OFF_FP_SHADOWFRAME 11570 mov x2, xPC 11571 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11572 11573/* ------------------------------ */ 11574 .balign 128 11575.L_ALT_op_invoke_custom: /* 0xfc */ 11576/* File: arm64/alt_stub.S */ 11577/* 11578 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11579 * any interesting requests and then jump to the real instruction 11580 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11581 */ 11582 .extern MterpCheckBefore 11583 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11584 adr lr, artMterpAsmInstructionStart + (252 * 128) // Addr of primary handler. 11585 mov x0, xSELF 11586 add x1, xFP, #OFF_FP_SHADOWFRAME 11587 mov x2, xPC 11588 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11589 11590/* ------------------------------ */ 11591 .balign 128 11592.L_ALT_op_invoke_custom_range: /* 0xfd */ 11593/* File: arm64/alt_stub.S */ 11594/* 11595 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11596 * any interesting requests and then jump to the real instruction 11597 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11598 */ 11599 .extern MterpCheckBefore 11600 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11601 adr lr, artMterpAsmInstructionStart + (253 * 128) // Addr of primary handler. 11602 mov x0, xSELF 11603 add x1, xFP, #OFF_FP_SHADOWFRAME 11604 mov x2, xPC 11605 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11606 11607/* ------------------------------ */ 11608 .balign 128 11609.L_ALT_op_unused_fe: /* 0xfe */ 11610/* File: arm64/alt_stub.S */ 11611/* 11612 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11613 * any interesting requests and then jump to the real instruction 11614 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11615 */ 11616 .extern MterpCheckBefore 11617 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11618 adr lr, artMterpAsmInstructionStart + (254 * 128) // Addr of primary handler. 11619 mov x0, xSELF 11620 add x1, xFP, #OFF_FP_SHADOWFRAME 11621 mov x2, xPC 11622 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11623 11624/* ------------------------------ */ 11625 .balign 128 11626.L_ALT_op_unused_ff: /* 0xff */ 11627/* File: arm64/alt_stub.S */ 11628/* 11629 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11630 * any interesting requests and then jump to the real instruction 11631 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11632 */ 11633 .extern MterpCheckBefore 11634 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11635 adr lr, artMterpAsmInstructionStart + (255 * 128) // Addr of primary handler. 11636 mov x0, xSELF 11637 add x1, xFP, #OFF_FP_SHADOWFRAME 11638 mov x2, xPC 11639 b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. 11640 11641 .balign 128 11642 .size artMterpAsmAltInstructionStart, .-artMterpAsmAltInstructionStart 11643 .global artMterpAsmAltInstructionEnd 11644artMterpAsmAltInstructionEnd: 11645