1 /* Copyright (c) 2012, 2014, The Linux Foundation. All rights reserved.
2  *
3  * Redistribution and use in source and binary forms, with or without
4  * modification, are permitted provided that the following conditions are
5  * met:
6  *     * Redistributions of source code must retain the above copyright
7  *       notice, this list of conditions and the following disclaimer.
8  *     * Redistributions in binary form must reproduce the above
9  *       copyright notice, this list of conditions and the following
10  *       disclaimer in the documentation and/or other materials provided
11  *       with the distribution.
12  *     * Neither the name of The Linux Foundation nor the names of its
13  *       contributors may be used to endorse or promote products derived
14  *       from this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  *
28  */
29 
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33 
34 #define FAILED                  -1
35 #define SUCCESS                 0
36 #define INDEFINITE_DURATION     0
37 
38 enum SCREEN_DISPLAY_TYPE {
39     DISPLAY_OFF = 0x00FF,
40 };
41 
42 enum PWR_CLSP_TYPE {
43     ALL_CPUS_PWR_CLPS_DIS = 0x101,
44 };
45 
46 /* For CPUx min freq, the leftmost byte
47  * represents the CPU and the
48  * rightmost byte represents the frequency
49  * All intermediate frequencies on the
50  * device are supported. The hex value
51  * passed into PerfLock will be multiplied
52  * by 10^5. This frequency or the next
53  * highest frequency available will be set
54  *
55  * For example, if 1.4 Ghz is required on
56  * CPU0, use 0x20E
57  *
58  * If the highest available frequency
59  * on the device is required, use
60  * CPUx_MIN_FREQ_TURBO_MAX
61  * where x represents the CPU
62  */
63 enum CPU0_MIN_FREQ_LVL {
64     CPU0_MIN_FREQ_NONTURBO_MAX = 0x20A,
65     CPU0_MIN_FREQ_TURBO_MAX = 0x2FE,
66 };
67 
68 enum CPU1_MIN_FREQ_LVL {
69     CPU1_MIN_FREQ_NONTURBO_MAX = 0x30A,
70     CPU1_MIN_FREQ_TURBO_MAX = 0x3FE,
71 };
72 
73 enum CPU2_MIN_FREQ_LVL {
74     CPU2_MIN_FREQ_NONTURBO_MAX = 0x40A,
75     CPU2_MIN_FREQ_TURBO_MAX = 0x4FE,
76 };
77 
78 enum CPU3_MIN_FREQ_LVL {
79     CPU3_MIN_FREQ_NONTURBO_MAX = 0x50A,
80     CPU3_MIN_FREQ_TURBO_MAX = 0x5FE,
81 };
82 
83 enum CPU0_MAX_FREQ_LVL {
84     CPU0_MAX_FREQ_NONTURBO_MAX = 0x150A,
85 };
86 
87 enum CPU1_MAX_FREQ_LVL {
88     CPU1_MAX_FREQ_NONTURBO_MAX = 0x160A,
89 };
90 
91 enum CPU2_MAX_FREQ_LVL {
92     CPU2_MAX_FREQ_NONTURBO_MAX = 0x170A,
93 };
94 
95 enum CPU3_MAX_FREQ_LVL {
96     CPU3_MAX_FREQ_NONTURBO_MAX = 0x180A,
97 };
98 
99 enum MIN_CPUS_ONLINE_LVL {
100     CPUS_ONLINE_MIN_2 = 0x702,
101     CPUS_ONLINE_MIN_3 = 0x703,
102     CPUS_ONLINE_MIN_4 = 0x704,
103     CPUS_ONLINE_MPD_OVERRIDE = 0x777,
104     CPUS_ONLINE_MAX = 0x7FF,
105 };
106 
107 enum MAX_CPUS_ONLINE_LVL {
108     CPUS_ONLINE_MAX_LIMIT_1 = 0x8FE,
109     CPUS_ONLINE_MAX_LIMIT_2 = 0x8FD,
110     CPUS_ONLINE_MAX_LIMIT_3 = 0x8FC,
111     CPUS_ONLINE_MAX_LIMIT_4 = 0x8FB,
112     CPUS_ONLINE_MAX_LIMIT_MAX = 0x8FB,
113 };
114 
115 enum SAMPLING_RATE_LVL {
116     MS_500 = 0xBCD,
117     MS_50 = 0xBFA,
118     MS_20 = 0xBFD,
119 };
120 
121 enum ONDEMAND_IO_BUSY_LVL {
122     IO_BUSY_OFF = 0xC00,
123     IO_BUSY_ON = 0xC01,
124 };
125 
126 enum ONDEMAND_SAMPLING_DOWN_FACTOR_LVL {
127     SAMPLING_DOWN_FACTOR_1 = 0xD01,
128     SAMPLING_DOWN_FACTOR_4 = 0xD04,
129 };
130 
131 enum INTERACTIVE_TIMER_RATE_LVL {
132     TR_MS_500 = 0xECD,
133     TR_MS_100 = 0xEF5,
134     TR_MS_50 = 0xEFA,
135     TR_MS_30 = 0xEFC,
136     TR_MS_20 = 0xEFD,
137 };
138 
139 /* This timer rate applicable to cpu0
140     across 8939/8952 series chipset */
141 enum INTERACTIVE_TIMER_RATE_LVL_CPU0_8939 {
142     TR_MS_CPU0_500 = 0x30CD,
143     TR_MS_CPU0_100 = 0x30F5,
144     TR_MS_CPU0_50 = 0x30FA,
145     TR_MS_CPU0_30 = 0x30FC,
146     TR_MS_CPU0_20 = 0x30FD,
147 };
148 
149 /* This timer rate applicable to cpu4
150     across 8939/8952 series chipset */
151 enum INTERACTIVE_TIMER_RATE_LVL_CPU4_8939 {
152     TR_MS_CPU4_500 = 0x3BCD,
153     TR_MS_CPU4_100 = 0x3BF5,
154     TR_MS_CPU4_50 = 0x3BFA,
155     TR_MS_CPU4_30 = 0x3BFC,
156     TR_MS_CPU4_20 = 0x3BFD,
157 };
158 
159 enum INTERACTIVE_HISPEED_FREQ_LVL {
160     HS_FREQ_1026 = 0xF0A,
161 };
162 
163 enum INTERACTIVE_HISPEED_LOAD_LVL {
164     HISPEED_LOAD_90 = 0x105A,
165 };
166 
167 enum SYNC_FREQ_LVL {
168     SYNC_FREQ_300 = 0x1103,
169     SYNC_FREQ_600 = 0X1106,
170     SYNC_FREQ_384 = 0x1103,
171     SYNC_FREQ_NONTURBO_MAX = 0x110A,
172     SYNC_FREQ_TURBO = 0x110F,
173 };
174 
175 enum OPTIMAL_FREQ_LVL {
176     OPTIMAL_FREQ_300 = 0x1203,
177     OPTIMAL_FREQ_600 = 0x1206,
178     OPTIMAL_FREQ_384 = 0x1203,
179     OPTIMAL_FREQ_NONTURBO_MAX = 0x120A,
180     OPTIMAL_FREQ_TURBO = 0x120F,
181 };
182 
183 enum SCREEN_PWR_CLPS_LVL {
184     PWR_CLPS_DIS = 0x1300,
185     PWR_CLPS_ENA = 0x1301,
186 };
187 
188 enum THREAD_MIGRATION_LVL {
189     THREAD_MIGRATION_SYNC_OFF = 0x1400,
190 };
191 
192 enum SCHED_GUIDED_LVL {
193     INTERACTIVE_USE_SCHED_LOAD_OFF = 0x5201,
194     INTERACTIVE_USE_MIGRATION_NOTIF_OFF = 0x5301
195 };
196 
197 enum INTERACTIVE_IO_BUSY_LVL {
198     INTERACTIVE_IO_BUSY_OFF = 0x1B00,
199     INTERACTIVE_IO_BUSY_ON = 0x1B01,
200 };
201 
202 enum SCHED_BOOST_LVL {
203     SCHED_BOOST_ON = 0x1E01,
204 };
205 
206 enum CPU4_MIN_FREQ_LVL {
207     CPU4_MIN_FREQ_NONTURBO_MAX = 0x1F0A,
208     CPU4_MIN_FREQ_TURBO_MAX = 0x1FFE,
209 };
210 
211 enum CPU5_MIN_FREQ_LVL {
212     CPU5_MIN_FREQ_NONTURBO_MAX = 0x200A,
213     CPU5_MIN_FREQ_TURBO_MAX = 0x20FE,
214 };
215 
216 enum CPU6_MIN_FREQ_LVL {
217     CPU6_MIN_FREQ_NONTURBO_MAX = 0x210A,
218     CPU6_MIN_FREQ_TURBO_MAX = 0x21FE,
219 };
220 
221 enum CPU7_MIN_FREQ_LVL {
222     CPU7_MIN_FREQ_NONTURBO_MAX = 0x220A,
223     CPU7_MIN_FREQ_TURBO_MAX = 0x22FE,
224 };
225 
226 enum CPU4_MAX_FREQ_LVL {
227     CPU4_MAX_FREQ_NONTURBO_MAX = 0x230A,
228 };
229 
230 enum CPU5_MAX_FREQ_LVL {
231     CPU5_MAX_FREQ_NONTURBO_MAX = 0x240A,
232 };
233 
234 enum CPU6_MAX_FREQ_LVL {
235     CPU6_MAX_FREQ_NONTURBO_MAX = 0x250A,
236 };
237 
238 enum CPU7_MAX_FREQ_LVL {
239     CPU7_MAX_FREQ_NONTURBO_MAX = 0x260A,
240 };
241 
242 #ifdef __cplusplus
243 }
244 #endif
245