1 /** @file 2 3 Copyright (c) 2015, Linaro Limited. All rights reserved. 4 Copyright (c) 2015, Hisilicon Limited. All rights reserved. 5 6 This program and the accompanying materials 7 are licensed and made available under the terms and conditions of the BSD License 8 which accompanies this distribution. The full text of the license may be found at 9 http://opensource.org/licenses/bsd-license.php 10 11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 14 **/ 15 16 #ifndef __DW_USB_DXE_H__ 17 #define __DW_USB_DXE_H__ 18 19 #define DW_USB_BASE FixedPcdGet32 (PcdDwUsbDxeBaseAddress) 20 21 #define READ_REG32(Offset) MmioRead32 (DW_USB_BASE + Offset) 22 #define READ_REG16(Offset) (UINT16)READ_REG32 (Offset) 23 #define WRITE_REG32(Offset, Val) MmioWrite32 (DW_USB_BASE + Offset, Val) 24 #define WRITE_REG16(Offset, Val) MmioWrite32 (DW_USB_BASE + Offset, (UINT32) Val) 25 #define WRITE_REG8(Offset, Val) MmioWrite32 (DW_USB_BASE + Offset, (UINT32) Val) 26 27 // Max packet size in bytes (For Full Speed USB 64 is the only valid value) 28 #define MAX_PACKET_SIZE_CONTROL 64 29 30 #define MAX_PACKET_SIZE_BULK 512 31 32 // 8 Endpoints, in and out. Don't count the Endpoint 0 setup buffer 33 #define DW_NUM_ENDPOINTS 16 34 35 // Endpoint Indexes 36 #define DW_EP0SETUP 0x20 37 #define DW_EP0RX 0x00 38 #define DW_EP0TX 0x01 39 #define DW_EP1RX 0x02 40 #define DW_EP1TX 0x03 41 42 // DcInterrupt bits 43 #define DW_DC_INTERRUPT_BRESET BIT0 44 #define DW_DC_INTERRUPT_SOF BIT1 45 #define DW_DC_INTERRUPT_PSOF BIT2 46 #define DW_DC_INTERRUPT_SUSP BIT3 47 #define DW_DC_INTERRUPT_RESUME BIT4 48 #define DW_DC_INTERRUPT_HS_STAT BIT5 49 #define DW_DC_INTERRUPT_DMA BIT6 50 #define DW_DC_INTERRUPT_VBUS BIT7 51 #define DW_DC_INTERRUPT_EP0SETUP BIT8 52 #define DW_DC_INTERRUPT_EP0RX BIT10 53 #define DW_DC_INTERRUPT_EP0TX BIT11 54 #define DW_DC_INTERRUPT_EP1RX BIT12 55 #define DW_DC_INTERRUPT_EP1TX BIT13 56 // All valid peripheral controller interrupts 57 #define DW_DC_INTERRUPT_MASK 0x003FFFDFF 58 59 #define DW_ADDRESS 0x200 60 #define DW_ADDRESS_DEVEN BIT7 61 62 #define DW_MODE 0x20C 63 #define DW_MODE_DATA_BUS_WIDTH BIT8 64 #define DW_MODE_CLKAON BIT7 65 #define DW_MODE_SFRESET BIT4 66 #define DW_MODE_WKUPCS BIT2 67 68 #define DW_ENDPOINT_MAX_PACKET_SIZE 0x204 69 70 #define DW_ENDPOINT_TYPE 0x208 71 #define DW_ENDPOINT_TYPE_NOEMPKT BIT4 72 #define DW_ENDPOINT_TYPE_ENABLE BIT3 73 74 #define DW_INTERRUPT_CONFIG 0x210 75 // Interrupt config value to only interrupt on ACK of IN and OUT tokens 76 #define DW_INTERRUPT_CONFIG_ACK_ONLY BIT2 | BIT5 | BIT6 77 78 #define DW_DC_INTERRUPT 0x218 79 #define DW_DC_INTERRUPT_ENABLE 0x214 80 81 #define DW_CTRL_FUNCTION 0x228 82 #define DW_CTRL_FUNCTION_VENDP BIT3 83 #define DW_CTRL_FUNCTION_DSEN BIT2 84 #define DW_CTRL_FUNCTION_STATUS BIT1 85 86 #define DW_DEVICE_UNLOCK 0x27C 87 #define DW_DEVICE_UNLOCK_MAGIC 0xAA37 88 89 #define DW_SW_RESET_REG 0x30C 90 #define DW_SW_RESET_ALL BIT0 91 92 #define DW_DEVICE_ID 0x370 93 94 #define DW_OTG_CTRL_SET 0x374 95 #define DW_OTG_CTRL_CLR OTG_CTRL_SET + 2 96 #define DW_OTG_CTRL_OTG_DISABLE BIT10 97 #define DW_OTG_CTRL_VBUS_CHRG BIT6 98 #define DW_OTG_CTRL_VBUS_DISCHRG BIT5 99 #define DW_OTG_CTRL_DM_PULLDOWN BIT2 100 #define DW_OTG_CTRL_DP_PULLDOWN BIT1 101 #define DW_OTG_CTRL_DP_PULLUP BIT0 102 103 #define DW_OTG_STATUS 0x378 104 #define DW_OTG_STATUS_B_SESS_END BIT7 105 #define DW_OTG_STATUS_A_B_SESS_VLD BIT1 106 107 #define DW_OTG_INTERRUPT_LATCH_SET 0x37C 108 #define DW_OTG_INTERRUPT_LATCH_CLR 0x37E 109 #define DW_OTG_INTERRUPT_ENABLE_RISE 0x384 110 111 #define DW_DMA_ENDPOINT_INDEX 0x258 112 113 #define DW_ENDPOINT_INDEX 0x22c 114 #define DW_DATA_PORT 0x220 115 #define DW_BUFFER_LENGTH 0x21c 116 117 // Device ID Values 118 #define PHILLIPS_VENDOR_ID_VAL 0x04cc 119 #define DW_PRODUCT_ID_VAL 0x1761 120 #define DW_DEVICE_ID_VAL ((ISP1761_PRODUCT_ID_VAL << 16) |\ 121 PHILLIPS_VENDOR_ID_VAL) 122 123 #define DWC_OTG_BASE DW_USB_BASE 124 125 #define USB_NUM_ENDPOINTS 2 126 #define MAX_EPS_CHANNELS 16 127 128 #define BULK_OUT_EP 1 129 #define BULK_IN_EP 1 130 131 #define RX_REQ_LEN 512 132 #define MAX_PACKET_LEN 512 133 134 #define DATA_FIFO_CONFIG 0x0F801000 135 /* RX FIFO: 2048 bytes */ 136 #define RX_SIZE 0x00000200 137 /* Non-periodic TX FIFO: 128 bytes. start address: 0x200 * 4. */ 138 #define ENDPOINT_TX_SIZE 0x01000200 139 140 /* EP1 TX FIFO: 1024 bytes. start address: 0x220 * 4. */ 141 /* EP2 TX FIFO: 1024 bytes. start address: 0x320 * 4. */ 142 /* EP3 TX FIFO: 1024 bytes. start address: 0x420 * 4. */ 143 /* EP4 TX FIFO: 1024 bytes. start address: 0x520 * 4. */ 144 /* EP5 TX FIFO: 128 bytes. start address: 0x620 * 4. */ 145 /* EP6 TX FIFO: 128 bytes. start address: 0x640 * 4. */ 146 /* EP7 TX FIFO: 128 bytes. start address: 0x660 * 4. */ 147 /* EP8 TX FIFO: 128 bytes. start address: 0x680 * 4. */ 148 /* EP9 TX FIFO: 128 bytes. start address: 0x6A0 * 4. */ 149 /* EP10 TX FIFO: 128 bytes. start address: 0x6C0 * 4. */ 150 /* EP11 TX FIFO: 128 bytes. start address: 0x6E0 * 4. */ 151 /* EP12 TX FIFO: 128 bytes. start address: 0x700 * 4. */ 152 /* EP13 TX FIFO: 128 bytes. start address: 0x720 * 4. */ 153 /* EP14 TX FIFO: 128 bytes. start address: 0x740 * 4. */ 154 /* EP15 TX FIFO: 128 bytes. start address: 0x760 * 4. */ 155 156 #define DATA_IN_ENDPOINT_TX_FIFO1 0x01000220 157 #define DATA_IN_ENDPOINT_TX_FIFO2 0x01000320 158 #define DATA_IN_ENDPOINT_TX_FIFO3 0x01000420 159 #define DATA_IN_ENDPOINT_TX_FIFO4 0x01000520 160 #define DATA_IN_ENDPOINT_TX_FIFO5 0x00200620 161 #define DATA_IN_ENDPOINT_TX_FIFO6 0x00200640 162 #define DATA_IN_ENDPOINT_TX_FIFO7 0x00200680 163 #define DATA_IN_ENDPOINT_TX_FIFO8 0x002006A0 164 #define DATA_IN_ENDPOINT_TX_FIFO9 0x002006C0 165 #define DATA_IN_ENDPOINT_TX_FIFO10 0x002006E0 166 #define DATA_IN_ENDPOINT_TX_FIFO11 0x00200700 167 #define DATA_IN_ENDPOINT_TX_FIFO12 0x00200720 168 #define DATA_IN_ENDPOINT_TX_FIFO13 0x00200740 169 #define DATA_IN_ENDPOINT_TX_FIFO14 0x00200760 170 #define DATA_IN_ENDPOINT_TX_FIFO15 0x00200F00 171 172 /*DWC_OTG regsiter descriptor*/ 173 /*Device mode CSR MAP*/ 174 #define DEVICE_CSR_BASE (0x800) 175 /*Device mode CSR MAP*/ 176 #define DEVICE_INEP_BASE (0x900) 177 /*Device mode CSR MAP*/ 178 #define DEVICE_OUTEP_BASE (0xB00) 179 180 /*** OTG LINK CORE REGISTERS ***/ 181 /* Core Global Registers */ 182 #define GOTGCTL (0x000) 183 #define GOTGINT (0x004) 184 #define GAHBCFG (0x008) 185 #define GAHBCFG_P_TXF_EMP_LVL (1 << 8) 186 #define GAHBCFG_NP_TXF_EMP_LVL (1 << 7) 187 #define GAHBCFG_DMA_EN (1 << 5) 188 #define GAHBCFG_GLBL_INTR_EN (1 << 0) 189 #define GAHBCFG_CTRL_MASK (GAHBCFG_P_TXF_EMP_LVL | \ 190 GAHBCFG_NP_TXF_EMP_LVL | \ 191 GAHBCFG_DMA_EN | \ 192 GAHBCFG_GLBL_INTR_EN) 193 194 #define GUSBCFG (0x00C) 195 #define GRSTCTL (0x010) 196 #define GRSTCTL_AHBIDLE (1 << 31) 197 #define GRSTCTL_CSFTRST (1 << 0) 198 199 #define GINTSTS (0x014) 200 #define GINTSTS_WKUPINT (1 << 31) 201 #define GINTSTS_SESSREGINT (1 << 30) 202 #define GINTSTS_DISCONNINT (1 << 29) 203 #define GINTSTS_CONIDSTSCHNG (1 << 28) 204 #define GINTSTS_LPMTRANRCVD (1 << 27) 205 #define GINTSTS_PTXFEMP (1 << 26) 206 #define GINTSTS_HCHINT (1 << 25) 207 #define GINTSTS_PRTINT (1 << 24) 208 #define GINTSTS_RESETDET (1 << 23) 209 #define GINTSTS_FET_SUSP (1 << 22) 210 #define GINTSTS_INCOMPL_IP (1 << 21) 211 #define GINTSTS_INCOMPL_SOIN (1 << 20) 212 #define GINTSTS_OEPINT (1 << 19) 213 #define GINTSTS_IEPINT (1 << 18) 214 #define GINTSTS_EPMIS (1 << 17) 215 #define GINTSTS_RESTOREDONE (1 << 16) 216 #define GINTSTS_EOPF (1 << 15) 217 #define GINTSTS_ISOUTDROP (1 << 14) 218 #define GINTSTS_ENUMDONE (1 << 13) 219 #define GINTSTS_USBRST (1 << 12) 220 #define GINTSTS_USBSUSP (1 << 11) 221 #define GINTSTS_ERLYSUSP (1 << 10) 222 #define GINTSTS_I2CINT (1 << 9) 223 #define GINTSTS_ULPI_CK_INT (1 << 8) 224 #define GINTSTS_GOUTNAKEFF (1 << 7) 225 #define GINTSTS_GINNAKEFF (1 << 6) 226 #define GINTSTS_NPTXFEMP (1 << 5) 227 #define GINTSTS_RXFLVL (1 << 4) 228 #define GINTSTS_SOF (1 << 3) 229 #define GINTSTS_OTGINT (1 << 2) 230 #define GINTSTS_MODEMIS (1 << 1) 231 #define GINTSTS_CURMODE_HOST (1 << 0) 232 233 #define GINTMSK (0x018) 234 #define GRXSTSR (0x01C) 235 #define GRXSTSP (0x020) 236 #define GRXFSIZ (0x024) 237 #define GNPTXFSIZ (0x028) 238 #define GNPTXSTS (0x02C) 239 240 #define GHWCFG1 (0x044) 241 #define GHWCFG2 (0x048) 242 #define GHWCFG3 (0x04c) 243 #define GHWCFG4 (0x050) 244 #define GLPMCFG (0x054) 245 246 #define GDFIFOCFG (0x05c) 247 248 #define HPTXFSIZ (0x100) 249 #define DIEPTXF(x) (0x100 + 4 * (x)) 250 #define DIEPTXF1 (0x104) 251 #define DIEPTXF2 (0x108) 252 #define DIEPTXF3 (0x10C) 253 #define DIEPTXF4 (0x110) 254 #define DIEPTXF5 (0x114) 255 #define DIEPTXF6 (0x118) 256 #define DIEPTXF7 (0x11C) 257 #define DIEPTXF8 (0x120) 258 #define DIEPTXF9 (0x124) 259 #define DIEPTXF10 (0x128) 260 #define DIEPTXF11 (0x12C) 261 #define DIEPTXF12 (0x130) 262 #define DIEPTXF13 (0x134) 263 #define DIEPTXF14 (0x138) 264 #define DIEPTXF15 (0x13C) 265 266 /*** HOST MODE REGISTERS ***/ 267 /* Host Global Registers */ 268 #define HCFG (0x400) 269 #define HFIR (0x404) 270 #define HFNUM (0x408) 271 #define HPTXSTS (0x410) 272 #define HAINT (0x414) 273 #define HAINTMSK (0x418) 274 275 /* Host Port Control and Status Registers */ 276 #define HPRT (0x440) 277 278 /* Host Channel-Specific Registers */ 279 #define HCCHAR(x) (0x500 + 0x20 * (x)) 280 #define HCSPLT(x) (0x504 + 0x20 * (x)) 281 #define HCINT(x) (0x508 + 0x20 * (x)) 282 #define HCINTMSK(x) (0x50C + 0x20 * (x)) 283 #define HCTSIZ(x) (0x510 + 0x20 * (x)) 284 #define HCDMA(x) (0x514 + 0x20 * (x)) 285 #define HCCHAR0 (0x500) 286 #define HCSPLT0 (0x504) 287 #define HCINT0 (0x508) 288 #define HCINTMSK0 (0x50C) 289 #define HCTSIZ0 (0x510) 290 #define HCDMA0 (0x514) 291 #define HCCHAR1 (0x520) 292 #define HCSPLT1 (0x524) 293 #define HCINT1 (0x528) 294 #define HCINTMSK1 (0x52C) 295 #define HCTSIZ1 (0x530) 296 #define HCDMA1 (0x534) 297 #define HCCHAR2 (0x540) 298 #define HCSPLT2 (0x544) 299 #define HCINT2 (0x548) 300 #define HCINTMSK2 (0x54C) 301 #define HCTSIZ2 (0x550) 302 #define HCDMA2 (0x554) 303 #define HCCHAR3 (0x560) 304 #define HCSPLT3 (0x564) 305 #define HCINT3 (0x568) 306 #define HCINTMSK3 (0x56C) 307 #define HCTSIZ3 (0x570) 308 #define HCDMA3 (0x574) 309 #define HCCHAR4 (0x580) 310 #define HCSPLT4 (0x584) 311 #define HCINT4 (0x588) 312 #define HCINTMSK4 (0x58C) 313 #define HCTSIZ4 (0x590) 314 #define HCDMA4 (0x594) 315 #define HCCHAR5 (0x5A0) 316 #define HCSPLT5 (0x5A4) 317 #define HCINT5 (0x5A8) 318 #define HCINTMSK5 (0x5AC) 319 #define HCTSIZ5 (0x5B0) 320 #define HCDMA5 (0x5B4) 321 #define HCCHAR6 (0x5C0) 322 #define HCSPLT6 (0x5C4) 323 #define HCINT6 (0x5C8) 324 #define HCINTMSK6 (0x5CC) 325 #define HCTSIZ6 (0x5D0) 326 #define HCDMA6 (0x5D4) 327 #define HCCHAR7 (0x5E0) 328 #define HCSPLT7 (0x5E4) 329 #define HCINT7 (0x5E8) 330 #define HCINTMSK7 (0x5EC) 331 #define HCTSIZ7 (0x5F0) 332 #define HCDMA7 (0x5F4) 333 #define HCCHAR8 (0x600) 334 #define HCSPLT8 (0x604) 335 #define HCINT8 (0x608) 336 #define HCINTMSK8 (0x60C) 337 #define HCTSIZ8 (0x610) 338 #define HCDMA8 (0x614) 339 #define HCCHAR9 (0x620) 340 #define HCSPLT9 (0x624) 341 #define HCINT9 (0x628) 342 #define HCINTMSK9 (0x62C) 343 #define HCTSIZ9 (0x630) 344 #define HCDMA9 (0x634) 345 #define HCCHAR10 (0x640) 346 #define HCSPLT10 (0x644) 347 #define HCINT10 (0x648) 348 #define HCINTMSK10 (0x64C) 349 #define HCTSIZ10 (0x650) 350 #define HCDMA10 (0x654) 351 #define HCCHAR11 (0x660) 352 #define HCSPLT11 (0x664) 353 #define HCINT11 (0x668) 354 #define HCINTMSK11 (0x66C) 355 #define HCTSIZ11 (0x670) 356 #define HCDMA11 (0x674) 357 #define HCCHAR12 (0x680) 358 #define HCSPLT12 (0x684) 359 #define HCINT12 (0x688) 360 #define HCINTMSK12 (0x68C) 361 #define HCTSIZ12 (0x690) 362 #define HCDMA12 (0x694) 363 #define HCCHAR13 (0x6A0) 364 #define HCSPLT13 (0x6A4) 365 #define HCINT13 (0x6A8) 366 #define HCINTMSK13 (0x6AC) 367 #define HCTSIZ13 (0x6B0) 368 #define HCDMA13 (0x6B4) 369 #define HCCHAR14 (0x6C0) 370 #define HCSPLT14 (0x6C4) 371 #define HCINT14 (0x6C8) 372 #define HCINTMSK14 (0x6CC) 373 #define HCTSIZ14 (0x6D0) 374 #define HCDMA14 (0x6D4) 375 #define HCCHAR15 (0x6E0) 376 #define HCSPLT15 (0x6E4) 377 #define HCINT15 (0x6E8) 378 #define HCINTMSK15 (0x6EC) 379 #define HCTSIZ15 (0x6F0) 380 #define HCDMA15 (0x6F4) 381 382 /*** DEVICE MODE REGISTERS ***/ 383 /* Device Global Registers */ 384 #define DCFG (0x800) 385 #define DCFG_EPMISCNT_MASK (0x1F << 18) 386 #define DCFG_EPMISCNT_SHIFT (18) 387 #define DCFG_NZ_STS_OUT_HSHK (1 << 2) 388 389 #define DCTL (0x804) 390 #define DSTS (0x808) 391 #define DIEPMSK (0x810) 392 #define DOEPMSK (0x814) 393 #define DAINT (0x818) 394 #define DAINTMSK (0x81C) 395 #define DTKNQR1 (0x820) 396 #define DTKNQR2 (0x824) 397 #define DVBUSDIS (0x828) 398 #define DVBUSPULSE (0x82C) 399 #define DTHRCTL (0x830) 400 401 /* Device Logical IN Endpoint-Specific Registers */ 402 #define DIEPCTL(x) (0x900 + 0x20 * (x)) 403 #define DIEPINT(x) (0x908 + 0x20 * (x)) 404 #define DIEPTSIZ(x) (0x910 + 0x20 * (x)) 405 #define DIEPDMA(x) (0x914 + 0x20 * (x)) 406 #define DTXFSTS(x) (0x918 + 0x20 * (x)) 407 408 #define DIEPCTL0 (0x900) 409 #define DIEPINT0 (0x908) 410 #define DIEPTSIZ0 (0x910) 411 #define DIEPDMA0 (0x914) 412 #define DIEPCTL1 (0x920) 413 #define DIEPINT1 (0x928) 414 #define DIEPTSIZ1 (0x930) 415 #define DIEPDMA1 (0x934) 416 #define DIEPCTL2 (0x940) 417 #define DIEPINT2 (0x948) 418 #define DIEPTSIZ2 (0x950) 419 #define DIEPDMA2 (0x954) 420 #define DIEPCTL3 (0x960) 421 #define DIEPINT3 (0x968) 422 #define DIEPTSIZ3 (0x970) 423 #define DIEPDMA3 (0x974) 424 #define DIEPCTL4 (0x980) 425 #define DIEPINT4 (0x988) 426 #define DIEPTSIZ4 (0x990) 427 #define DIEPDMA4 (0x994) 428 #define DIEPCTL5 (0x9A0) 429 #define DIEPINT5 (0x9A8) 430 #define DIEPTSIZ5 (0x9B0) 431 #define DIEPDMA5 (0x9B4) 432 #define DIEPCTL6 (0x9C0) 433 #define DIEPINT6 (0x9C8) 434 #define DIEPTSIZ6 (0x9D0) 435 #define DIEPDMA6 (0x9D4) 436 #define DIEPCTL7 (0x9E0) 437 #define DIEPINT7 (0x9E8) 438 #define DIEPTSIZ7 (0x9F0) 439 #define DIEPDMA7 (0x9F4) 440 #define DIEPCTL8 (0xA00) 441 #define DIEPINT8 (0xA08) 442 #define DIEPTSIZ8 (0xA10) 443 #define DIEPDMA8 (0xA14) 444 #define DIEPCTL9 (0xA20) 445 #define DIEPINT9 (0xA28) 446 #define DIEPTSIZ9 (0xA30) 447 #define DIEPDMA9 (0xA34) 448 #define DIEPCTL10 (0xA40) 449 #define DIEPINT10 (0xA48) 450 #define DIEPTSIZ10 (0xA50) 451 #define DIEPDMA10 (0xA54) 452 #define DIEPCTL11 (0xA60) 453 #define DIEPINT11 (0xA68) 454 #define DIEPTSIZ11 (0xA70) 455 #define DIEPDMA11 (0xA74) 456 #define DIEPCTL12 (0xA80) 457 #define DIEPINT12 (0xA88) 458 #define DIEPTSIZ12 (0xA90) 459 #define DIEPDMA12 (0xA94) 460 #define DIEPCTL13 (0xAA0) 461 #define DIEPINT13 (0xAA8) 462 #define DIEPTSIZ13 (0xAB0) 463 #define DIEPDMA13 (0xAB4) 464 #define DIEPCTL14 (0xAC0) 465 #define DIEPINT14 (0xAC8) 466 #define DIEPTSIZ14 (0xAD0) 467 #define DIEPDMA14 (0xAD4) 468 #define DIEPCTL15 (0xAE0) 469 #define DIEPINT15 (0xAE8) 470 #define DIEPTSIZ15 (0xAF0) 471 #define DIEPDMA15 (0xAF4) 472 473 /* Device Logical OUT Endpoint-Specific Registers */ 474 #define DOEPCTL(x) (0xB00 + 0x20 * (x)) 475 #define DOEPINT(x) (0xB08 + 0x20 * (x)) 476 #define DOEPTSIZ(x) (0xB10 + 0x20 * (x)) 477 #define DOEPDMA(x) (0xB14 + 0x20 * (x)) 478 #define DOEPCTL0 (0xB00) 479 #define DOEPINT0 (0xB08) 480 #define DOEPTSIZ0 (0xB10) 481 #define DOEPDMA0 (0xB14) 482 #define DOEPCTL1 (0xB20) 483 #define DOEPINT1 (0xB28) 484 #define DOEPTSIZ1 (0xB30) 485 #define DOEPDMA1 (0xB34) 486 #define DOEPCTL2 (0xB40) 487 #define DOEPINT2 (0xB48) 488 #define DOEPTSIZ2 (0xB50) 489 #define DOEPDMA2 (0xB54) 490 #define DOEPCTL3 (0xB60) 491 #define DOEPINT3 (0xB68) 492 #define DOEPTSIZ3 (0xB70) 493 #define DOEPDMA3 (0xB74) 494 #define DOEPCTL4 (0xB80) 495 #define DOEPINT4 (0xB88) 496 #define DOEPTSIZ4 (0xB90) 497 #define DOEPDMA4 (0xB94) 498 #define DOEPCTL5 (0xBA0) 499 #define DOEPINT5 (0xBA8) 500 #define DOEPTSIZ5 (0xBB0) 501 #define DOEPDMA5 (0xBB4) 502 #define DOEPCTL6 (0xBC0) 503 #define DOEPINT6 (0xBC8) 504 #define DOEPTSIZ6 (0xBD0) 505 #define DOEPDMA6 (0xBD4) 506 #define DOEPCTL7 (0xBE0) 507 #define DOEPINT7 (0xBE8) 508 #define DOEPTSIZ7 (0xBF0) 509 #define DOEPDMA7 (0xBF4) 510 #define DOEPCTL8 (0xC00) 511 #define DOEPINT8 (0xC08) 512 #define DOEPTSIZ8 (0xC10) 513 #define DOEPDMA8 (0xC14) 514 #define DOEPCTL9 (0xC20) 515 #define DOEPINT9 (0xC28) 516 #define DOEPTSIZ9 (0xC30) 517 #define DOEPDMA9 (0xC34) 518 #define DOEPCTL10 (0xC40) 519 #define DOEPINT10 (0xC48) 520 #define DOEPTSIZ10 (0xC50) 521 #define DOEPDMA10 (0xC54) 522 #define DOEPCTL11 (0xC60) 523 #define DOEPINT11 (0xC68) 524 #define DOEPTSIZ11 (0xC70) 525 #define DOEPDMA11 (0xC74) 526 #define DOEPCTL12 (0xC80) 527 #define DOEPINT12 (0xC88) 528 #define DOEPTSIZ12 (0xC90) 529 #define DOEPDMA12 (0xC94) 530 #define DOEPCTL13 (0xCA0) 531 #define DOEPINT13 (0xCA8) 532 #define DOEPTSIZ13 (0xCB0) 533 #define DOEPDMA13 (0xCB4) 534 #define DOEPCTL14 (0xCC0) 535 #define DOEPINT14 (0xCC8) 536 #define DOEPTSIZ14 (0xCD0) 537 #define DOEPDMA14 (0xCD4) 538 #define DOEPCTL15 (0xCE0) 539 #define DOEPINT15 (0xCE8) 540 #define DOEPTSIZ15 (0xCF0) 541 #define DOEPDMA15 (0xCF4) 542 543 /* Power and Clock Gating Register */ 544 #define PCGCCTL (0xE00) 545 546 #define EP0FIFO (0x1000) 547 548 /** 549 * This union represents the bit fields in the DMA Descriptor 550 * status quadlet. Read the quadlet into the <i>d32</i> member then 551 * set/clear the bits using the <i>b</i>it, <i>b_iso_out</i> and 552 * <i>b_iso_in</i> elements. 553 */ 554 typedef union dev_dma_desc_sts { 555 /** raw register data */ 556 unsigned int d32; 557 /** quadlet bits */ 558 struct { 559 /** Received number of bytes */ 560 unsigned bytes:16; 561 /** NAK bit - only for OUT EPs */ 562 unsigned nak:1; 563 unsigned reserved17_22:6; 564 /** Multiple Transfer - only for OUT EPs */ 565 unsigned mtrf:1; 566 /** Setup Packet received - only for OUT EPs */ 567 unsigned sr:1; 568 /** Interrupt On Complete */ 569 unsigned ioc:1; 570 /** Short Packet */ 571 unsigned sp:1; 572 /** Last */ 573 unsigned l:1; 574 /** Receive Status */ 575 unsigned sts:2; 576 /** Buffer Status */ 577 unsigned bs:2; 578 } b; 579 } dev_dma_desc_sts_t; 580 581 /** 582 * DMA Descriptor structure 583 * 584 * DMA Descriptor structure contains two quadlets: 585 * Status quadlet and Data buffer pointer. 586 */ 587 typedef struct dwc_otg_dev_dma_desc { 588 /** DMA Descriptor status quadlet */ 589 dev_dma_desc_sts_t status; 590 /** DMA Descriptor data buffer pointer */ 591 UINT32 buf; 592 } dwc_otg_dev_dma_desc_t; 593 594 #endif //ifndef __DW_USB_DXE_H__ 595