1/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31/dts-v1/;
32
33/memreserve/ 0x80000000 0x00010000;
34
35/ {
36};
37
38/ {
39	model = "FVP Base";
40	compatible = "arm,vfp-base", "arm,vexpress";
41	interrupt-parent = <&gic>;
42	#address-cells = <2>;
43	#size-cells = <2>;
44
45	chosen {
46		stdout-path = "serial0";
47	};
48
49	aliases {
50		serial0 = &v2m_serial0;
51		serial1 = &v2m_serial1;
52		serial2 = &v2m_serial2;
53		serial3 = &v2m_serial3;
54	};
55
56	psci {
57		compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
58		method = "smc";
59		cpu_suspend = <0xc4000001>;
60		cpu_off = <0x84000002>;
61		cpu_on = <0xc4000003>;
62		sys_poweroff = <0x84000008>;
63		sys_reset = <0x84000009>;
64	};
65
66	cpus {
67		#address-cells = <2>;
68		#size-cells = <0>;
69
70		cpu-map {
71			cluster0 {
72				core0 {
73					cpu = <&CPU0>;
74				};
75				core1 {
76					cpu = <&CPU1>;
77				};
78				core2 {
79					cpu = <&CPU2>;
80				};
81				core3 {
82					cpu = <&CPU3>;
83				};
84			};
85
86			cluster1 {
87				core0 {
88					cpu = <&CPU4>;
89				};
90				core1 {
91					cpu = <&CPU5>;
92				};
93				core2 {
94					cpu = <&CPU6>;
95				};
96				core3 {
97					cpu = <&CPU7>;
98				};
99			};
100		};
101
102		idle-states {
103			entry-method = "arm,psci";
104
105			CPU_SLEEP_0: cpu-sleep-0 {
106				compatible = "arm,idle-state";
107				local-timer-stop;
108				arm,psci-suspend-param = <0x0010000>;
109				entry-latency-us = <40>;
110				exit-latency-us = <100>;
111				min-residency-us = <150>;
112			};
113
114			CLUSTER_SLEEP_0: cluster-sleep-0 {
115				compatible = "arm,idle-state";
116				local-timer-stop;
117				arm,psci-suspend-param = <0x1010000>;
118				entry-latency-us = <500>;
119				exit-latency-us = <1000>;
120				min-residency-us = <2500>;
121			};
122		};
123
124		CPU0:cpu@0 {
125			device_type = "cpu";
126			compatible = "arm,armv8";
127			reg = <0x0 0x0>;
128			enable-method = "psci";
129			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
130		};
131
132		CPU1:cpu@1 {
133			device_type = "cpu";
134			compatible = "arm,armv8";
135			reg = <0x0 0x1>;
136			enable-method = "psci";
137			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
138		};
139
140		CPU2:cpu@2 {
141			device_type = "cpu";
142			compatible = "arm,armv8";
143			reg = <0x0 0x2>;
144			enable-method = "psci";
145			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
146		};
147
148		CPU3:cpu@3 {
149			device_type = "cpu";
150			compatible = "arm,armv8";
151			reg = <0x0 0x3>;
152			enable-method = "psci";
153			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
154		};
155
156		CPU4:cpu@100 {
157			device_type = "cpu";
158			compatible = "arm,armv8";
159			reg = <0x0 0x100>;
160			enable-method = "psci";
161			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
162		};
163
164		CPU5:cpu@101 {
165			device_type = "cpu";
166			compatible = "arm,armv8";
167			reg = <0x0 0x101>;
168			enable-method = "psci";
169			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
170		};
171
172		CPU6:cpu@102 {
173			device_type = "cpu";
174			compatible = "arm,armv8";
175			reg = <0x0 0x102>;
176			enable-method = "psci";
177			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
178		};
179
180		CPU7:cpu@103 {
181			device_type = "cpu";
182			compatible = "arm,armv8";
183			reg = <0x0 0x103>;
184			enable-method = "psci";
185			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
186		};
187	};
188
189	memory@80000000 {
190		device_type = "memory";
191		reg = <0x00000000 0x80000000 0 0x7F000000>,
192		      <0x00000008 0x80000000 0 0x80000000>;
193	};
194
195	gic: interrupt-controller@2c001000 {
196		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
197		#interrupt-cells = <3>;
198		#address-cells = <0>;
199		interrupt-controller;
200		reg = <0x0 0x2c001000 0 0x1000>,
201		      <0x0 0x2c002000 0 0x1000>,
202		      <0x0 0x2c004000 0 0x2000>,
203		      <0x0 0x2c006000 0 0x2000>;
204		interrupts = <1 9 0xf04>;
205	};
206
207	timer {
208		compatible = "arm,armv8-timer";
209		interrupts = <1 13 0xff01>,
210			     <1 14 0xff01>,
211			     <1 11 0xff01>,
212			     <1 10 0xff01>;
213		clock-frequency = <100000000>;
214	};
215
216	timer@2a810000 {
217			compatible = "arm,armv7-timer-mem";
218			reg = <0x0 0x2a810000 0x0 0x10000>;
219			clock-frequency = <100000000>;
220			#address-cells = <2>;
221			#size-cells = <2>;
222			ranges;
223			frame@2a830000 {
224				frame-number = <1>;
225				interrupts = <0 26 4>;
226				reg = <0x0 0x2a830000 0x0 0x10000>;
227			};
228	};
229
230	pmu {
231		compatible = "arm,armv8-pmuv3";
232		interrupts = <0 60 4>,
233			     <0 61 4>,
234			     <0 62 4>,
235			     <0 63 4>;
236	};
237
238	smb {
239		compatible = "simple-bus";
240
241		#address-cells = <2>;
242		#size-cells = <1>;
243		ranges = <0 0 0 0x08000000 0x04000000>,
244			 <1 0 0 0x14000000 0x04000000>,
245			 <2 0 0 0x18000000 0x04000000>,
246			 <3 0 0 0x1c000000 0x04000000>,
247			 <4 0 0 0x0c000000 0x04000000>,
248			 <5 0 0 0x10000000 0x04000000>;
249
250		#interrupt-cells = <1>;
251		interrupt-map-mask = <0 0 63>;
252		interrupt-map = <0 0  0 &gic 0  0 4>,
253				<0 0  1 &gic 0  1 4>,
254				<0 0  2 &gic 0  2 4>,
255				<0 0  3 &gic 0  3 4>,
256				<0 0  4 &gic 0  4 4>,
257				<0 0  5 &gic 0  5 4>,
258				<0 0  6 &gic 0  6 4>,
259				<0 0  7 &gic 0  7 4>,
260				<0 0  8 &gic 0  8 4>,
261				<0 0  9 &gic 0  9 4>,
262				<0 0 10 &gic 0 10 4>,
263				<0 0 11 &gic 0 11 4>,
264				<0 0 12 &gic 0 12 4>,
265				<0 0 13 &gic 0 13 4>,
266				<0 0 14 &gic 0 14 4>,
267				<0 0 15 &gic 0 15 4>,
268				<0 0 16 &gic 0 16 4>,
269				<0 0 17 &gic 0 17 4>,
270				<0 0 18 &gic 0 18 4>,
271				<0 0 19 &gic 0 19 4>,
272				<0 0 20 &gic 0 20 4>,
273				<0 0 21 &gic 0 21 4>,
274				<0 0 22 &gic 0 22 4>,
275				<0 0 23 &gic 0 23 4>,
276				<0 0 24 &gic 0 24 4>,
277				<0 0 25 &gic 0 25 4>,
278				<0 0 26 &gic 0 26 4>,
279				<0 0 27 &gic 0 27 4>,
280				<0 0 28 &gic 0 28 4>,
281				<0 0 29 &gic 0 29 4>,
282				<0 0 30 &gic 0 30 4>,
283				<0 0 31 &gic 0 31 4>,
284				<0 0 32 &gic 0 32 4>,
285				<0 0 33 &gic 0 33 4>,
286				<0 0 34 &gic 0 34 4>,
287				<0 0 35 &gic 0 35 4>,
288				<0 0 36 &gic 0 36 4>,
289				<0 0 37 &gic 0 37 4>,
290				<0 0 38 &gic 0 38 4>,
291				<0 0 39 &gic 0 39 4>,
292				<0 0 40 &gic 0 40 4>,
293				<0 0 41 &gic 0 41 4>,
294				<0 0 42 &gic 0 42 4>;
295
296		/include/ "rtsm_ve-motherboard.dtsi"
297	};
298
299	panels {
300		panel@0 {
301			compatible	= "panel";
302			mode		= "XVGA";
303			refresh		= <60>;
304			xres		= <1024>;
305			yres		= <768>;
306			pixclock	= <15748>;
307			left_margin	= <152>;
308			right_margin	= <48>;
309			upper_margin	= <23>;
310			lower_margin	= <3>;
311			hsync_len	= <104>;
312			vsync_len	= <4>;
313			sync		= <0>;
314			vmode		= "FB_VMODE_NONINTERLACED";
315			tim2		= "TIM2_BCD", "TIM2_IPC";
316			cntl		= "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
317			caps		= "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
318			bpp		= <16>;
319		};
320	};
321};
322