1/*
2 * pinctrl dts fils for Hislicon HiKey development board
3 *
4 */
5#include <dt-bindings/pinctrl/hisi.h>
6
7/ {
8	soc {
9		pmx0: pinmux@f7010000 {
10			pinctrl-names = "default";
11			pinctrl-0 = <
12				&boot_sel_pmx_func
13				&hkadc_ssi_pmx_func
14				&codec_clk_pmx_func
15				&pwm_in_pmx_func
16				&bl_pwm_pmx_func
17				>;
18
19			boot_sel_pmx_func: boot_sel_pmx_func {
20				pinctrl-single,pins = <
21					0x0    MUX_M0	/* BOOT_SEL     (IOMG000) */
22				>;
23			};
24
25			emmc_pmx_func: emmc_pmx_func {
26				pinctrl-single,pins = <
27					0x100  MUX_M0	/* EMMC_CLK     (IOMG064) */
28					0x104  MUX_M0	/* EMMC_CMD     (IOMG065) */
29					0x108  MUX_M0	/* EMMC_DATA0   (IOMG066) */
30					0x10c  MUX_M0	/* EMMC_DATA1   (IOMG067) */
31					0x110  MUX_M0	/* EMMC_DATA2   (IOMG068) */
32					0x114  MUX_M0	/* EMMC_DATA3   (IOMG069) */
33					0x118  MUX_M0	/* EMMC_DATA4   (IOMG070) */
34					0x11c  MUX_M0	/* EMMC_DATA5   (IOMG071) */
35					0x120  MUX_M0	/* EMMC_DATA6   (IOMG072) */
36					0x124  MUX_M0	/* EMMC_DATA7   (IOMG073) */
37				>;
38			};
39
40			sd_pmx_func: sd_pmx_func {
41				pinctrl-single,pins = <
42					0xc    MUX_M0	/* SD_CLK       (IOMG003) */
43					0x10   MUX_M0	/* SD_CMD       (IOMG004) */
44					0x14   MUX_M0	/* SD_DATA0     (IOMG005) */
45					0x18   MUX_M0	/* SD_DATA1     (IOMG006) */
46					0x1c   MUX_M0	/* SD_DATA2     (IOMG007) */
47					0x20   MUX_M0	/* SD_DATA3     (IOMG008) */
48				>;
49			};
50			sd_pmx_idle: sd_pmx_idle {
51				pinctrl-single,pins = <
52					0xc    MUX_M1	/* SD_CLK       (IOMG003) */
53					0x10   MUX_M1	/* SD_CMD       (IOMG004) */
54					0x14   MUX_M1	/* SD_DATA0     (IOMG005) */
55					0x18   MUX_M1	/* SD_DATA1     (IOMG006) */
56					0x1c   MUX_M1	/* SD_DATA2     (IOMG007) */
57					0x20   MUX_M1	/* SD_DATA3     (IOMG008) */
58				>;
59			};
60
61			sdio_pmx_func: sdio_pmx_func {
62				pinctrl-single,pins = <
63					0x128  MUX_M0	/* SDIO_CLK     (IOMG074) */
64					0x12c  MUX_M0	/* SDIO_CMD     (IOMG075) */
65					0x130  MUX_M0	/* SDIO_DATA0   (IOMG076) */
66					0x134  MUX_M0	/* SDIO_DATA1   (IOMG077) */
67					0x138  MUX_M0	/* SDIO_DATA2   (IOMG078) */
68					0x13c  MUX_M0	/* SDIO_DATA3   (IOMG079) */
69				>;
70			};
71			sdio_pmx_idle: sdio_pmx_idle {
72				pinctrl-single,pins = <
73					0x128  MUX_M1	/* SDIO_CLK     (IOMG074) */
74					0x12c  MUX_M1	/* SDIO_CMD     (IOMG075) */
75					0x130  MUX_M1	/* SDIO_DATA0   (IOMG076) */
76					0x134  MUX_M1	/* SDIO_DATA1   (IOMG077) */
77					0x138  MUX_M1	/* SDIO_DATA2   (IOMG078) */
78					0x13c  MUX_M1	/* SDIO_DATA3   (IOMG079) */
79				>;
80			};
81
82			isp_pmx_func: isp_pmx_func {
83				pinctrl-single,pins = <
84					0x24   MUX_M0	/* ISP_PWDN0    (IOMG009) */
85					0x28   MUX_M0	/* ISP_PWDN1    (IOMG010) */
86					0x2c   MUX_M0	/* ISP_PWDN2    (IOMG011) */
87					0x30   MUX_M1	/* ISP_SHUTTER0 (IOMG012) */
88					0x34   MUX_M1	/* ISP_SHUTTER1 (IOMG013) */
89					0x38   MUX_M1	/* ISP_PWM      (IOMG014) */
90					0x3c   MUX_M0	/* ISP_CCLK0    (IOMG015) */
91					0x40   MUX_M0	/* ISP_CCLK1    (IOMG016) */
92					0x44   MUX_M0	/* ISP_RESETB0  (IOMG017) */
93					0x48   MUX_M0	/* ISP_RESETB1  (IOMG018) */
94					0x4c   MUX_M1	/* ISP_STROBE0  (IOMG019) */
95					0x50   MUX_M1	/* ISP_STROBE1  (IOMG020) */
96					0x54   MUX_M0	/* ISP_SDA0     (IOMG021) */
97					0x58   MUX_M0	/* ISP_SCL0     (IOMG022) */
98					0x5c   MUX_M0	/* ISP_SDA1     (IOMG023) */
99					0x60   MUX_M0	/* ISP_SCL1     (IOMG024) */
100				>;
101			};
102
103			hkadc_ssi_pmx_func: hkadc_ssi_pmx_func {
104				pinctrl-single,pins = <
105					0x68   MUX_M0	/* HKADC_SSI    (IOMG026) */
106				>;
107			};
108
109			codec_clk_pmx_func: codec_clk_pmx_func {
110				pinctrl-single,pins = <
111					0x6c   MUX_M0	/* CODEC_CLK    (IOMG027) */
112				>;
113			};
114
115			codec_pmx_func: codec_pmx_func {
116				pinctrl-single,pins = <
117					0x70   MUX_M1	/* DMIC_CLK     (IOMG028) */
118					0x74   MUX_M0	/* CODEC_SYNC   (IOMG029) */
119					0x78   MUX_M0	/* CODEC_DI     (IOMG030) */
120					0x7c   MUX_M0	/* CODEC_DO     (IOMG031) */
121				>;
122			};
123
124			fm_pmx_func: fm_pmx_func {
125				pinctrl-single,pins = <
126					0x80   MUX_M1	/* FM_XCLK      (IOMG032) */
127					0x84   MUX_M1	/* FM_XFS       (IOMG033) */
128					0x88   MUX_M1	/* FM_DI        (IOMG034) */
129					0x8c   MUX_M1	/* FM_DO        (IOMG035) */
130				>;
131			};
132
133			bt_pmx_func: bt_pmx_func {
134				pinctrl-single,pins = <
135					0x90   MUX_M0	/* BT_XCLK      (IOMG036) */
136					0x94   MUX_M0	/* BT_XFS       (IOMG037) */
137					0x98   MUX_M0	/* BT_DI        (IOMG038) */
138					0x9c   MUX_M0	/* BT_DO        (IOMG039) */
139				>;
140			};
141
142			pwm_in_pmx_func: pwm_in_pmx_func {
143				pinctrl-single,pins = <
144					0xb8   MUX_M1	/* PWM_IN       (IOMG046) */
145				>;
146			};
147
148			bl_pwm_pmx_func: bl_pwm_pmx_func {
149				pinctrl-single,pins = <
150					0xbc   MUX_M1	/* BL_PWM       (IOMG047) */
151				>;
152			};
153
154			uart0_pmx_func: uart0_pmx_func {
155				pinctrl-single,pins = <
156					0xc0   MUX_M0	/* UART0_RXD    (IOMG048) */
157					0xc4   MUX_M0	/* UART0_TXD    (IOMG049) */
158				>;
159			};
160
161			uart1_pmx_func: uart1_pmx_func {
162				pinctrl-single,pins = <
163					0xc8   MUX_M0	/* UART1_CTS_N  (IOMG050) */
164					0xcc   MUX_M0	/* UART1_RTS_N  (IOMG051) */
165					0xd0   MUX_M0	/* UART1_RXD    (IOMG052) */
166					0xd4   MUX_M0	/* UART1_TXD    (IOMG053) */
167				>;
168			};
169
170			uart2_pmx_func: uart2_pmx_func {
171				pinctrl-single,pins = <
172					0xd8   MUX_M0	/* UART2_CTS_N  (IOMG054) */
173					0xdc   MUX_M0	/* UART2_RTS_N  (IOMG055) */
174					0xe0   MUX_M0	/* UART2_RXD    (IOMG056) */
175					0xe4   MUX_M0	/* UART2_TXD    (IOMG057) */
176				>;
177			};
178
179			uart3_pmx_func: uart3_pmx_func {
180				pinctrl-single,pins = <
181					0x180  MUX_M1	/* UART3_CTS_N  (IOMG096) */
182					0x184  MUX_M1	/* UART3_RTS_N  (IOMG097) */
183					0x188  MUX_M1	/* UART3_RXD    (IOMG098) */
184					0x18c  MUX_M1	/* UART3_TXD    (IOMG099) */
185				>;
186			};
187
188			uart4_pmx_func: uart4_pmx_func {
189				pinctrl-single,pins = <
190					0x1d0  MUX_M1	/* UART4_CTS_N  (IOMG116) */
191					0x1d4  MUX_M1	/* UART4_RTS_N  (IOMG117) */
192					0x1d8  MUX_M1	/* UART4_RXD    (IOMG118) */
193					0x1dc  MUX_M1	/* UART4_TXD    (IOMG119) */
194				>;
195			};
196
197			uart5_pmx_func: uart5_pmx_func {
198				pinctrl-single,pins = <
199					0x1c8  MUX_M1	/* UART5_RXD    (IOMG114) */
200					0x1cc  MUX_M1	/* UART5_TXD    (IOMG115) */
201				>;
202			};
203
204			i2c0_pmx_func: i2c0_pmx_func {
205				pinctrl-single,pins = <
206					0xe8   MUX_M0	/* I2C0_SCL     (IOMG058) */
207					0xec   MUX_M0	/* I2C0_SDA     (IOMG059) */
208				>;
209			};
210
211			i2c1_pmx_func: i2c1_pmx_func {
212				pinctrl-single,pins = <
213					0xf0   MUX_M0	/* I2C1_SCL     (IOMG060) */
214					0xf4   MUX_M0	/* I2C1_SDA     (IOMG061) */
215				>;
216			};
217
218			i2c2_pmx_func: i2c2_pmx_func {
219				pinctrl-single,pins = <
220					0xf8   MUX_M0	/* I2C2_SCL     (IOMG062) */
221					0xfc   MUX_M0	/* I2C2_SDA     (IOMG063) */
222				>;
223			};
224
225			spi0_pmx_func: spi0_pmx_func {
226				pinctrl-single,pins = <
227					0x1a0  MUX_M1   /* SPI0_DI      (IOMG104) */
228					0x1a4  MUX_M1	/* SPI0_DO	(IOMG105) */
229					0x1a8  MUX_M1	/* SPI0_CS_N	(IOMG106) */
230					0x1ac  MUX_M1	/* SPI0_CLK	(IOMG107) */
231				>;
232			};
233
234			modem_pcm_pmx_func: modem_pcm_pmx_func {
235				pinctrl-single,pins = <
236					0x198  MUX_M3	/* MODEM_PCM_XCLK  (IOMG102) */
237					0x19c  MUX_M3	/* MODEM_PCM_XFS  (IOMG103) */
238					0x1d0  MUX_M3	/* MODEM_PCM_DI  (IOMG116) */
239					0x1d4  MUX_M3	/* MODEM_PCM_DO  (IOMG117) */
240				>;
241			};
242
243		};
244
245		pmx1: pinmux@f7010800 {
246
247			pinctrl-names = "default";
248			pinctrl-0 = <
249				&boot_sel_cfg_func
250				&hkadc_ssi_cfg_func
251				&codec_clk_cfg_func
252				&pwm_in_cfg_func
253				&bl_pwm_cfg_func
254				>;
255
256			boot_sel_cfg_func: boot_sel_cfg_func {
257				pinctrl-single,pins = <
258					0x0    0x0	/* BOOT_SEL     (IOCFG000) */
259				>;
260				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
261				pinctrl-single,bias-pullup    = <PULL_UP   PULL_UP   PULL_DIS  PULL_UP>;
262				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
263			};
264
265			hkadc_ssi_cfg_func: hkadc_ssi_cfg_func {
266				pinctrl-single,pins = <
267					0x6c   0x0	/* HKADC_SSI    (IOCFG027) */
268				>;
269				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
270				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
271				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
272			};
273
274			emmc_clk_cfg_func: emmc_clk_cfg_func {
275				pinctrl-single,pins = <
276					0x104  0x0	/* EMMC_CLK     (IOCFG065) */
277				>;
278				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
279				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
280				pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
281			};
282
283			emmc_cfg_func: emmc_cfg_func {
284				pinctrl-single,pins = <
285					0x108  0x0	/* EMMC_CMD     (IOCFG066) */
286					0x10c  0x0	/* EMMC_DATA0   (IOCFG067) */
287					0x110  0x0	/* EMMC_DATA1   (IOCFG068) */
288					0x114  0x0	/* EMMC_DATA2   (IOCFG069) */
289					0x118  0x0	/* EMMC_DATA3   (IOCFG070) */
290					0x11c  0x0	/* EMMC_DATA4   (IOCFG071) */
291					0x120  0x0	/* EMMC_DATA5   (IOCFG072) */
292					0x124  0x0	/* EMMC_DATA6   (IOCFG073) */
293					0x128  0x0	/* EMMC_DATA7   (IOCFG074) */
294				>;
295				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
296				pinctrl-single,bias-pullup    = <PULL_UP   PULL_UP   PULL_DIS  PULL_UP>;
297				pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
298			};
299
300			emmc_rst_cfg_func: emmc_rst_cfg_func {
301				pinctrl-single,pins = <
302					0x12c  0x0	/* EMMC_RST_N   (IOCFG075) */
303				>;
304				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
305				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
306				pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
307			};
308
309			sd_clk_cfg_func: sd_clk_cfg_func {
310				pinctrl-single,pins = <
311					0xc    0x0	/* SD_CLK       (IOCFG003) */
312				>;
313				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
314				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
315				pinctrl-single,drive-strength = <DRIVE1_10MA DRIVE_MASK>;
316			};
317			sd_clk_cfg_idle: sd_clk_cfg_idle {
318				pinctrl-single,pins = <
319					0xc    0x0	/* SD_CLK       (IOCFG003) */
320				>;
321				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
322				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
323				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
324			};
325
326			sd_cfg_func: sd_cfg_func {
327				pinctrl-single,pins = <
328					0x10   0x0	/* SD_CMD       (IOCFG004) */
329					0x14   0x0	/* SD_DATA0     (IOCFG005) */
330					0x18   0x0	/* SD_DATA1     (IOCFG006) */
331					0x1c   0x0	/* SD_DATA2     (IOCFG007) */
332					0x20   0x0	/* SD_DATA3     (IOCFG008) */
333				>;
334				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
335				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
336				pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
337			};
338			sd_cfg_idle: sd_cfg_idle {
339				pinctrl-single,pins = <
340					0x10   0x0	/* SD_CMD       (IOCFG004) */
341					0x14   0x0	/* SD_DATA0     (IOCFG005) */
342					0x18   0x0	/* SD_DATA1     (IOCFG006) */
343					0x1c   0x0	/* SD_DATA2     (IOCFG007) */
344					0x20   0x0	/* SD_DATA3     (IOCFG008) */
345				>;
346				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
347				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
348				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
349			};
350
351			sdio_clk_cfg_func: sdio_clk_cfg_func {
352				pinctrl-single,pins = <
353					0x134  0x0	/* SDIO_CLK     (IOCFG077) */
354				>;
355				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
356				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
357				pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
358			};
359			sdio_clk_cfg_idle: sdio_clk_cfg_idle {
360				pinctrl-single,pins = <
361					0x134  0x0	/* SDIO_CLK     (IOCFG077) */
362				>;
363				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
364				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
365				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
366			};
367
368			sdio_cfg_func: sdio_cfg_func {
369				pinctrl-single,pins = <
370					0x138  0x0	/* SDIO_CMD     (IOCFG078) */
371					0x13c  0x0	/* SDIO_DATA0   (IOCFG079) */
372					0x140  0x0	/* SDIO_DATA1   (IOCFG080) */
373					0x144  0x0	/* SDIO_DATA2   (IOCFG081) */
374					0x148  0x0	/* SDIO_DATA3   (IOCFG082) */
375				>;
376				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
377				pinctrl-single,bias-pullup    = <PULL_UP   PULL_UP   PULL_DIS  PULL_UP>;
378				pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
379			};
380			sdio_cfg_idle: sdio_cfg_idle {
381				pinctrl-single,pins = <
382					0x138  0x0	/* SDIO_CMD     (IOCFG078) */
383					0x13c  0x0	/* SDIO_DATA0   (IOCFG079) */
384					0x140  0x0	/* SDIO_DATA1   (IOCFG080) */
385					0x144  0x0	/* SDIO_DATA2   (IOCFG081) */
386					0x148  0x0	/* SDIO_DATA3   (IOCFG082) */
387				>;
388				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
389				pinctrl-single,bias-pullup    = <PULL_UP   PULL_UP   PULL_DIS  PULL_UP>;
390				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
391			};
392
393			isp_cfg_func1: isp_cfg_func1 {
394				pinctrl-single,pins = <
395					0x28   0x0	/* ISP_PWDN0    (IOCFG010) */
396					0x2c   0x0	/* ISP_PWDN1    (IOCFG011) */
397					0x30   0x0	/* ISP_PWDN2    (IOCFG012) */
398					0x34   0x0	/* ISP_SHUTTER0 (IOCFG013) */
399					0x38   0x0	/* ISP_SHUTTER1 (IOCFG014) */
400					0x3c   0x0	/* ISP_PWM      (IOCFG015) */
401					0x40   0x0	/* ISP_CCLK0    (IOCFG016) */
402					0x44   0x0	/* ISP_CCLK1    (IOCFG017) */
403					0x48   0x0	/* ISP_RESETB0  (IOCFG018) */
404					0x4c   0x0	/* ISP_RESETB1  (IOCFG019) */
405					0x50   0x0	/* ISP_STROBE0  (IOCFG020) */
406					0x58   0x0	/* ISP_SDA0     (IOCFG022) */
407					0x5c   0x0	/* ISP_SCL0     (IOCFG023) */
408					0x60   0x0	/* ISP_SDA1     (IOCFG024) */
409					0x64   0x0	/* ISP_SCL1     (IOCFG025) */
410				>;
411				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
412				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
413				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
414			};
415			isp_cfg_idle1: isp_cfg_idle1 {
416				pinctrl-single,pins = <
417					0x34   0x0	/* ISP_SHUTTER0 (IOCFG013) */
418					0x38   0x0	/* ISP_SHUTTER1 (IOCFG014) */
419				>;
420				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
421				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
422				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
423			};
424
425			isp_cfg_func2: isp_cfg_func2 {
426				pinctrl-single,pins = <
427					0x54   0x0	/* ISP_STROBE1  (IOCFG021) */
428				>;
429				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
430				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
431				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
432			};
433
434			codec_clk_cfg_func: codec_clk_cfg_func {
435				pinctrl-single,pins = <
436					0x70   0x0	/* CODEC_CLK    (IOCFG028) */
437				>;
438				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
439				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
440				pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
441			};
442			codec_clk_cfg_idle: codec_clk_cfg_idle {
443				pinctrl-single,pins = <
444					0x70   0x0	/* CODEC_CLK    (IOCFG028) */
445				>;
446				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
447				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
448				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
449			};
450
451			codec_cfg_func1: codec_cfg_func1 {
452				pinctrl-single,pins = <
453					0x74   0x0	/* DMIC_CLK     (IOCFG029) */
454				>;
455				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
456				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
457				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
458			};
459
460			codec_cfg_func2: codec_cfg_func2 {
461				pinctrl-single,pins = <
462					0x78   0x0	/* CODEC_SYNC   (IOCFG030) */
463					0x7c   0x0	/* CODEC_DI     (IOCFG031) */
464					0x80   0x0	/* CODEC_DO     (IOCFG032) */
465				>;
466				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
467				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
468				pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
469			};
470			codec_cfg_idle2: codec_cfg_idle2 {
471				pinctrl-single,pins = <
472					0x78   0x0	/* CODEC_SYNC   (IOCFG030) */
473					0x7c   0x0	/* CODEC_DI     (IOCFG031) */
474					0x80   0x0	/* CODEC_DO     (IOCFG032) */
475				>;
476				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
477				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
478				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
479			};
480
481			fm_cfg_func: fm_cfg_func {
482				pinctrl-single,pins = <
483					0x84   0x0	/* FM_XCLK      (IOCFG033) */
484					0x88   0x0	/* FM_XFS       (IOCFG034) */
485					0x8c   0x0	/* FM_DI        (IOCFG035) */
486					0x90   0x0	/* FM_DO        (IOCFG036) */
487				>;
488				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
489				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
490				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
491			};
492
493			bt_cfg_func: bt_cfg_func {
494				pinctrl-single,pins = <
495					0x94   0x0	/* BT_XCLK      (IOCFG037) */
496					0x98   0x0	/* BT_XFS       (IOCFG038) */
497					0x9c   0x0	/* BT_DI        (IOCFG039) */
498					0xa0   0x0	/* BT_DO        (IOCFG040) */
499				>;
500				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
501				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
502				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
503			};
504			bt_cfg_idle: bt_cfg_idle {
505				pinctrl-single,pins = <
506					0x94   0x0	/* BT_XCLK      (IOCFG037) */
507					0x98   0x0	/* BT_XFS       (IOCFG038) */
508					0x9c   0x0	/* BT_DI        (IOCFG039) */
509					0xa0   0x0	/* BT_DO        (IOCFG040) */
510				>;
511				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
512				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
513				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
514			};
515
516			pwm_in_cfg_func: pwm_in_cfg_func {
517				pinctrl-single,pins = <
518					0xbc   0x0	/* PWM_IN       (IOCFG047) */
519				>;
520				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
521				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
522				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
523			};
524
525			bl_pwm_cfg_func: bl_pwm_cfg_func {
526				pinctrl-single,pins = <
527					0xc0   0x0	/* BL_PWM       (IOCFG048) */
528				>;
529				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
530				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
531				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
532			};
533
534			uart0_cfg_func1: uart0_cfg_func1 {
535				pinctrl-single,pins = <
536					0xc4   0x0	/* UART0_RXD    (IOCFG049) */
537				>;
538				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
539				pinctrl-single,bias-pullup    = <PULL_UP   PULL_UP   PULL_DIS  PULL_UP>;
540				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
541			};
542
543			uart0_cfg_func2: uart0_cfg_func2 {
544				pinctrl-single,pins = <
545					0xc8   0x0	/* UART0_TXD    (IOCFG050) */
546				>;
547				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
548				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
549				pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
550			};
551
552			uart1_cfg_func1: uart1_cfg_func1 {
553				pinctrl-single,pins = <
554					0xcc   0x0	/* UART1_CTS_N  (IOCFG051) */
555					0xd4   0x0	/* UART1_RXD    (IOCFG053) */
556				>;
557				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
558				pinctrl-single,bias-pullup    = <PULL_UP   PULL_UP   PULL_DIS  PULL_UP>;
559				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
560			};
561
562			uart1_cfg_func2: uart1_cfg_func2 {
563				pinctrl-single,pins = <
564					0xd0   0x0	/* UART1_RTS_N  (IOCFG052) */
565					0xd8   0x0	/* UART1_TXD    (IOCFG054) */
566				>;
567				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
568				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
569				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
570			};
571
572			uart2_cfg_func: uart2_cfg_func {
573				pinctrl-single,pins = <
574					0xdc   0x0	/* UART2_CTS_N  (IOCFG055) */
575					0xe0   0x0	/* UART2_RTS_N  (IOCFG056) */
576					0xe4   0x0	/* UART2_RXD    (IOCFG057) */
577					0xe8   0x0	/* UART2_TXD    (IOCFG058) */
578				>;
579				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
580				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
581				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
582			};
583
584			uart3_cfg_func: uart3_cfg_func {
585				pinctrl-single,pins = <
586					0x190  0x0	/* UART3_CTS_N  (IOCFG100) */
587					0x194  0x0	/* UART3_RTS_N  (IOCFG101) */
588					0x198  0x0	/* UART3_RXD    (IOCFG102) */
589					0x19c  0x0	/* UART3_TXD    (IOCFG103) */
590				>;
591				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
592				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
593				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
594			};
595
596			uart4_cfg_func: uart4_cfg_func {
597				pinctrl-single,pins = <
598					0x1e0  0x0	/* UART4_CTS_N  (IOCFG120) */
599					0x1e4  0x0	/* UART4_RTS_N  (IOCFG121) */
600					0x1e8  0x0	/* UART4_RXD    (IOCFG122) */
601					0x1ec  0x0	/* UART4_TXD    (IOCFG123) */
602				>;
603				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
604				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
605				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
606			};
607
608			uart5_cfg_func: uart5_cfg_func {
609				pinctrl-single,pins = <
610					0x1d8  0x0	/* UART4_RXD    (IOCFG118) */
611					0x1dc  0x0	/* UART4_TXD    (IOCFG119) */
612				>;
613				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
614				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
615				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
616			};
617
618			i2c0_cfg_func: i2c0_cfg_func {
619				pinctrl-single,pins = <
620					0xec   0x0	/* I2C0_SCL     (IOCFG059) */
621					0xf0   0x0	/* I2C0_SDA     (IOCFG060) */
622				>;
623				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
624				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
625				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
626			};
627
628			i2c1_cfg_func: i2c1_cfg_func {
629				pinctrl-single,pins = <
630					0xf4   0x0	/* I2C1_SCL     (IOCFG061) */
631					0xf8   0x0	/* I2C1_SDA     (IOCFG062) */
632				>;
633				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
634				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
635				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
636			};
637
638			i2c2_cfg_func: i2c2_cfg_func {
639				pinctrl-single,pins = <
640					0xfc   0x0	/* I2C2_SCL     (IOCFG063) */
641					0x100  0x0	/* I2C2_SDA     (IOCFG064) */
642				>;
643				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
644				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
645				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
646			};
647
648			spi0_cfg_func: spi0_cfg_func {
649				pinctrl-single,pins = <
650					0x1b0  0x0	/* SPI0_DI	(IOCFG108) */
651					0x1b4  0x0	/* SPI0_DO	(IOCFG109) */
652					0x1b8  0x0	/* SPI0_CS_N	(IOCFG110) */
653					0x1bc  0x0	/* SPI0_CLK	(IOCFG111) */
654				>;
655				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS PULL_DOWN>;
656				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS PULL_UP>;
657				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
658			};
659
660			modem_pcm_cfg_func: modem_pcm_cfg_func {
661				pinctrl-single,pins = <
662					0x1a8  0x0	/* MODEM_PCM_XCLK  (IOCFG106) */
663					0x1ac  0x0	/* MODEM_PCM_XFS  (IOCFG107) */
664					0x1e0  0x0	/* MODEM_PCM_DI  (IOCFG120) */
665					0x1e4  0x0	/* MODEM_PCM_DO  (IOCFG121) */
666				>;
667				pinctrl-single,bias-pulldown  = <PULL_DOWN  PULL_DOWN PULL_DIS  PULL_DOWN>;
668				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
669				pinctrl-single,drive-strength = <DRIVE2_02MA DRIVE_MASK>;
670			};
671		};
672
673		pmx2: pinmux@f8001800 {
674
675			pinctrl-names = "default";
676			pinctrl-0 = <
677				&rstout_n_cfg_func
678				>;
679
680			rstout_n_cfg_func: rstout_n_cfg_func {
681				pinctrl-single,pins = <
682					0x0    0x0	/* RSTOUT_N     (IOCFG000) */
683				>;
684				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
685				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
686				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
687			};
688
689			pmu_peri_en_cfg_func: pmu_peri_en_cfg_func {
690				pinctrl-single,pins = <
691					0x4    0x0	/* PMU_PERI_EN  (IOCFG001) */
692				>;
693				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
694				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
695				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
696			};
697
698			sysclk0_en_cfg_func: sysclk0_en_cfg_func {
699				pinctrl-single,pins = <
700					0x8    0x0	/* SYSCLK0_EN   (IOCFG002) */
701				>;
702				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
703				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
704				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
705			};
706
707			jtag_tdo_cfg_func: jtag_tdo_cfg_func {
708				pinctrl-single,pins = <
709					0xc    0x0	/* JTAG_TDO     (IOCFG003) */
710				>;
711				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
712				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
713				pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
714			};
715
716			rf_reset_cfg_func: rf_reset_cfg_func {
717				pinctrl-single,pins = <
718					0x70   0x0	/* RF_RESET0    (IOCFG028) */
719					0x74   0x0	/* RF_RESET1    (IOCFG029) */
720				>;
721				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
722				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
723				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
724			};
725		};
726	};
727};
728