1 /** @file
2 
3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
4 
5   This program and the accompanying materials
6   are licensed and made available under the terms and conditions of the BSD License
7   which accompanies this distribution.  The full text of the license may be found at
8   http://opensource.org/licenses/bsd-license.php
9 
10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 
13 **/
14 
15 #include <PiPei.h>
16 
17 #include <Library/ArmLib.h>
18 #include <Library/PrePiLib.h>
19 #include <Library/PcdLib.h>
20 
21 // DDR attributes
22 #define DDR_ATTRIBUTES_CACHED                ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
23 #define DDR_ATTRIBUTES_UNCACHED              ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
24 
25 // SoC registers. L3 interconnects
26 #define SOC_REGISTERS_L3_PHYSICAL_BASE       0x68000000
27 #define SOC_REGISTERS_L3_PHYSICAL_LENGTH     0x08000000
28 #define SOC_REGISTERS_L3_ATTRIBUTES          ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
29 
30 // SoC registers. L4 interconnects
31 #define SOC_REGISTERS_L4_PHYSICAL_BASE       0x48000000
32 #define SOC_REGISTERS_L4_PHYSICAL_LENGTH     0x08000000
33 #define SOC_REGISTERS_L4_ATTRIBUTES          ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
34 
35 VOID
InitCache(IN UINT32 MemoryBase,IN UINT32 MemoryLength)36 InitCache (
37   IN  UINT32  MemoryBase,
38   IN  UINT32  MemoryLength
39   )
40 {
41   UINT32                        CacheAttributes;
42   ARM_MEMORY_REGION_DESCRIPTOR  MemoryTable[5];
43   VOID                          *TranslationTableBase;
44   UINTN                         TranslationTableSize;
45 
46   if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
47     CacheAttributes = DDR_ATTRIBUTES_CACHED;
48   } else {
49     CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
50   }
51 
52   // DDR
53   MemoryTable[0].PhysicalBase = MemoryBase;
54   MemoryTable[0].VirtualBase  = MemoryBase;
55   MemoryTable[0].Length       = MemoryLength;
56   MemoryTable[0].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;
57 
58   // SOC Registers. L3 interconnects
59   MemoryTable[1].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;
60   MemoryTable[1].VirtualBase  = SOC_REGISTERS_L3_PHYSICAL_BASE;
61   MemoryTable[1].Length       = SOC_REGISTERS_L3_PHYSICAL_LENGTH;
62   MemoryTable[1].Attributes   = SOC_REGISTERS_L3_ATTRIBUTES;
63 
64   // SOC Registers. L4 interconnects
65   MemoryTable[2].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;
66   MemoryTable[2].VirtualBase  = SOC_REGISTERS_L4_PHYSICAL_BASE;
67   MemoryTable[2].Length       = SOC_REGISTERS_L4_PHYSICAL_LENGTH;
68   MemoryTable[2].Attributes   = SOC_REGISTERS_L4_ATTRIBUTES;
69 
70   // End of Table
71   MemoryTable[3].PhysicalBase = 0;
72   MemoryTable[3].VirtualBase  = 0;
73   MemoryTable[3].Length       = 0;
74   MemoryTable[3].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;
75 
76   ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);
77 
78   BuildMemoryAllocationHob((EFI_PHYSICAL_ADDRESS)(UINTN)TranslationTableBase, TranslationTableSize, EfiBootServicesData);
79 }
80