1 /*
2 * Copyright (c) 2014-2015, Linaro Ltd. All rights reserved.
3 * Copyright (c) 2014-2015, Hisilicon Ltd. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * Neither the name of ARM nor the names of its contributors may be used
16 * to endorse or promote products derived from this software without specific
17 * prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <console.h>
33 #include <debug.h>
34 #include <errno.h>
35 #include <mmio.h>
36 #include <string.h>
37 #include <sp804_timer.h>
38 #include <dw_mmc.h>
39 #include <partitions.h>
40 #include <platform_def.h>
41 #include <hi6220.h>
42 #include <hi6553.h>
43
44 #define MMC_PLL 100000000
45
46 #define IDMAC_DES0_DIC (1 << 1)
47 #define IDMAC_DES0_LD (1 << 2)
48 #define IDMAC_DES0_FS (1 << 3)
49 #define IDMAC_DES0_CH (1 << 4)
50 #define IDMAC_DES0_ER (1 << 5)
51 #define IDMAC_DES0_CES (1 << 30)
52 #define IDMAC_DES0_OWN (1 << 31)
53
54 #define IDMAC_DES1_BS1(x) ((x) & 0x1fff)
55 #define IDMAC_DES2_BS2(x) (((x) & 0x1fff) << 13)
56
57 struct idmac_desc {
58 unsigned int des0;
59 unsigned int des1;
60 unsigned int des2;
61 unsigned int des3;
62 };
63
mmc_state(unsigned int data)64 static inline int mmc_state(unsigned int data)
65 {
66 return ((data & MMC_STATUS_CURRENT_STATE_MASK) >>
67 MMC_STATUS_CURRENT_STATE_SHIFT);
68 }
69
wait_data_ready(void)70 static inline int wait_data_ready(void)
71 {
72 unsigned int data;
73
74 while (1) {
75 data = mmio_read_32(MMC0_RINTSTS);
76 if (data & (MMC_INT_DCRC | MMC_INT_DRT | MMC_INT_SBE |
77 MMC_INT_EBE)) {
78 NOTICE("unwanted interrupts:0x%x\n", data);
79 return -EINVAL;
80 }
81 if (data & MMC_INT_DTO)
82 break;
83 }
84 /* clear interrupts */
85 mmio_write_32(MMC0_RINTSTS, ~0);
86 return 0;
87 }
88
update_mmc0_clock(void)89 static int update_mmc0_clock(void)
90 {
91 unsigned int data;
92
93 /* CMD_UPDATE_CLK */
94 data = BIT_CMD_WAIT_PRVDATA_COMPLETE | BIT_CMD_UPDATE_CLOCK_ONLY |
95 BIT_CMD_START;
96 mmio_write_32(MMC0_CMD, data);
97 while (1) {
98 data = mmio_read_32(MMC0_CMD);
99 if (!(data & CMD_START_BIT))
100 break;
101 data = mmio_read_32(MMC0_RINTSTS);
102 if (data & MMC_INT_HLE) {
103 NOTICE("fail to update mmc clock frequency\n");
104 return -EINVAL;
105 }
106 }
107 return 0;
108 }
109
set_mmc0_clock(int rate)110 static int set_mmc0_clock(int rate)
111 {
112 int ret, divider, found = 0;
113 unsigned int data;
114
115 for (divider = 1; divider < 256; divider++) {
116 if ((MMC_PLL / (2 * divider)) <= rate) {
117 found = 1;
118 break;
119 }
120 }
121 if (!found)
122 return -EINVAL;
123
124 /* wait until mmc is idle */
125 do {
126 data = mmio_read_32(MMC0_STATUS);
127 } while (data & MMC_STS_DATA_BUSY);
128
129 /* Disable mmc clock first */
130 mmio_write_32(MMC0_CLKENA, 0);
131 do {
132 ret = update_mmc0_clock();
133 } while (ret);
134
135 /* enable mmc clock */
136 do {
137 mmio_write_32(MMC0_CLKENA, 1);
138 mmio_write_32(MMC0_CLKSRC, 0);
139 mmio_write_32(MMC0_CLKDIV, divider);
140 ret = update_mmc0_clock();
141 } while (ret);
142 return 0;
143 }
144
set_mmc0_io(void)145 static void set_mmc0_io(void)
146 {
147 mmio_write_32(MMC0_CTYPE, MMC_8BIT_MODE);
148 mmio_write_32(MMC0_TMOUT, ~0); /* maxium timeout value */
149 mmio_write_32(MMC0_DEBNCE, 0x00ffffff);
150 mmio_write_32(MMC0_BLKSIZ, MMC_BLOCK_SIZE);
151 mmio_write_32(MMC0_BYTCNT, 256 * 1024);
152 }
153
mmc0_send_cmd(unsigned int cmd,unsigned int arg,unsigned int * buf)154 static int mmc0_send_cmd(unsigned int cmd, unsigned int arg, unsigned int *buf)
155 {
156 unsigned int data, err_mask;
157
158 if (!buf) {
159 NOTICE("buf is invalid\n");
160 return -EFAULT;
161 }
162
163 mmio_write_32(MMC0_CMDARG, arg);
164
165 /* clear interrupts */
166 mmio_write_32(MMC0_RINTSTS, ~0);
167
168 switch (cmd) {
169 case 0:
170 data = BIT_CMD_SEND_INIT;
171 break;
172 case 1:
173 data = BIT_CMD_RESPONSE_EXPECT;
174 break;
175 case 2:
176 data = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_LONG_RESPONSE |
177 BIT_CMD_CHECK_RESPONSE_CRC | BIT_CMD_SEND_INIT;
178 break;
179 case 3:
180 data = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
181 BIT_CMD_SEND_INIT;
182 break;
183 case 8:
184 data = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
185 BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
186 BIT_CMD_WAIT_PRVDATA_COMPLETE;
187 break;
188 case 9:
189 data = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
190 BIT_CMD_LONG_RESPONSE;
191 break;
192 case 12:
193 data = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
194 BIT_CMD_STOP_ABORT_CMD;
195 break;
196 case 17:
197 case 18:
198 data = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
199 BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
200 BIT_CMD_WAIT_PRVDATA_COMPLETE;
201 break;
202 case 24:
203 case 25:
204 data = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
205 BIT_CMD_DATA_EXPECTED | BIT_CMD_WRITE |
206 BIT_CMD_WAIT_PRVDATA_COMPLETE;
207 break;
208 case 30:
209 data = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
210 BIT_CMD_DATA_EXPECTED;
211 break;
212 case 7:
213 if (arg)
214 data = BIT_CMD_RESPONSE_EXPECT |
215 BIT_CMD_CHECK_RESPONSE_CRC;
216 else
217 data = 0;
218 break;
219 default:
220 data = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
221 break;
222 }
223 data |= (cmd & 0x3f) | BIT_CMD_USE_HOLD_REG | BIT_CMD_START;
224 mmio_write_32(MMC0_CMD, data);
225 err_mask = MMC_INT_EBE | MMC_INT_HLE | MMC_INT_RTO | MMC_INT_RCRC |
226 MMC_INT_RE;
227 do {
228 data = mmio_read_32(MMC0_RINTSTS);
229 if (data & err_mask) {
230 NOTICE("mmc: error status 0x%x\n", data);
231 return -EIO;
232 }
233 } while (!(data & MMC_INT_CMD_DONE));
234
235 buf[0] = mmio_read_32(MMC0_RESP0);
236 if ((cmd == 2) || (cmd == 9)) {
237 buf[1] = mmio_read_32(MMC0_RESP1);
238 buf[2] = mmio_read_32(MMC0_RESP2);
239 buf[3] = mmio_read_32(MMC0_RESP3);
240 }
241 return 0;
242 }
243
244 /* Only print error message if it meets failure? */
mmc0_check_tran_mode(void)245 static void mmc0_check_tran_mode(void)
246 {
247 unsigned int buf[4];
248 int ret;
249
250 mmio_write_32(MMC0_RINTSTS, ~0);
251
252 while (1) {
253 ret = mmc0_send_cmd(13, EMMC_FIX_RCA << 16, buf);
254 if (ret) {
255 NOTICE("failed on command 13\n");
256 return;
257 }
258 if (((buf[0] >> 9) & 0xf) == 4)
259 return;
260 }
261 }
262
mmc0_update_ext_csd(int index,int value)263 static int mmc0_update_ext_csd(int index, int value)
264 {
265 unsigned int arg, data, buf[4];
266 int ret;
267
268 arg = 3 << 24;
269 arg |= (index & 0xff) << 16;
270 arg |= (value & 0xff) << 8;
271 arg |= 1;
272 memset(buf, 0, 4 * sizeof(buf[0]));
273
274 ret = mmc0_send_cmd(6, arg, buf);
275 if (ret) {
276 NOTICE("failed to send command 6\n");
277 return ret;
278 }
279
280 /* wait busy de-assert */
281 while (1) {
282 data = mmio_read_32(MMC0_STATUS);
283 if (!(data & MMC_STS_DATA_BUSY))
284 break;
285 }
286
287 do {
288 ret = mmc0_send_cmd(13, EMMC_FIX_RCA << 16, buf);
289 if (ret) {
290 NOTICE("failed to send command 13\n");
291 return ret;
292 }
293
294 if (buf[0] & MMC_STATUS_SWITCH_ERROR) {
295 NOTICE("maybe switch mmc mode error\n");
296 return -1;
297 }
298 } while (mmc_state(buf[0]) == MMC_STATE_PRG);
299
300 return 0;
301 }
302
303 #define EXTCSD_BUS_WIDTH 183
304
mmc0_set_clock_and_width(int rate,int width)305 static int mmc0_set_clock_and_width(int rate, int width)
306 {
307 int ret;
308
309 switch (width) {
310 case 0:
311 mmio_write_32(MMC0_CTYPE, 0);
312 ret = mmc0_update_ext_csd(EXTCSD_BUS_WIDTH, 0);
313 break;
314 case 8:
315 mmio_write_32(MMC0_CTYPE, 1 << 16);
316 ret = mmc0_update_ext_csd(EXTCSD_BUS_WIDTH, 2 + 4);
317 mmio_write_32(MMC0_UHSREG, 1 << 16);
318 break;
319 default:
320 NOTICE("wrong bus width:%d\n", width);
321 return -EINVAL;
322 }
323 if (ret) {
324 NOTICE("return failure on %s, %d\n", __func__, __LINE__);
325 return ret;
326 }
327
328 set_mmc0_clock(rate);
329 return 0;
330 }
331
332 static int manu_id;
333
334 #define EXTCSD_HS_TIMING 185
335
336 #ifdef EMMC_READ_EXT_CSD
337 static int mmc0_read_ext_csd(unsigned int dst_start);
338 #endif
enum_mmc0_card(void)339 static int enum_mmc0_card(void)
340 {
341 unsigned int buf[4], cid[4];
342 int ret = 0, i, version;
343
344 /* CMD0: reset to IDLE */
345 ret = mmc0_send_cmd(0, 0, buf);
346 if (ret) {
347 NOTICE("failed to send IDLE command\n");
348 return ret;
349 }
350
351 while (1) {
352 udelay(100);
353 /* CMD1: READY */
354 ret = mmc0_send_cmd(1, 0x40ff8000, buf);
355 if (ret) {
356 NOTICE("failed to send READY command\n");
357 return ret;
358 }
359 if (buf[0] & 0x80000000)
360 break;
361 }
362
363 /* CMD2: IDENT */
364 ret = mmc0_send_cmd(2, 0, buf);
365 if (ret) {
366 NOTICE("failed to send IDENT command\n");
367 return ret;
368 }
369 VERBOSE("manuid:");
370 for (i = 0; i < 4; i++) {
371 cid[i] = buf[i];
372 VERBOSE(" 0x%x", cid[i]);
373 }
374 VERBOSE("\n");
375
376 /* CMD3: STBY */
377 ret = mmc0_send_cmd(3, EMMC_FIX_RCA << 16, buf);
378 if (ret) {
379 NOTICE("failed to send STBY command\n");
380 return ret;
381 }
382
383 /* CMD9: get CSD */
384 ret = mmc0_send_cmd(9, EMMC_FIX_RCA << 16, buf);
385 if (ret) {
386 NOTICE("failed to get CSD\n");
387 return ret;
388 }
389 VERBOSE("CSD: %x-%x-%x-%x\n", buf[0], buf[1], buf[2], buf[3]);
390 version = (buf[3] >> 26) & 0xf;
391 switch (version) {
392 case 0: /* MMC v1.0-v1.2 */
393 case 1: /* MMC v1.4 */
394 manu_id = (cid[3] >> 8) & 0xffffff;
395 break;
396 case 2: /* MMC v2.0-v2.2 */
397 case 3: /* MMC v3.1-v3.3 */
398 case 4: /* MMC v4 */
399 manu_id = (cid[3] >> 24) & 0xff;
400 break;
401 default:
402 WARN("wrong mmc version (%d) is specified.\n", version);
403 break;
404 }
405
406 VERBOSE("mmc version:%d\n", version);
407 /* CMD7: TRAN */
408 ret = mmc0_send_cmd(7, EMMC_FIX_RCA << 16, buf);
409 if (ret) {
410 NOTICE("failed to send TRAN command\n");
411 return ret;
412 }
413 mmc0_check_tran_mode();
414
415 mmc0_set_clock_and_width(400000, 0);
416 #ifdef EMMC_READ_EXT_CSD
417 mmc0_read_ext_csd(0x50000);
418 #endif
419 ret = mmc0_update_ext_csd(EXTCSD_HS_TIMING, 1);
420 if (ret) {
421 NOTICE("alter HS mode fail\n");
422 }
423
424 ret = mmc0_set_clock_and_width(50000000, 8);
425 return ret;
426 }
427
enable_mmc0(void)428 static int enable_mmc0(void)
429 {
430 unsigned int data;
431
432 /* reset mmc0 */
433 data = MMC_CTRL_RESET | MMC_FIFO_RESET | MMC_DMA_RESET;
434 mmio_write_32(MMC0_CTRL, data);
435 /* wait until reset operation finished */
436 do {
437 data = mmio_read_32(MMC0_CTRL);
438 } while (data);
439
440 data = MMC_INT_EN | MMC_DMA_EN;
441 mmio_write_32(MMC0_CTRL, data);
442
443 mmio_write_32(MMC0_INTMASK, 0x0);
444 mmio_write_32(MMC0_RINTSTS, ~0);
445 mmio_write_32(MMC0_IDINTEN, ~0);
446 mmio_write_32(MMC0_IDSTS, ~0);
447
448 mmio_write_32(MMC0_BLKSIZ, MMC_BLOCK_SIZE);
449 mmio_write_32(MMC0_BMOD, MMC_IDMAC_SWRESET);
450 do {
451 data = mmio_read_32(MMC0_BMOD);
452 } while (data & MMC_IDMAC_SWRESET);
453
454 data |= MMC_IDMAC_ENABLE | MMC_IDMAC_FB;
455 mmio_write_32(MMC0_BMOD, data);
456
457 data = MMC_DMA_BURST_SIZE(2) | MMC_FIFO_TWMARK(8) | MMC_FIFO_RWMARK(7);
458 mmio_write_32(MMC0_FIFOTH, data);
459 data = MMC_CARD_RD_THR(512) | MMC_CARD_RD_THR_EN;
460 mmio_write_32(MMC0_CARDTHRCTL, data);
461
462 udelay(100);
463 set_mmc0_clock(378000);
464 udelay(100);
465
466 set_mmc0_io();
467 return 0;
468 }
469
470 #define MMC_BLOCK_SIZE 512
471 #define MMC_DMA_MAX_BUFFER_SIZE (512 * 8)
472
473 #ifdef EMMC_READ_EXT_CSD
mmc0_read_ext_csd(unsigned int dst_start)474 static int mmc0_read_ext_csd(unsigned int dst_start)
475 {
476 unsigned int blk_cnt, bytes, desc_num, buf[4], data;
477 struct idmac_desc *desc = NULL;
478 int i, ret, last_idx;
479 uintptr_t src_addr, dst_addr = dst_start;
480
481 blk_cnt = 1;
482 bytes = blk_cnt * MMC_BLOCK_SIZE;
483 memset((void *)MMC_DATA_BASE, 0, bytes);
484
485 mmio_write_32(MMC0_BYTCNT, bytes);
486
487 mmio_write_32(MMC0_RINTSTS, ~0);
488
489 desc_num = (bytes + MMC_DMA_MAX_BUFFER_SIZE - 1) /
490 MMC_DMA_MAX_BUFFER_SIZE;
491
492 desc = (struct idmac_desc *)MMC_DESC_BASE;
493
494 for (i = 0; i < desc_num; i++) {
495 (desc + i)->des0 = IDMAC_DES0_OWN | IDMAC_DES0_CH |
496 IDMAC_DES0_DIC;
497 (desc + i)->des1 = IDMAC_DES1_BS1(MMC_DMA_MAX_BUFFER_SIZE);
498 /* buffer address */
499 (desc + i)->des2 = MMC_DATA_BASE + MMC_DMA_MAX_BUFFER_SIZE * i;
500 /* next descriptor address */
501 (desc + i)->des3 = MMC_DESC_BASE +
502 (sizeof(struct idmac_desc) * (i + 1));
503 }
504 /* first descriptor */
505 desc->des0 |= IDMAC_DES0_FS;
506 /* last descriptor */
507 last_idx = desc_num - 1;
508 (desc + last_idx)->des0 |= IDMAC_DES0_LD;
509 (desc + last_idx)->des0 &= ~(IDMAC_DES0_DIC | IDMAC_DES0_CH);
510 (desc + last_idx)->des1 = IDMAC_DES1_BS1(bytes - (last_idx *
511 MMC_DMA_MAX_BUFFER_SIZE));
512 /* set next descriptor address as 0 */
513 (desc + last_idx)->des3 = 0;
514
515 mmio_write_32(MMC0_DBADDR, MMC_DESC_BASE);
516
517 /* read extended CSD */
518 ret = mmc0_send_cmd(8, EMMC_FIX_RCA << 16, buf);
519 if (ret) {
520 NOTICE("failed to send CMD8\n");
521 mmio_write_32(MMC0_RINTSTS, ~0);
522 return -EFAULT;
523 }
524
525 ret = wait_data_ready();
526 if (ret)
527 return ret;
528
529 if (blk_cnt > 1) {
530 ret = mmc0_send_cmd(12, EMMC_FIX_RCA << 16, buf);
531 if (ret) {
532 NOTICE("failed to send Stop Transmission command\n");
533 return ret;
534 }
535 mmio_write_32(MMC0_RINTSTS, ~0);
536 }
537 src_addr = MMC_DATA_BASE;
538 memcpy((void *)dst_addr, (void *)src_addr, MMC_BLOCK_SIZE);
539
540 return 0;
541 }
542 #endif
543
mmc0_read(unsigned long src_start,size_t src_size,unsigned long dst_start,uint32_t boot_partition)544 int mmc0_read(unsigned long src_start, size_t src_size,
545 unsigned long dst_start, uint32_t boot_partition)
546 {
547 unsigned int src_blk_start = src_start / MMC_BLOCK_SIZE;
548 unsigned int src_blk_cnt, offset, bytes, desc_num, buf[4];
549 struct idmac_desc *desc = NULL;
550 int i, ret, last_idx;
551 uintptr_t src_addr, dst_addr = dst_start;
552
553 if (boot_partition) {
554 /* switch to boot partition 1 */
555 ret = mmc0_update_ext_csd(EXT_CSD_PARTITION_CONFIG,
556 PART_CFG_BOOT_PARTITION1_ENABLE |
557 PART_CFG_PARTITION1_ACCESS);
558 if (ret) {
559 NOTICE("fail to switch eMMC boot partition\n");
560 return ret;
561 }
562 }
563 offset = src_start % MMC_BLOCK_SIZE;
564 src_blk_cnt = (src_size + offset + MMC_BLOCK_SIZE - 1) / MMC_BLOCK_SIZE;
565 bytes = src_blk_cnt * MMC_BLOCK_SIZE;
566
567 mmio_write_32(MMC0_BYTCNT, bytes);
568
569 mmio_write_32(MMC0_RINTSTS, ~0);
570
571 desc_num = (bytes + MMC_DMA_MAX_BUFFER_SIZE - 1) /
572 MMC_DMA_MAX_BUFFER_SIZE;
573
574 desc = (struct idmac_desc *)MMC_DESC_BASE;
575
576 for (i = 0; i < desc_num; i++) {
577 (desc + i)->des0 = IDMAC_DES0_OWN | IDMAC_DES0_CH |
578 IDMAC_DES0_DIC;
579 (desc + i)->des1 = IDMAC_DES1_BS1(MMC_DMA_MAX_BUFFER_SIZE);
580 /* buffer address */
581 (desc + i)->des2 = MMC_DATA_BASE + MMC_DMA_MAX_BUFFER_SIZE * i;
582 /* next descriptor address */
583 (desc + i)->des3 = MMC_DESC_BASE +
584 (sizeof(struct idmac_desc) * (i + 1));
585 }
586 /* first descriptor */
587 desc->des0 |= IDMAC_DES0_FS;
588 /* last descriptor */
589 last_idx = desc_num - 1;
590 (desc + last_idx)->des0 |= IDMAC_DES0_LD;
591 (desc + last_idx)->des0 &= ~(IDMAC_DES0_DIC | IDMAC_DES0_CH);
592 (desc + last_idx)->des1 = IDMAC_DES1_BS1(bytes - (last_idx *
593 MMC_DMA_MAX_BUFFER_SIZE));
594 /* set next descriptor address as 0 */
595 (desc + last_idx)->des3 = 0;
596
597 mmio_write_32(MMC0_DBADDR, MMC_DESC_BASE);
598
599 ret = mmc0_send_cmd(23, src_blk_cnt & 0xffff, buf);
600 if (ret) {
601 NOTICE("failed to send CMD23\n");
602 mmio_write_32(MMC0_RINTSTS, ~0);
603 return -EFAULT;
604 }
605 /* multiple read */
606 ret = mmc0_send_cmd(18, src_blk_start, buf);
607 if (ret) {
608 NOTICE("failed to send CMD18\n");
609 mmio_write_32(MMC0_RINTSTS, ~0);
610 return -EFAULT;
611 }
612
613 ret = wait_data_ready();
614 if (ret)
615 return ret;
616
617 src_addr = MMC_DATA_BASE + offset;
618 memcpy((void *)dst_addr, (void *)src_addr, src_size);
619
620 if (boot_partition) {
621 /* switch back to normal partition */
622 ret = mmc0_update_ext_csd(EXT_CSD_PARTITION_CONFIG,
623 PART_CFG_BOOT_PARTITION1_ENABLE);
624 if (ret)
625 NOTICE("fail to switch eMMC normal partition\n");
626 }
627 return ret;
628 }
629
write_multi_blocks(unsigned int lba,unsigned int count,unsigned int buffer,unsigned int boot_partition)630 static int write_multi_blocks(unsigned int lba, unsigned int count,
631 unsigned int buffer, unsigned int boot_partition)
632 {
633 unsigned int bytes, resp_buf[4], desc_num;
634 struct idmac_desc *desc = NULL;
635 int ret, last_idx, i;
636
637 if (buffer % 4) {
638 NOTICE("invalid buffer address:0x%x\n", buffer);
639 return -EINVAL;
640 }
641 if (boot_partition) {
642 /* switch to boot partition 1 */
643 ret = mmc0_update_ext_csd(EXT_CSD_PARTITION_CONFIG,
644 PART_CFG_BOOT_PARTITION1_ENABLE |
645 PART_CFG_PARTITION1_ACCESS);
646 if (ret) {
647 NOTICE("fail to switch eMMC boot partition\n");
648 return ret;
649 }
650 }
651 bytes = MMC_BLOCK_SIZE * count;
652
653 mmio_write_32(MMC0_BYTCNT, bytes);
654 mmio_write_32(MMC0_RINTSTS, ~0);
655
656 desc_num = (bytes + MMC_DMA_MAX_BUFFER_SIZE - 1) /
657 MMC_DMA_MAX_BUFFER_SIZE;
658
659 desc = (struct idmac_desc *)MMC_DESC_BASE;
660
661 for (i = 0; i < desc_num; i++) {
662 (desc + i)->des0 = IDMAC_DES0_OWN | IDMAC_DES0_CH |
663 IDMAC_DES0_DIC;
664 (desc + i)->des1 = IDMAC_DES1_BS1(MMC_DMA_MAX_BUFFER_SIZE);
665 /* buffer address */
666 (desc + i)->des2 = buffer + MMC_DMA_MAX_BUFFER_SIZE * i;
667 /* next descriptor address */
668 (desc + i)->des3 = MMC_DESC_BASE +
669 (sizeof(struct idmac_desc) * (i + 1));
670 }
671 /* first descriptor */
672 desc->des0 |= IDMAC_DES0_FS;
673 /* last descriptor */
674 last_idx = desc_num - 1;
675 (desc + last_idx)->des0 |= IDMAC_DES0_LD;
676 (desc + last_idx)->des0 &= ~(IDMAC_DES0_DIC | IDMAC_DES0_CH);
677 (desc + last_idx)->des1 = IDMAC_DES1_BS1(bytes - (last_idx *
678 MMC_DMA_MAX_BUFFER_SIZE));
679 /* set next descriptor address as 0 */
680 (desc + last_idx)->des3 = 0;
681
682 mmio_write_32(MMC0_DBADDR, MMC_DESC_BASE);
683
684 ret = mmc0_send_cmd(25, lba, resp_buf);
685 if (ret) {
686 NOTICE("failed to send CMD25\n");
687 mmio_write_32(MMC0_RINTSTS, ~0);
688 return -EFAULT;
689 }
690 ret = wait_data_ready();
691 if (ret)
692 return ret;
693
694 ret = mmc0_send_cmd(12, EMMC_FIX_RCA << 16, resp_buf);
695 if (ret) {
696 NOTICE("failed to send CMD12\n");
697 mmio_write_32(MMC0_RINTSTS, ~0);
698 return -EFAULT;
699 }
700
701 do {
702 ret = mmc0_send_cmd(13, EMMC_FIX_RCA << 16, resp_buf);
703 if (ret) {
704 NOTICE("failed to send command 13\n");
705 return ret;
706 }
707 } while (!(resp_buf[0] & MMC_STATUS_READY_FOR_DATA) ||
708 (mmc_state(resp_buf[0] != MMC_STATE_TRAN)));
709
710 if (boot_partition) {
711 /* switch back to normal partition */
712 ret = mmc0_update_ext_csd(EXT_CSD_PARTITION_CONFIG,
713 PART_CFG_BOOT_PARTITION1_ENABLE);
714 if (ret)
715 NOTICE("fail to switch eMMC normal partition\n");
716 }
717 return ret;
718 }
719
mmc0_write(unsigned long mmc_start,size_t size,unsigned long buffer,uint32_t boot_partition)720 int mmc0_write(unsigned long mmc_start, size_t size,
721 unsigned long buffer, uint32_t boot_partition)
722 {
723 unsigned int mmc_blk_start = mmc_start / MMC_BLOCK_SIZE;
724 unsigned int mmc_blk_cnt, offset;
725
726 offset = mmc_start % MMC_BLOCK_SIZE;
727 mmc_blk_cnt = (size + offset + MMC_BLOCK_SIZE - 1) / MMC_BLOCK_SIZE;
728
729 return write_multi_blocks(mmc_blk_start, mmc_blk_cnt, buffer,
730 boot_partition);
731 }
732
init_mmc(void)733 int init_mmc(void)
734 {
735 int ret;
736
737 enable_mmc0();
738
739 ret = enum_mmc0_card();
740 if (ret)
741 return ret;
742
743 /* set boot mode to 8-bit */
744 mmc0_update_ext_csd(177, 2);
745 /* response to RESET signal */
746 mmc0_update_ext_csd(162, 1);
747 /* set access userdata area */
748 mmc0_update_ext_csd(EXT_CSD_PARTITION_CONFIG,
749 PART_CFG_BOOT_PARTITION1_ENABLE);
750
751 mmio_write_32(MMC0_RINTSTS, ~0);
752
753 return 0;
754 }
755