1 /*
2 * Copyright (c) 2014-2015, Linaro Ltd and Contributors. All rights reserved.
3 * Copyright (c) 2014-2015, Hisilicon Ltd and Contributors. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * Neither the name of ARM nor the names of its contributors may be used
16 * to endorse or promote products derived from this software without specific
17 * prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <assert.h>
33 #include <ctype.h>
34 #include <debug.h>
35 #include <gpio.h>
36 #include <hi6220.h>
37 #include <mmio.h>
38 #include <partitions.h>
39 #include <platform_def.h>
40 #include <sp804_timer.h>
41 #include <string.h>
42 #include <usb.h>
43 #include "hikey_private.h"
44 #include <bl_common.h>
45
46 #define NUM_ENDPOINTS 16
47
48 #define USB_BLOCK_HIGH_SPEED_SIZE 512
49
50 #define VERSION_BOOTLOADER "0.4"
51
52 struct ep_type {
53 unsigned char active;
54 unsigned char busy;
55 unsigned char done;
56 unsigned int rc;
57 unsigned int size;
58 };
59
60 struct usb_endpoint {
61 struct usb_endpoint *next;
62 unsigned int maxpkt;
63 struct usb_request *req;
64 unsigned char num;
65 unsigned char in;
66 };
67
68 struct usb_config_bundle {
69 struct usb_config_descriptor config;
70 struct usb_interface_descriptor interface;
71 struct usb_endpoint_descriptor ep1;
72 struct usb_endpoint_descriptor ep2;
73 } __attribute__ ((packed));
74
75 static setup_packet ctrl_req[NUM_ENDPOINTS]
76 __attribute__ ((section("tzfw_coherent_mem")));
77 static unsigned char ctrl_resp[2]
78 __attribute__ ((section("tzfw_coherent_mem")));
79
80 static struct ep_type endpoints[NUM_ENDPOINTS]
81 __attribute__ ((section("tzfw_coherent_mem")));
82
83 dwc_otg_dev_dma_desc_t dma_desc
84 __attribute__ ((section("tzfw_coherent_mem")));
85 dwc_otg_dev_dma_desc_t dma_desc_ep0
86 __attribute__ ((section("tzfw_coherent_mem")));
87 dwc_otg_dev_dma_desc_t dma_desc_in
88 __attribute__ ((section("tzfw_coherent_mem")));
89 dwc_otg_dev_dma_desc_t dma_desc_addr
90 __attribute__ ((section("tzfw_coherent_mem")));
91
92 static struct usb_config_bundle config_bundle
93 __attribute__ ((section("tzfw_coherent_mem")));
94 static struct usb_device_descriptor device_descriptor
95 __attribute__ ((section("tzfw_coherent_mem")));
96
97 static struct usb_request rx_req
98 __attribute__ ((section("tzfw_coherent_mem")));
99 static struct usb_request tx_req
100 __attribute__ ((section("tzfw_coherent_mem")));
101
102 static struct usb_string_descriptor serial_string
103 __attribute__ ((section("tzfw_coherent_mem")));
104
105 static const struct usb_string_descriptor string_devicename = {
106 24,
107 USB_DT_STRING,
108 {'A', 'n', 'd', 'r', 'o', 'i', 'd', ' ', '2', '.', '0'}
109 };
110
111 static const struct usb_string_descriptor serial_string_descriptor = {
112 34,
113 USB_DT_STRING,
114 {'0','1','2','3','4','5','6','7','8','9','A','B','C','D','E','F'}
115 };
116
117 static const struct usb_string_descriptor lang_descriptor = {
118 4,
119 USB_DT_STRING,
120 {0x0409} /* en-US */
121 };
122
123 static void usb_rx_cmd_complete(unsigned actual, int stat);
124 static void usb_rx_data_complete(unsigned actual, int status);
125
126 static unsigned int rx_desc_bytes = 0;
127 static unsigned long rx_addr;
128 static unsigned long rx_length;
129 static unsigned int last_one = 0;
130 static char *cmdbuf;
131 static struct usb_endpoint ep1in, ep1out;
132 static int g_usb_enum_flag = 0;
133
134 int usb_need_reset = 0;
135
usb_drv_port_speed(void)136 static int usb_drv_port_speed(void)
137 {
138 /* 2'b00 High speed (PHY clock is at 30MHz or 60MHz) */
139 return (mmio_read_32(DSTS) & 2) == 0 ? 1 : 0;
140 }
141
reset_endpoints(void)142 static void reset_endpoints(void)
143 {
144 int i;
145 unsigned int data;
146
147 INFO("enter reset_endpoints.\n");
148 for (i = 0; i < NUM_ENDPOINTS; i++) {
149 endpoints[i].active = 0;
150 endpoints[i].busy = 0;
151 endpoints[i].rc = -1;
152 endpoints[i].done = 1;
153 }
154
155 /* EP0 IN ACTIVE NEXT=1 */
156 mmio_write_32(DIEPCTL0, 0x8800);
157
158 /* EP0 OUT ACTIVE */
159 mmio_write_32(DOEPCTL0, 0x8000);
160
161 /* Clear any pending OTG Interrupts */
162 mmio_write_32(GOTGINT, ~0);
163
164 /* Clear any pending interrupts */
165 mmio_write_32(GINTSTS, ~0);
166 mmio_write_32(DIEPINT0, ~0);
167 mmio_write_32(DOEPINT0, ~0);
168 mmio_write_32(DIEPINT1, ~0);
169 mmio_write_32(DOEPINT1, ~0);
170
171 /* IN EP interrupt mask */
172 mmio_write_32(DIEPMSK, 0x0D);
173 /* OUT EP interrupt mask */
174 mmio_write_32(DOEPMSK, 0x0D);
175 /* Enable interrupts on Ep0 */
176 mmio_write_32(DAINTMSK, 0x00010001);
177
178 /* EP0 OUT Transfer Size:64 Bytes, 1 Packet, 3 Setup Packet, Read to receive setup packet*/
179 data = DOEPTSIZ0_SUPCNT(3) | DOEPTSIZ0_PKTCNT |
180 (64 << DOEPTSIZ0_XFERSIZE_SHIFT);
181 mmio_write_32(DOEPTSIZ0, data);
182 //notes that:the compulsive conversion is expectable.
183 dma_desc_ep0.status.b.bs = 0x3;
184 dma_desc_ep0.status.b.mtrf = 0;
185 dma_desc_ep0.status.b.sr = 0;
186 dma_desc_ep0.status.b.l = 1;
187 dma_desc_ep0.status.b.ioc = 1;
188 dma_desc_ep0.status.b.sp = 0;
189 dma_desc_ep0.status.b.bytes = 64;
190 dma_desc_ep0.buf = (unsigned long)&ctrl_req;
191 dma_desc_ep0.status.b.sts = 0;
192 dma_desc_ep0.status.b.bs = 0x0;
193 mmio_write_32(DOEPDMA0, ((unsigned long)&(dma_desc_ep0)));
194 VERBOSE("%s, &ctrl_req:%llx:%x, &dms_desc_ep0:%llx:%x\n",
195 __func__, (unsigned long)&ctrl_req, (unsigned long)&ctrl_req,
196 (unsigned long)&dma_desc_ep0, (unsigned long)&dma_desc_ep0);
197 /* EP0 OUT ENABLE CLEARNAK */
198 data = mmio_read_32(DOEPCTL0);
199 mmio_write_32(DOEPCTL0, (data | 0x84000000));
200
201 VERBOSE("exit reset_endpoints. \n");
202 }
203
usb_drv_request_endpoint(int type,int dir)204 static int usb_drv_request_endpoint(int type, int dir)
205 {
206 int ep = 1; /*FIXME*/
207 unsigned int newbits, data;
208
209 newbits = (type << 18) | 0x10000000;
210
211 /*
212 * (type << 18):Endpoint Type (EPType)
213 * 0x10000000:Endpoint Enable (EPEna)
214 * 0x000C000:Endpoint Type (EPType);Hardcoded to 00 for control.
215 * (ep<<22):TxFIFO Number (TxFNum)
216 * 0x20000:NAK Status (NAKSts);The core is transmitting NAK handshakes on this endpoint.
217 */
218 if (dir) { // IN: to host
219 data = mmio_read_32(DIEPCTL(ep));
220 data &= ~0x000c0000;
221 data |= newbits | (ep << 22) | 0x20000;
222 mmio_write_32(DIEPCTL(ep), data);
223 } else { // OUT: to device
224 data = mmio_read_32(DOEPCTL(ep));
225 data &= ~0x000c0000;
226 data |= newbits;
227 mmio_write_32(DOEPCTL(ep), data);
228 }
229 endpoints[ep].active = 1; // true
230
231 return ep | dir;
232 }
233
usb_drv_release_endpoint(int ep)234 void usb_drv_release_endpoint(int ep)
235 {
236 ep = ep % NUM_ENDPOINTS;
237 if (ep < 1 || ep > NUM_ENDPOINTS)
238 return;
239
240 endpoints[ep].active = 0;
241 }
242
usb_config(void)243 void usb_config(void)
244 {
245 unsigned int data;
246
247 INFO("enter usb_config\n");
248
249 mmio_write_32(GDFIFOCFG, DATA_FIFO_CONFIG);
250 mmio_write_32(GRXFSIZ, RX_SIZE);
251 mmio_write_32(GNPTXFSIZ, ENDPOINT_TX_SIZE);
252
253 mmio_write_32(DIEPTXF1, DATA_IN_ENDPOINT_TX_FIFO1);
254 mmio_write_32(DIEPTXF2, DATA_IN_ENDPOINT_TX_FIFO2);
255 mmio_write_32(DIEPTXF3, DATA_IN_ENDPOINT_TX_FIFO3);
256 mmio_write_32(DIEPTXF4, DATA_IN_ENDPOINT_TX_FIFO4);
257 mmio_write_32(DIEPTXF5, DATA_IN_ENDPOINT_TX_FIFO5);
258 mmio_write_32(DIEPTXF6, DATA_IN_ENDPOINT_TX_FIFO6);
259 mmio_write_32(DIEPTXF7, DATA_IN_ENDPOINT_TX_FIFO7);
260 mmio_write_32(DIEPTXF8, DATA_IN_ENDPOINT_TX_FIFO8);
261 mmio_write_32(DIEPTXF9, DATA_IN_ENDPOINT_TX_FIFO9);
262 mmio_write_32(DIEPTXF10, DATA_IN_ENDPOINT_TX_FIFO10);
263 mmio_write_32(DIEPTXF11, DATA_IN_ENDPOINT_TX_FIFO11);
264 mmio_write_32(DIEPTXF12, DATA_IN_ENDPOINT_TX_FIFO12);
265 mmio_write_32(DIEPTXF13, DATA_IN_ENDPOINT_TX_FIFO13);
266 mmio_write_32(DIEPTXF14, DATA_IN_ENDPOINT_TX_FIFO14);
267 mmio_write_32(DIEPTXF15, DATA_IN_ENDPOINT_TX_FIFO15);
268
269 /*Init global csr register.*/
270
271 /*
272 * set Periodic TxFIFO Empty Level,
273 * Non-Periodic TxFIFO Empty Level,
274 * Enable DMA, Unmask Global Intr
275 */
276 INFO("USB: DMA mode.\n");
277 mmio_write_32(GAHBCFG, GAHBCFG_CTRL_MASK);
278
279 /*select 8bit UTMI+, ULPI Inerface*/
280 INFO("USB ULPI PHY\n");
281 mmio_write_32(GUSBCFG, 0x2400);
282
283 /* Detect usb work mode,host or device? */
284 do {
285 data = mmio_read_32(GINTSTS);
286 } while (data & GINTSTS_CURMODE_HOST);
287 VERBOSE("Enter device mode\n");
288 udelay(3);
289
290 /*Init global and device mode csr register.*/
291 /*set Non-Zero-Length status out handshake */
292 data = (0x20 << DCFG_EPMISCNT_SHIFT) | DCFG_NZ_STS_OUT_HSHK;
293 mmio_write_32(DCFG, data);
294
295 /* Interrupt unmask: IN event, OUT event, bus reset */
296 data = GINTSTS_OEPINT | GINTSTS_IEPINT | GINTSTS_ENUMDONE |
297 GINTSTS_USBRST | GINTSTS_USBSUSP | GINTSTS_ERLYSUSP |
298 GINTSTS_GOUTNAKEFF;
299 mmio_write_32(GINTMSK, data);
300
301 do {
302 data = mmio_read_32(GINTSTS) & GINTSTS_ENUMDONE;
303 } while (data);
304 VERBOSE("USB Enum Done.\n");
305
306 /* Clear any pending OTG Interrupts */
307 mmio_write_32(GOTGINT, ~0);
308 /* Clear any pending interrupts */
309 mmio_write_32(GINTSTS, ~0);
310 mmio_write_32(GINTMSK, ~0);
311 data = mmio_read_32(GOTGINT);
312 data &= ~0x3000;
313 mmio_write_32(GOTGINT, data);
314 /*endpoint settings cfg*/
315 reset_endpoints();
316
317 udelay(1);
318
319 /*init finish. and ready to transfer data*/
320
321 /* Soft Disconnect */
322 mmio_write_32(DCTL, 0x802);
323 udelay(10000);
324
325 /* Soft Reconnect */
326 mmio_write_32(DCTL, 0x800);
327 VERBOSE("exit usb_config.\n");
328 }
329
usb_drv_set_address(int address)330 void usb_drv_set_address(int address)
331 {
332 unsigned int cfg;
333
334 cfg = mmio_read_32(DCFG);
335 cfg &= ~0x7F0;
336 cfg |= address << 4;
337 mmio_write_32(DCFG, cfg); // 0x7F0: device address
338 }
339
ep_send(int ep,const void * ptr,int len)340 static void ep_send(int ep, const void *ptr, int len)
341 {
342 unsigned int data;
343
344 endpoints[ep].busy = 1; // true
345 endpoints[ep].size = len;
346
347 /* EPx OUT ACTIVE */
348 data = mmio_read_32(DIEPCTL(ep)) | DXEPCTL_USBACTEP;
349 mmio_write_32(DIEPCTL(ep), data);
350
351 /* set DMA Address */
352 if (!len) {
353 /* send one empty packet */
354 dma_desc_in.buf = 0;
355 } else {
356 dma_desc_in.buf = (unsigned long)ptr;
357 }
358 dma_desc_in.status.b.bs = 0x3;
359 dma_desc_in.status.b.l = 1;
360 dma_desc_in.status.b.ioc = 1;
361 dma_desc_in.status.b.sp = 1;
362 dma_desc_in.status.b.sts = 0;
363 dma_desc_in.status.b.bs = 0x0;
364 dma_desc_in.status.b.bytes = len;
365 mmio_write_32(DIEPDMA(ep), (unsigned long)&dma_desc_in);
366
367 data = mmio_read_32(DIEPCTL(ep));
368 data |= DXEPCTL_EPENA | DXEPCTL_CNAK | DXEPCTL_NEXTEP(ep + 1);
369 mmio_write_32(DIEPCTL(ep), data);
370 }
371
usb_drv_stall(int endpoint,char stall,char in)372 void usb_drv_stall(int endpoint, char stall, char in)
373 {
374 unsigned int data;
375
376 /*
377 * STALL Handshake (Stall)
378 */
379
380 data = mmio_read_32(DIEPCTL(endpoint));
381 if (in) {
382 if (stall)
383 mmio_write_32(DIEPCTL(endpoint), data | 0x00200000);
384 else
385 mmio_write_32(DIEPCTL(endpoint), data & ~0x00200000);
386 } else {
387 if (stall)
388 mmio_write_32(DOEPCTL(endpoint), data | 0x00200000);
389 else
390 mmio_write_32(DOEPCTL(endpoint), data & ~0x00200000);
391 }
392 }
393
usb_drv_send_nonblocking(int endpoint,const void * ptr,int len)394 int usb_drv_send_nonblocking(int endpoint, const void *ptr, int len)
395 {
396 VERBOSE("%s, endpoint = %d, ptr = 0x%x, Len=%d.\n",
397 __func__, endpoint, ptr, len);
398 ep_send(endpoint % NUM_ENDPOINTS, ptr, len);
399 return 0;
400 }
401
usb_drv_cancel_all_transfers(void)402 void usb_drv_cancel_all_transfers(void)
403 {
404 reset_endpoints();
405 }
406
hiusb_epx_tx(unsigned ep,void * buf,unsigned len)407 int hiusb_epx_tx(unsigned ep, void *buf, unsigned len)
408 {
409 int blocksize,packets;
410 unsigned int epints;
411 unsigned int cycle = 0;
412 unsigned int data;
413
414 endpoints[ep].busy = 1; //true
415 endpoints[ep].size = len;
416
417 while (mmio_read_32(GINTSTS) & 0x40) {
418 data = mmio_read_32(DCTL);
419 data |= 0x100;
420 mmio_write_32(DCTL, data);
421 }
422
423 data = mmio_read_32(DIEPCTL(ep));
424 data |= 0x08000000;
425 mmio_write_32(DIEPCTL(ep), data);
426
427 /* EPx OUT ACTIVE */
428 mmio_write_32(DIEPCTL(ep), data | 0x8000);
429 if (!ep) {
430 blocksize = 64;
431 } else {
432 blocksize = usb_drv_port_speed() ? USB_BLOCK_HIGH_SPEED_SIZE : 64;
433 }
434 packets = (len + blocksize - 1) / blocksize;
435
436 if (!len) {
437 /* one empty packet */
438 mmio_write_32(DIEPTSIZ(ep), 1 << 19);
439 /* NULL */
440 dma_desc_in.status.b.bs = 0x3;
441 dma_desc_in.status.b.l = 1;
442 dma_desc_in.status.b.ioc = 1;
443 dma_desc_in.status.b.sp = last_one;
444 dma_desc_in.status.b.bytes = 0;
445 dma_desc_in.buf = 0;
446 dma_desc_in.status.b.sts = 0;
447 dma_desc_in.status.b.bs = 0x0;
448 mmio_write_32(DIEPDMA(ep), (unsigned long)&dma_desc_in);
449 } else {
450 mmio_write_32(DIEPTSIZ(ep), len | (packets << 19));
451 dma_desc_in.status.b.bs = 0x3;
452 dma_desc_in.status.b.l = 1;
453 dma_desc_in.status.b.ioc = 1;
454 dma_desc_in.status.b.sp = last_one;
455 dma_desc_in.status.b.bytes = len;
456 dma_desc_in.buf = (unsigned long)buf;
457 dma_desc_in.status.b.sts = 0;
458 dma_desc_in.status.b.bs = 0x0;
459 mmio_write_32(DIEPDMA(ep), (unsigned long)&dma_desc_in);
460 }
461
462 cycle = 0;
463 while(1){
464 data = mmio_read_32(DIEPINT(ep));
465 if ((data & 0x2000) || (cycle > 10000)) {
466 if (cycle > 10000) {
467 NOTICE("Phase 2:ep(%d) status, DIEPCTL(%d) is [0x%x],"
468 "DTXFSTS(%d) is [0x%x], DIEPINT(%d) is [0x%x],"
469 "DIEPTSIZ(%d) is [0x%x] GINTSTS is [0x%x]\n",
470 ep, ep, data,
471 ep, mmio_read_32(DTXFSTS(ep)),
472 ep, mmio_read_32(DIEPINT(ep)),
473 ep, mmio_read_32(DIEPTSIZ(ep)),
474 mmio_read_32(GINTSTS));
475 }
476 break;
477 }
478
479 cycle++;
480 udelay(10);
481 }
482 VERBOSE("ep(%d) enable, DIEPCTL(%d) is [0x%x], DTXFSTS(%d) is [0x%x],"
483 "DIEPINT(%d) is [0x%x], DIEPTSIZ(%d) is [0x%x] \n",
484 ep, ep, mmio_read_32(DIEPCTL(ep)),
485 ep, mmio_read_32(DTXFSTS(ep)),
486 ep, mmio_read_32(DIEPINT(ep)),
487 ep, mmio_read_32(DIEPTSIZ(ep)));
488
489 __asm__ volatile("dsb sy\n"
490 "isb sy\n");
491 data = mmio_read_32(DIEPCTL(ep));
492 data |= 0x84000000;
493 /* epena & cnak*/
494 mmio_write_32(DIEPCTL(ep), data);
495 __asm__ volatile("dsb sy\n"
496 "isb sy\n");
497
498 cycle = 0;
499 while (1) {
500 epints = mmio_read_32(DIEPINT(ep)) & 1;
501 if ((mmio_read_32(GINTSTS) & 0x40000) && epints) {
502 VERBOSE("Tx succ:ep(%d), DTXFSTS(%d) is [0x%x] \n",
503 ep, ep, mmio_read_32(DTXFSTS(ep)));
504 mmio_write_32(DIEPINT(ep), epints);
505 if (endpoints[ep].busy) {
506 endpoints[ep].busy = 0;//false
507 endpoints[ep].rc = 0;
508 endpoints[ep].done = 1;//true
509 }
510 break;
511 }
512 cycle++;
513 udelay(10);
514 VERBOSE("loop for intr: ep(%d), DIEPCTL(%d) is [0x%x], ",
515 "DTXFSTS(%d) is [0x%x], DIEPINT(%d) is [0x%x] \n",
516 ep, ep, mmio_read_32(DIEPCTL(ep)),
517 ep, mmio_read_32(DTXFSTS(ep)),
518 ep, mmio_read_32(DIEPINT(ep)));
519
520 if (cycle > 1000000) {
521 WARN("Wait IOC intr over 10s! USB will reset\n");
522 usb_need_reset = 1;
523 return 1;
524 }
525 }
526
527 cycle = 0;
528 while (1) {
529 if ((mmio_read_32(DIEPINT(ep)) & 0x2000) || (cycle > 100000)) {
530 if (cycle > 100000){
531 WARN("all wait cycle is [%d]\n",cycle);
532 }
533 break;
534 }
535
536 cycle++;
537 udelay(10);
538 }
539
540 return 0;
541 }
542
hiusb_epx_rx(unsigned ep,void * buf,unsigned len)543 int hiusb_epx_rx(unsigned ep, void *buf, unsigned len)
544 {
545 unsigned int blocksize = 0, data;
546 int packets;
547
548 VERBOSE("ep%d rx, len = 0x%x, buf = 0x%x.\n", ep, len, buf);
549
550 endpoints[ep].busy = 1;//true
551 /* EPx UNSTALL */
552 data = mmio_read_32(DOEPCTL(ep)) & ~0x00200000;
553 mmio_write_32(DOEPCTL(ep), data);
554 /* EPx OUT ACTIVE */
555 data = mmio_read_32(DOEPCTL(ep)) | 0x8000;
556 mmio_write_32(DOEPCTL(ep), data);
557
558 blocksize = usb_drv_port_speed() ? USB_BLOCK_HIGH_SPEED_SIZE : 64;
559 packets = (len + blocksize - 1) / blocksize;
560
561 #define MAX_RX_PACKET 0x3FF
562
563 /*Max recv packets is 1023*/
564 if (packets > MAX_RX_PACKET) {
565 endpoints[ep].size = MAX_RX_PACKET * blocksize;
566 len = MAX_RX_PACKET * blocksize;
567 } else {
568 endpoints[ep].size = len;
569 }
570
571 if (!len) {
572 /* one empty packet */
573 mmio_write_32(DOEPTSIZ(ep), 1 << 19);
574 //NULL /* dummy address */
575 dma_desc.status.b.bs = 0x3;
576 dma_desc.status.b.mtrf = 0;
577 dma_desc.status.b.sr = 0;
578 dma_desc.status.b.l = 1;
579 dma_desc.status.b.ioc = 1;
580 dma_desc.status.b.sp = 0;
581 dma_desc.status.b.bytes = 0;
582 dma_desc.buf = 0;
583 dma_desc.status.b.sts = 0;
584 dma_desc.status.b.bs = 0x0;
585
586 mmio_write_32(DOEPDMA(ep), (unsigned long)&dma_desc);
587 } else {
588 if (len >= blocksize * 64) {
589 rx_desc_bytes = blocksize*64;
590 } else {
591 rx_desc_bytes = len;
592 }
593 VERBOSE("rx len %d, rx_desc_bytes %d \n",len,rx_desc_bytes);
594 dma_desc.status.b.bs = 0x3;
595 dma_desc.status.b.mtrf = 0;
596 dma_desc.status.b.sr = 0;
597 dma_desc.status.b.l = 1;
598 dma_desc.status.b.ioc = 1;
599 dma_desc.status.b.sp = 0;
600 dma_desc.status.b.bytes = rx_desc_bytes;
601 dma_desc.buf = (unsigned long)buf;
602 dma_desc.status.b.sts = 0;
603 dma_desc.status.b.bs = 0x0;
604
605 mmio_write_32(DOEPDMA(ep), (unsigned long)&dma_desc);
606 }
607 /* EPx OUT ENABLE CLEARNAK */
608 data = mmio_read_32(DOEPCTL(ep));
609 data |= 0x84000000;
610 mmio_write_32(DOEPCTL(ep), data);
611 return 0;
612 }
613
usb_queue_req(struct usb_endpoint * ept,struct usb_request * req)614 int usb_queue_req(struct usb_endpoint *ept, struct usb_request *req)
615 {
616 if (ept->in)
617 hiusb_epx_tx(ept->num, req->buf, req->length);
618 else
619 hiusb_epx_rx(ept->num, req->buf, req->length);
620
621 return 0;
622 }
623
rx_cmd(void)624 static void rx_cmd(void)
625 {
626 struct usb_request *req = &rx_req;
627 req->buf = cmdbuf;
628 req->length = RX_REQ_LEN;
629 req->complete = usb_rx_cmd_complete;
630 usb_queue_req(&ep1out, req);
631 }
632
rx_data(void)633 static void rx_data(void)
634 {
635 struct usb_request *req = &rx_req;
636
637 req->buf = (void *)((unsigned long) rx_addr);
638 req->length = rx_length;
639 req->complete = usb_rx_data_complete;
640 usb_queue_req(&ep1out, req);
641 }
642
tx_status(const char * status)643 void tx_status(const char *status)
644 {
645 struct usb_request *req = &tx_req;
646 int len = strlen(status);
647
648 memcpy(req->buf, status, (unsigned int)len);
649 req->length = (unsigned int)len;
650 req->complete = 0;
651 usb_queue_req(&ep1in, req);
652 }
653
fastboot_tx_status(const char * status)654 void fastboot_tx_status(const char *status)
655 {
656 tx_status(status);
657 rx_cmd();
658 }
659
tx_dump_page(const char * ptr,int len)660 void tx_dump_page(const char *ptr, int len)
661 {
662 struct usb_request *req = &tx_req;
663
664 memcpy(req->buf, ptr, (unsigned int)len);
665 req->length = (unsigned int)len;
666 req->complete = 0;
667 usb_queue_req(&ep1in, req);
668 }
669
670
usb_rx_data_complete(unsigned actual,int status)671 static void usb_rx_data_complete(unsigned actual, int status)
672 {
673
674 if(status != 0)
675 return;
676
677 if(actual > rx_length) {
678 actual = rx_length;
679 }
680
681 rx_addr += actual;
682 rx_length -= actual;
683
684 if(rx_length > 0) {
685 rx_data();
686 } else {
687 tx_status("OKAY");
688 rx_cmd();
689 }
690 }
691
usb_status(unsigned online,unsigned highspeed)692 static void usb_status(unsigned online, unsigned highspeed)
693 {
694 if (online) {
695 INFO("usb: online (%s)\n", highspeed ? "highspeed" : "fullspeed");
696 rx_cmd();
697 }
698 }
699
usb_handle_control_request(setup_packet * req)700 void usb_handle_control_request(setup_packet* req)
701 {
702 const void* addr = NULL;
703 int size = -1;
704 int i;
705 int maxpacket;
706 unsigned int data;
707 char *serialno;
708 struct usb_endpoint_descriptor epx;
709 struct usb_config_bundle const_bundle = {
710 .config = {
711 .bLength = sizeof(struct usb_config_descriptor),
712 .bDescriptorType = USB_DT_CONFIG,
713 .wTotalLength = sizeof(struct usb_config_descriptor) +
714 sizeof(struct usb_interface_descriptor) +
715 sizeof(struct usb_endpoint_descriptor) *
716 USB_NUM_ENDPOINTS,
717 .bNumInterfaces = 1,
718 .bConfigurationValue = 1,
719 .iConfiguration = 0,
720 .bmAttributes = USB_CONFIG_ATT_ONE,
721 .bMaxPower = 0x80
722 },
723 .interface = {
724 .bLength = sizeof(struct usb_interface_descriptor),
725 .bDescriptorType = USB_DT_INTERFACE,
726 .bInterfaceNumber = 0,
727 .bAlternateSetting = 0,
728 .bNumEndpoints = USB_NUM_ENDPOINTS,
729 .bInterfaceClass = USB_CLASS_VENDOR_SPEC,
730 .bInterfaceSubClass = 0x42,
731 .bInterfaceProtocol = 0x03,
732 .iInterface = 0
733 }
734 };
735
736 /* avoid to hang on accessing unaligned memory */
737 struct usb_endpoint_descriptor const_ep1 = {
738 .bLength = sizeof(struct usb_endpoint_descriptor),
739 .bDescriptorType = USB_DT_ENDPOINT,
740 .bEndpointAddress = 0x81,
741 .bmAttributes = USB_ENDPOINT_XFER_BULK,
742 .wMaxPacketSize = 0,
743 .bInterval = 0
744 };
745
746 struct usb_endpoint_descriptor const_ep2 = {
747 .bLength = sizeof(struct usb_endpoint_descriptor),
748 .bDescriptorType = USB_DT_ENDPOINT,
749 .bEndpointAddress = 0x01,
750 .bmAttributes = USB_ENDPOINT_XFER_BULK,
751 .wMaxPacketSize = 0,
752 .bInterval = 1
753 };
754
755 struct usb_device_descriptor const_device = {
756 .bLength = sizeof(struct usb_device_descriptor),
757 .bDescriptorType = USB_DT_DEVICE,
758 .bcdUSB = 0x0200,
759 .bDeviceClass = 0,
760 .bDeviceClass = 0,
761 .bDeviceProtocol = 0,
762 .bMaxPacketSize0 = 0x40,
763 .idVendor = 0x18d1,
764 .idProduct = 0xd00d,
765 .bcdDevice = 0x0100,
766 .iManufacturer = 1,
767 .iProduct = 2,
768 .iSerialNumber = 3,
769 .bNumConfigurations = 1
770 };
771
772 memcpy(&config_bundle, &const_bundle, sizeof(struct usb_config_bundle));
773 memcpy(&config_bundle.ep1, &const_ep1, sizeof(struct usb_endpoint_descriptor));
774 memcpy(&config_bundle.ep2, &const_ep2, sizeof(struct usb_endpoint_descriptor));
775 memcpy(&device_descriptor, &const_device,
776 sizeof(struct usb_device_descriptor));
777
778 switch (req->request) {
779 case USB_REQ_GET_STATUS:
780 if (req->type == USB_DIR_IN)
781 ctrl_resp[0] = 1;
782 else
783 ctrl_resp[0] = 0;
784 ctrl_resp[1] = 0;
785 addr = ctrl_resp;
786 size = 2;
787 break;
788
789 case USB_REQ_CLEAR_FEATURE:
790 if ((req->type == USB_RECIP_ENDPOINT) &&
791 (req->value == USB_ENDPOINT_HALT))
792 usb_drv_stall(req->index & 0xf, 0, req->index >> 7);
793 size = 0;
794 break;
795
796 case USB_REQ_SET_FEATURE:
797 size = 0;
798 break;
799
800 case USB_REQ_SET_ADDRESS:
801 size = 0;
802 usb_drv_cancel_all_transfers(); // all endpoints reset
803 usb_drv_set_address(req->value); // set device address
804 break;
805
806 case USB_REQ_GET_DESCRIPTOR:
807 VERBOSE("USB_REQ_GET_DESCRIPTOR: 0x%x\n", req->value >> 8);
808 switch (req->value >> 8) {
809 case USB_DT_DEVICE:
810 addr = &device_descriptor;
811 size = sizeof(device_descriptor);
812 VERBOSE("Get device descriptor.\n");
813 break;
814
815 case USB_DT_OTHER_SPEED_CONFIG:
816 case USB_DT_CONFIG:
817 if ((req->value >> 8) == USB_DT_CONFIG) {
818 maxpacket = usb_drv_port_speed() ? USB_BLOCK_HIGH_SPEED_SIZE : 64;
819 config_bundle.config.bDescriptorType = USB_DT_CONFIG;
820 } else {
821 maxpacket = usb_drv_port_speed() ? 64 : USB_BLOCK_HIGH_SPEED_SIZE;
822 config_bundle.config.bDescriptorType = USB_DT_OTHER_SPEED_CONFIG;
823 }
824 /* avoid hang when access unaligned structure */
825 memcpy(&epx, &config_bundle.ep1, sizeof(struct usb_endpoint_descriptor));
826 epx.wMaxPacketSize = maxpacket;
827 memcpy(&config_bundle.ep1, &epx, sizeof(struct usb_endpoint_descriptor));
828 memcpy(&epx, &config_bundle.ep2, sizeof(struct usb_endpoint_descriptor));
829 epx.wMaxPacketSize = maxpacket;
830 memcpy(&config_bundle.ep2, &epx, sizeof(struct usb_endpoint_descriptor));
831 addr = &config_bundle;
832 size = sizeof(config_bundle);
833 VERBOSE("Get config descriptor.\n");
834 break;
835
836 case USB_DT_STRING:
837 switch (req->value & 0xff) {
838 case 0:
839 addr = &lang_descriptor;
840 size = lang_descriptor.bLength;
841 break;
842 case 1:
843 addr = &string_devicename;
844 size = 14;
845 break;
846 case 2:
847 addr = &string_devicename;
848 size = string_devicename.bLength;
849 break;
850 case 3:
851 serialno = load_serialno();
852 if (serialno == NULL) {
853 addr = &serial_string_descriptor;
854 size = serial_string_descriptor.bLength;
855 } else {
856 i = 0;
857 memcpy((void *)&serial_string,
858 (void *)&serial_string_descriptor,
859 sizeof(serial_string));
860 while (1) {
861 serial_string.wString[i] = serialno[i];
862 if (serialno[i] == '\0')
863 break;
864 i++;
865 }
866 addr = &serial_string;
867 size = serial_string.bLength;
868 }
869 break;
870 default:
871 break;
872 }
873 break;
874
875 default:
876 break;
877 }
878 break;
879
880 case USB_REQ_GET_CONFIGURATION:
881 ctrl_resp[0] = 1;
882 addr = ctrl_resp;
883 size = 1;
884 break;
885
886 case USB_REQ_SET_CONFIGURATION:
887 usb_drv_cancel_all_transfers(); // call reset_endpoints reset all EPs
888
889 usb_drv_request_endpoint(USB_ENDPOINT_XFER_BULK, USB_DIR_OUT);
890 usb_drv_request_endpoint(USB_ENDPOINT_XFER_BULK, USB_DIR_IN);
891 /*
892 * 0x10088800:
893 * 1:EP enable; 8:EP type:BULK; 8:USB Active Endpoint; 8:Next Endpoint
894 */
895 data = mmio_read_32(DIEPCTL1) | 0x10088800;
896 mmio_write_32(DIEPCTL1, data);
897 data = mmio_read_32(DIEPCTL(1)) | 0x08000000;
898 mmio_write_32(DIEPCTL(1), data);
899
900 /* Enable interrupts on all endpoints */
901 mmio_write_32(DAINTMSK, 0xffffffff);
902
903 usb_status(req->value? 1 : 0, usb_drv_port_speed() ? 1 : 0);
904 size = 0;
905 VERBOSE("Set config descriptor.\n");
906
907 /* USB ö�ٳɹ���,���ϱ�ʶ */
908 g_usb_enum_flag = 1;
909 break;
910
911 default:
912 break;
913 }
914
915 if (!size) {
916 usb_drv_send_nonblocking(0, 0, 0); // send an empty packet
917 } else if (size == -1) { // stall:Applies to non-control, non-isochronous IN and OUT endpoints only.
918 usb_drv_stall(0, 1, 1); // IN
919 usb_drv_stall(0, 1, 0); // OUT
920 } else { // stall:Applies to control endpoints only.
921 usb_drv_stall(0, 0, 1); // IN
922 usb_drv_stall(0, 0, 0); // OUT
923
924 usb_drv_send_nonblocking(0, addr, size > req->length ? req->length : size);
925 }
926 }
927
928 /* IRQ handler */
usb_poll(void)929 static void usb_poll(void)
930 {
931 uint32_t ints;
932 uint32_t epints, data;
933
934 ints = mmio_read_32(GINTSTS); /* interrupt status */
935
936
937 if ((ints & 0xc3010) == 0)
938 return;
939 /*
940 * bus reset
941 * The core sets this bit to indicate that a reset is detected on the USB.
942 */
943 if (ints & GINTSTS_USBRST) {
944 VERBOSE("bus reset intr\n");
945 /*set Non-Zero-Length status out handshake */
946 /*
947 * DCFG:This register configures the core in Device mode after power-on
948 * or after certain control commands or enumeration. Do not make changes
949 * to this register after initial programming.
950 * Send a STALL handshake on a nonzero-length status OUT transaction and
951 * do not send the received OUT packet to the application.
952 */
953 mmio_write_32(DCFG, 0x800004);
954 reset_endpoints();
955 }
956 /*
957 * enumeration done, we now know the speed
958 * The core sets this bit to indicate that speed enumeration is complete. The
959 * application must read the Device Status (DSTS) register to obtain the
960 * enumerated speed.
961 */
962 if (ints & GINTSTS_ENUMDONE) {
963 /* Set up the maximum packet sizes accordingly */
964 uint32_t maxpacket = usb_drv_port_speed() ? USB_BLOCK_HIGH_SPEED_SIZE : 64; // high speed maxpacket=512
965 VERBOSE("enum done intr. Maxpacket:%d\n", maxpacket);
966 //Set Maximum In Packet Size (MPS)
967 data = mmio_read_32(DIEPCTL1) & ~0x000003ff;
968 mmio_write_32(DIEPCTL1, data | maxpacket);
969 //Set Maximum Out Packet Size (MPS)
970 data = mmio_read_32(DOEPCTL1) & ~0x000003ff;
971 mmio_write_32(DOEPCTL1, data | maxpacket);
972 }
973
974 /*
975 * IN EP event
976 * The core sets this bit to indicate that an interrupt is pending on one of the IN
977 * endpoints of the core (in Device mode). The application must read the
978 * Device All Endpoints Interrupt (DAINT) register to determine the exact
979 * number of the IN endpoint on which the interrupt occurred, and then read
980 * the corresponding Device IN Endpoint-n Interrupt (DIEPINTn) register to
981 * determine the exact cause of the interrupt. The application must clear the
982 * appropriate status bit in the corresponding DIEPINTn register to clear this bit.
983 */
984 if (ints & GINTSTS_IEPINT) {
985 epints = mmio_read_32(DIEPINT0);
986 mmio_write_32(DIEPINT0, epints);
987
988 //VERBOSE("IN EP event,ints:0x%x, DIEPINT0:%x, DAINT:%x, DAINTMSK:%x.\n",
989 // ints, epints, mmio_read_32(DAINT), mmio_read_32(DAINTMSK));
990 if (epints & 0x1) { /* Transfer Completed Interrupt (XferCompl) */
991 VERBOSE("TX completed.DIEPTSIZ(0) = 0x%x.\n", mmio_read_32(DIEPTSIZ0));
992 /*FIXME,Maybe you can use bytes*/
993 /*int bytes = endpoints[0].size - (DIEPTSIZ(0) & 0x3FFFF);*/ //actual transfer
994 if (endpoints[0].busy) {
995 endpoints[0].busy = 0;//false
996 endpoints[0].rc = 0;
997 endpoints[0].done = 1;//true
998 }
999 }
1000 if (epints & 0x4) { /* AHB error */
1001 WARN("AHB error on IN EP0.\n");
1002 }
1003
1004 if (epints & 0x8) { /* Timeout */
1005 WARN("Timeout on IN EP0.\n");
1006 if (endpoints[0].busy) {
1007 endpoints[0].busy = 1;//false
1008 endpoints[0].rc = 1;
1009 endpoints[0].done = 1;//true
1010 }
1011 }
1012 }
1013
1014 /*
1015 * OUT EP event
1016 * The core sets this bit to indicate that an interrupt is pending on one of the
1017 * OUT endpoints of the core (in Device mode). The application must read the
1018 * Device All Endpoints Interrupt (DAINT) register to determine the exact
1019 * number of the OUT endpoint on which the interrupt occurred, and then read
1020 * the corresponding Device OUT Endpoint-n Interrupt (DOEPINTn) register
1021 * to determine the exact cause of the interrupt. The application must clear the
1022 * appropriate status bit in the corresponding DOEPINTn register to clear this bit.
1023 */
1024 if (ints & GINTSTS_OEPINT) {
1025 /* indicates the status of an endpoint
1026 * with respect to USB- and AHB-related events. */
1027 epints = mmio_read_32(DOEPINT(0));
1028 //VERBOSE("OUT EP event,ints:0x%x, DOEPINT0:%x, DAINT:%x, DAINTMSK:%x.\n",
1029 // ints, epints, mmio_read_32(DAINT), mmio_read_32(DAINTMSK));
1030 if (epints) {
1031 mmio_write_32(DOEPINT(0), epints);
1032 /* Transfer completed */
1033 if (epints & DXEPINT_XFERCOMPL) {
1034 /*FIXME,need use bytes*/
1035 VERBOSE("EP0 RX completed. DOEPTSIZ(0) = 0x%x.\n",
1036 mmio_read_32(DOEPTSIZ(0)));
1037 if (endpoints[0].busy) {
1038 endpoints[0].busy = 0;
1039 endpoints[0].rc = 0;
1040 endpoints[0].done = 1;
1041 }
1042 }
1043 if (epints & DXEPINT_AHBERR) { /* AHB error */
1044 WARN("AHB error on OUT EP0.\n");
1045 }
1046
1047 /*
1048 * IN Token Received When TxFIFO is Empty (INTknTXFEmp)
1049 * Indicates that an IN token was received when the associated TxFIFO (periodic/nonperiodic)
1050 * was empty. This interrupt is asserted on the endpoint for which the IN token
1051 * was received.
1052 */
1053 if (epints & DXEPINT_SETUP) { /* SETUP phase done */
1054 VERBOSE("Setup phase \n");
1055 data = mmio_read_32(DIEPCTL(0)) | DXEPCTL_SNAK;
1056 mmio_write_32(DIEPCTL(0), data);
1057 data = mmio_read_32(DOEPCTL(0)) | DXEPCTL_SNAK;
1058 mmio_write_32(DOEPCTL(0), data);
1059 /*clear IN EP intr*/
1060 mmio_write_32(DIEPINT(0), ~0);
1061 usb_handle_control_request((setup_packet *)&ctrl_req);
1062 }
1063
1064 /* Make sure EP0 OUT is set up to accept the next request */
1065 /* memset(p_ctrlreq, 0, NUM_ENDPOINTS*8); */
1066 data = DOEPTSIZ0_SUPCNT(3) | DOEPTSIZ0_PKTCNT |
1067 (64 << DOEPTSIZ0_XFERSIZE_SHIFT);
1068 mmio_write_32(DOEPTSIZ0, data);
1069 /*
1070 * IN Token Received When TxFIFO is Empty (INTknTXFEmp)
1071 * Indicates that an IN token was received when the associated TxFIFO (periodic/nonperiodic)
1072 * was empty. This interrupt is asserted on the endpoint for which the IN token
1073 * was received.
1074 */
1075 // notes that:the compulsive conversion is expectable.
1076 // Holds the start address of the external memory for storing or fetching endpoint data.
1077 dma_desc_ep0.status.b.bs = 0x3;
1078 dma_desc_ep0.status.b.mtrf = 0;
1079 dma_desc_ep0.status.b.sr = 0;
1080 dma_desc_ep0.status.b.l = 1;
1081 dma_desc_ep0.status.b.ioc = 1;
1082 dma_desc_ep0.status.b.sp = 0;
1083 dma_desc_ep0.status.b.bytes = 64;
1084 dma_desc_ep0.buf = (uintptr_t)&ctrl_req;
1085 dma_desc_ep0.status.b.sts = 0;
1086 dma_desc_ep0.status.b.bs = 0x0;
1087 mmio_write_32(DOEPDMA0, (uintptr_t)&dma_desc_ep0);
1088 // endpoint enable; clear NAK
1089 mmio_write_32(DOEPCTL0, 0x84000000);
1090 }
1091
1092 epints = mmio_read_32(DOEPINT1);
1093 if(epints) {
1094 mmio_write_32(DOEPINT1, epints);
1095 VERBOSE("OUT EP1: epints :0x%x,DOEPTSIZ1 :0x%x.\n",epints, mmio_read_32(DOEPTSIZ1));
1096 /* Transfer Completed Interrupt (XferCompl);Transfer completed */
1097 if (epints & DXEPINT_XFERCOMPL) {
1098 /* ((readl(DOEPTSIZ(1))) & 0x7FFFF is Transfer Size (XferSize) */
1099 /*int bytes = (p_endpoints + 1)->size - ((readl(DOEPTSIZ(1))) & 0x7FFFF);*/
1100 int bytes = rx_desc_bytes - dma_desc.status.b.bytes;
1101 VERBOSE("OUT EP1: recv %d bytes \n",bytes);
1102 if (endpoints[1].busy) {
1103 endpoints[1].busy = 0;
1104 endpoints[1].rc = 0;
1105 endpoints[1].done = 1;
1106 rx_req.complete(bytes, 0);
1107 }
1108 }
1109
1110 if (epints & DXEPINT_AHBERR) { /* AHB error */
1111 WARN("AHB error on OUT EP1.\n");
1112 }
1113 if (epints & DXEPINT_SETUP) { /* SETUP phase done */
1114 WARN("SETUP phase done on OUT EP1.\n");
1115 }
1116 }
1117 }
1118 /* write to clear interrupts */
1119 mmio_write_32(GINTSTS, ints);
1120 }
1121
1122 #define EYE_PATTERN 0x70533483
1123
1124 /*
1125 * pico phy exit siddq, nano phy enter siddq,
1126 * and open the clock of pico phy and dvc,
1127 */
dvc_and_picophy_init_chip(void)1128 static void dvc_and_picophy_init_chip(void)
1129 {
1130 unsigned int data;
1131
1132 /* enable USB clock */
1133 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_USBOTG);
1134 do {
1135 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
1136 } while ((data & PERI_CLK0_USBOTG) == 0);
1137
1138
1139 /* out of reset */
1140 mmio_write_32(PERI_SC_PERIPH_RSTDIS0,
1141 PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
1142 PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K);
1143 do {
1144 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
1145 data &= PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
1146 PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K;
1147 } while (data);
1148
1149 mmio_write_32(PERI_SC_PERIPH_CTRL8, EYE_PATTERN);
1150
1151 /* configure USB PHY */
1152 data = mmio_read_32(PERI_SC_PERIPH_CTRL4);
1153 /* make PHY out of low power mode */
1154 data &= ~PERI_CTRL4_PICO_SIDDQ;
1155 /* detect VBUS by external circuit, switch D+ to 1.5KOhm pullup */
1156 data |= PERI_CTRL4_PICO_VBUSVLDEXTSEL | PERI_CTRL4_PICO_VBUSVLDEXT;
1157 data &= ~PERI_CTRL4_FPGA_EXT_PHY_SEL;
1158 /* select PHY */
1159 data &= ~PERI_CTRL4_OTG_PHY_SEL;
1160 mmio_write_32(PERI_SC_PERIPH_CTRL4, data);
1161
1162 udelay(1000);
1163
1164 data = mmio_read_32(PERI_SC_PERIPH_CTRL5);
1165 data &= ~PERI_CTRL5_PICOPHY_BC_MODE;
1166 mmio_write_32(PERI_SC_PERIPH_CTRL5, data);
1167
1168 udelay(20000);
1169 }
1170
init_usb(void)1171 int init_usb(void)
1172 {
1173 static int init_flag = 0;
1174 uint32_t data;
1175
1176 if (init_flag == 0) {
1177 memset(&ctrl_req, 0, sizeof(setup_packet));
1178 memset(&ctrl_resp, 0, 2);
1179 memset(&endpoints, 0, sizeof(struct ep_type) * NUM_ENDPOINTS);
1180 memset(&dma_desc, 0, sizeof(struct dwc_otg_dev_dma_desc));
1181 memset(&dma_desc_ep0, 0, sizeof(struct dwc_otg_dev_dma_desc));
1182 memset(&dma_desc_in, 0, sizeof(struct dwc_otg_dev_dma_desc));
1183 }
1184
1185 VERBOSE("Pico PHY and DVC init start.\n");
1186
1187 dvc_and_picophy_init_chip();
1188 VERBOSE("Pico PHY and DVC init done.\n");
1189
1190 /* wait for OTG AHB master idle */
1191 do {
1192 data = mmio_read_32(GRSTCTL) & GRSTCTL_AHBIDLE;
1193 } while (data == 0);
1194 VERBOSE("Reset usb controller\n");
1195
1196 /* OTG: Assert software reset */
1197 mmio_write_32(GRSTCTL, GRSTCTL_CSFTRST);
1198
1199 /* wait for OTG to ack reset */
1200 while (mmio_read_32(GRSTCTL) & GRSTCTL_CSFTRST);
1201
1202 /* wait for OTG AHB master idle */
1203 while ((mmio_read_32(GRSTCTL) & GRSTCTL_AHBIDLE) == 0);
1204
1205 VERBOSE("Reset usb controller done\n");
1206
1207 usb_config();
1208 VERBOSE("exit usb_init()\n");
1209 return 0;
1210 }
1211
1212 #define LOCK_STATE_LOCKED 0
1213 #define LOCK_STATE_UNLOCKED 1
1214 #define LOCK_STATE_RELOCKED 2
1215
1216 #define FB_MAX_FILE_SIZE (256 * 1024 * 1024)
1217
1218 static struct ptentry *flash_ptn = NULL;
1219
fb_getvar(char * cmdbuf)1220 static void fb_getvar(char *cmdbuf)
1221 {
1222 char response[64];
1223 char part_name[32];
1224 int bytes;
1225 struct ptentry *ptn = 0;
1226
1227 if (!strncmp(cmdbuf + 7, "max-download-size", 17)) {
1228 bytes = sprintf(response, "OKAY0x%08x",
1229 FB_MAX_FILE_SIZE);
1230 response[bytes] = '\0';
1231 tx_status(response);
1232 rx_cmd();
1233 } else if (!strncmp(cmdbuf + 7, "partition-type:", 15)) {
1234 bytes = sprintf(part_name, "%s", cmdbuf + 22);
1235 ptn = find_ptn(part_name);
1236 if (ptn == NULL) {
1237 bytes = sprintf(response, "FAIL%s",
1238 "invalid partition");
1239 response[bytes] = '\0';
1240 flash_ptn = NULL;
1241 } else {
1242 flash_ptn = ptn;
1243 if (!strncmp(cmdbuf +22, "system", 6) || !strncmp(cmdbuf +22, "userdata", 8) ||
1244 !strncmp(cmdbuf +22, "cache", 5)) {
1245 bytes = sprintf(response, "OKAYext4");
1246 response[bytes] = '\0';
1247 } else {
1248 bytes = sprintf(response, "OKAYraw");
1249 response[bytes] = '\0';
1250 }
1251 }
1252 tx_status(response);
1253 rx_cmd();
1254 } else if (!strncmp(cmdbuf + 7, "partition-size:", 15)) {
1255 bytes = sprintf(part_name, "%s", cmdbuf + 22);
1256 ptn = find_ptn(part_name);
1257 if (ptn == NULL) {
1258 bytes = sprintf(response, "FAIL%s",
1259 "invalid partition");
1260 response[bytes] = '\0';
1261 flash_ptn = NULL;
1262 } else {
1263 bytes = sprintf(response, "OKAY%llx",ptn->length);
1264 response[bytes] = '\0';
1265 flash_ptn = ptn;
1266 }
1267 tx_status(response);
1268 rx_cmd();
1269 } else if (!strncmp(cmdbuf + 7, "serialno", 8)) {
1270 bytes = sprintf(response, "OKAY%s",
1271 load_serialno());
1272 response[bytes] = '\0';
1273 tx_status(response);
1274 rx_cmd();
1275 } else if (!strncmp(cmdbuf + 7, "version-bootloader", 18)) {
1276 bytes = sprintf(response, "OKAY%s", VERSION_BOOTLOADER);
1277 response[bytes] = '\0';
1278 tx_status(response);
1279 rx_cmd();
1280 } else if (!strncmp(cmdbuf + 7, "version-baseband", 16)) {
1281 bytes = sprintf(response, "OKAYN/A");
1282 response[bytes] = '\0';
1283 tx_status(response);
1284 rx_cmd();
1285 } else if (!strncmp(cmdbuf + 7, "product", 8)) {
1286 bytes = sprintf(response, "OKAYhikey");
1287 response[bytes] = '\0';
1288 tx_status(response);
1289 rx_cmd();
1290 } else {
1291 bytes = sprintf(response, "FAIL%s",
1292 "unknown var");
1293 response[bytes] = '\0';
1294 tx_status(response);
1295 rx_cmd();
1296 }
1297 }
1298
1299 /* FIXME: do not support endptr yet */
strtoul(const char * nptr,char ** endptr,int base)1300 static unsigned long strtoul(const char *nptr, char **endptr, int base)
1301 {
1302 unsigned long step, data;
1303 int i;
1304
1305 if (base == 0)
1306 step = 10;
1307 else if ((base < 2) || (base > 36)) {
1308 VERBOSE("%s: invalid base %d\n", __func__, base);
1309 return 0;
1310 } else
1311 step = base;
1312
1313 for (i = 0, data = 0; ; i++) {
1314 if (nptr[i] == '\0')
1315 break;
1316 else if (!isalpha(nptr[i]) && !isdigit(nptr[i])) {
1317 VERBOSE("%s: invalid string %s at %d [%x]\n",
1318 __func__, nptr, i, nptr[i]);
1319 return 0;
1320 } else {
1321 data *= step;
1322 if (isupper(nptr[i]))
1323 data += nptr[i] - 'A' + 10;
1324 else if (islower(nptr[i]))
1325 data += nptr[i] - 'a' + 10;
1326 else if (isdigit(nptr[i]))
1327 data += nptr[i] - '0';
1328 }
1329 }
1330 return data;
1331 }
1332
fb_serialno(char * cmdbuf)1333 static void fb_serialno(char *cmdbuf)
1334 {
1335 struct random_serial_num random;
1336
1337 generate_serialno(&random);
1338 flush_random_serialno((unsigned long)&random, sizeof(random));
1339 }
1340
fb_assigned_sn(char * cmdbuf)1341 static int fb_assigned_sn(char *cmdbuf)
1342 {
1343 struct random_serial_num random;
1344 int ret;
1345
1346 ret = assign_serialno(cmdbuf, &random);
1347 if (ret < 0)
1348 return ret;
1349 flush_random_serialno((unsigned long)&random, sizeof(random));
1350 return 0;
1351 }
1352
1353 #define FB_DOWNLOAD_BASE 0x20000000
1354
1355 static unsigned long fb_download_base, fb_download_size;
1356
fb_download(char * cmdbuf)1357 static void fb_download(char *cmdbuf)
1358 {
1359 char response[64];
1360 int bytes;
1361
1362 if (!flash_ptn) {
1363 bytes = sprintf(response, "FAIL%s",
1364 "invalid partition");
1365 response[bytes] = '\0';
1366 tx_status(response);
1367 rx_cmd();
1368 } else {
1369 rx_addr = FB_DOWNLOAD_BASE;
1370 rx_length = strtoul(cmdbuf + 9, NULL, 16);
1371 fb_download_base = rx_addr;
1372 fb_download_size = rx_length;
1373 if (rx_length > FB_MAX_FILE_SIZE) {
1374 bytes = sprintf(response, "FAIL%s",
1375 "file is too large");
1376 response[bytes] = '\0';
1377 tx_status(response);
1378 rx_cmd();
1379 } else {
1380 bytes = sprintf(response, "DATA%08x",
1381 rx_length);
1382 VERBOSE("start:0x%x, length:0x%x, res:%s\n",
1383 rx_addr, rx_length, response);
1384 response[bytes] = '\0';
1385 tx_status(response);
1386 rx_data();
1387 }
1388 }
1389 }
1390
fb_flash(char * cmdbuf)1391 static void fb_flash(char *cmdbuf)
1392 {
1393 flush_user_images(cmdbuf + 6, fb_download_base, fb_download_size);
1394 tx_status("OKAY");
1395 rx_cmd();
1396 }
1397
fb_reboot(char * cmdbuf)1398 static void fb_reboot(char *cmdbuf)
1399 {
1400 /* Send the system reset request */
1401 mmio_write_32(AO_SC_SYS_STAT0, 0x48698284);
1402
1403 wfi();
1404 panic();
1405 }
1406
usb_rx_cmd_complete(unsigned actual,int stat)1407 static void usb_rx_cmd_complete(unsigned actual, int stat)
1408 {
1409 if(stat != 0) return;
1410
1411 if(actual > 4095)
1412 actual = 4095;
1413 cmdbuf[actual] = 0;
1414
1415 INFO("cmd :%s\n",cmdbuf);
1416
1417 if(memcmp(cmdbuf, (void *)"reboot", 6) == 0) {
1418 tx_status("OKAY");
1419 fb_reboot(cmdbuf);
1420 return;
1421 } else if (!memcmp(cmdbuf, (void *)"getvar:", 7)) {
1422 fb_getvar(cmdbuf);
1423 return;
1424 } else if (!memcmp(cmdbuf, (void *)"download:", 9)) {
1425 fb_download(cmdbuf);
1426 return;
1427 } else if(memcmp(cmdbuf, (void *)"erase:", 6) == 0) {
1428 /* FIXME erase is not supported but we return success */
1429 tx_status("OKAY");
1430 rx_cmd();
1431 return;
1432 } else if(memcmp(cmdbuf, (void *)"flash:", 6) == 0) {
1433 INFO("recog updatefile\n");
1434 fb_flash(cmdbuf);
1435 return;
1436 } else if(memcmp(cmdbuf, (void *)"boot", 4) == 0) {
1437 INFO(" - OKAY\n");
1438
1439 return;
1440 } else if (memcmp(cmdbuf, (void *)"oem serialno", 12) == 0) {
1441 if (*(cmdbuf + 12) == '\0') {
1442 fb_serialno(cmdbuf);
1443 tx_status("OKAY");
1444 rx_cmd();
1445 return;
1446 } else if (memcmp(cmdbuf + 12, (void *)" set", 4) == 0) {
1447 if (fb_assigned_sn(cmdbuf + 16) == 0) {
1448 tx_status("OKAY");
1449 rx_cmd();
1450 return;
1451 }
1452 }
1453 } else if (memcmp(cmdbuf, (void *)"oem led", 7) == 0) {
1454 if ((*(cmdbuf + 7) >= '1') && (*(cmdbuf + 7) <= '4')) {
1455 int led;
1456 led = *(cmdbuf + 7) - '0';
1457 if (memcmp(cmdbuf + 8, (void *)" on", 3) == 0) {
1458 gpio_set_value(31 + led, 1);
1459 tx_status("OKAY");
1460 rx_cmd();
1461 return;
1462 } else if (memcmp(cmdbuf + 8, (void *)" off", 4) == 0) {
1463 gpio_set_value(31 + led, 0);
1464 tx_status("OKAY");
1465 rx_cmd();
1466 return;
1467 }
1468 }
1469 }
1470
1471 tx_status("FAILinvalid command");
1472 rx_cmd();
1473 }
1474
usbloader_init(void)1475 static void usbloader_init(void)
1476 {
1477 VERBOSE("enter usbloader_init\n");
1478
1479 /*usb sw and hw init*/
1480 init_usb();
1481
1482 /*alloc and init sth for transfer*/
1483 ep1in.num = BULK_IN_EP;
1484 ep1in.in = 1;
1485 ep1in.req = NULL;
1486 ep1in.maxpkt = MAX_PACKET_LEN;
1487 ep1in.next = &ep1in;
1488 ep1out.num = BULK_OUT_EP;
1489 ep1out.in = 0;
1490 ep1out.req = NULL;
1491 ep1out.maxpkt = MAX_PACKET_LEN;
1492 ep1out.next = &ep1out;
1493 cmdbuf = (char *)(rx_req.buf);
1494
1495 VERBOSE("exit usbloader_init\n");
1496 }
1497
usb_reinit()1498 void usb_reinit()
1499 {
1500 if (usb_need_reset)
1501 {
1502 usb_need_reset = 0;
1503 init_usb();
1504 }
1505 }
1506
usb_download(void)1507 void usb_download(void)
1508 {
1509 usbloader_init();
1510 INFO("Enter downloading mode. Please run fastboot command on Host.\n");
1511 for (;;) {
1512 usb_poll();
1513 usb_reinit();
1514 }
1515 }
1516