1/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <asm_macros.S>
33#include <bl_common.h>
34#include <cortex_a57.h>
35#include <cpu_macros.S>
36#include <platform_def.h>
37#include "../juno_def.h"
38
39	.globl	plat_crash_console_init
40	.globl	plat_crash_console_putc
41	.globl	plat_report_exception
42	.globl	plat_reset_handler
43	.globl	platform_get_core_pos
44	.globl	platform_mem_init
45
46	/* Define a crash console for the plaform */
47#define JUNO_CRASH_CONSOLE_BASE		PL011_UART3_BASE
48
49	/* ---------------------------------------------
50	 * int plat_crash_console_init(void)
51	 * Function to initialize the crash console
52	 * without a C Runtime to print crash report.
53	 * Clobber list : x0, x1, x2
54	 * ---------------------------------------------
55	 */
56func plat_crash_console_init
57	mov_imm	x0, JUNO_CRASH_CONSOLE_BASE
58	mov_imm	x1, PL011_UART3_CLK_IN_HZ
59	mov_imm	x2, PL011_BAUDRATE
60	b	console_core_init
61
62	/* ---------------------------------------------
63	 * int plat_crash_console_putc(int c)
64	 * Function to print a character on the crash
65	 * console without a C Runtime.
66	 * Clobber list : x1, x2
67	 * ---------------------------------------------
68	 */
69func plat_crash_console_putc
70	mov_imm	x1, JUNO_CRASH_CONSOLE_BASE
71	b	console_core_putc
72
73	/* ---------------------------------------------
74	 * void plat_report_exception(unsigned int type)
75	 * Function to report an unhandled exception
76	 * with platform-specific means.
77	 * On Juno platform, it updates the LEDs
78	 * to indicate where we are
79	 * ---------------------------------------------
80	 */
81func plat_report_exception
82	mrs	x1, CurrentEl
83	lsr	x1, x1, #MODE_EL_SHIFT
84	lsl	x1, x1, #SYS_LED_EL_SHIFT
85	lsl	x0, x0, #SYS_LED_EC_SHIFT
86	mov	x2, #(SECURE << SYS_LED_SS_SHIFT)
87	orr	x0, x0, x2
88	orr	x0, x0, x1
89	mov	x1, #VE_SYSREGS_BASE
90	add	x1, x1, #V2M_SYS_LED
91	str	w0, [x1]
92	ret
93
94	/*
95	 * Return 0 to 3 for the A53s and 4 or 5 for the A57s
96	 */
97func platform_get_core_pos
98	and	x1, x0, #MPIDR_CPU_MASK
99	and	x0, x0, #MPIDR_CLUSTER_MASK
100	eor	x0, x0, #(1 << MPIDR_AFFINITY_BITS)  // swap A53/A57 order
101	add	x0, x1, x0, LSR #6
102	ret
103
104
105	/* -----------------------------------------------------
106	 * void platform_mem_init(void);
107	 *
108	 * We don't need to carry out any memory initialization
109	 * on Juno. The Secure RAM is accessible straight away.
110	 * -----------------------------------------------------
111	 */
112func platform_mem_init
113	ret
114
115	/* -----------------------------------------------------
116	 * void plat_reset_handler(void);
117	 *
118	 * Before adding code in this function, refer to the
119	 * guidelines in docs/firmware-design.md to determine
120	 * whether the code should reside within the
121	 * FIRST_RESET_HANDLER_CALL block or not.
122	 *
123	 * Implement workaround for defect id 831273 by enabling
124	 * an event stream every 65536 cycles and set the L2 RAM
125	 * latencies for Cortex-A57. This code is included only
126	 * when FIRST_RESET_HANDLER_CALL is defined since it
127	 * should be executed only during BL1.
128	 * -----------------------------------------------------
129	 */
130func plat_reset_handler
131#ifdef FIRST_RESET_HANDLER_CALL
132	/* Read the MIDR_EL1 */
133	mrs	x0, midr_el1
134	ubfx	x1, x0, MIDR_PN_SHIFT, #12
135	cmp     w1, #((CORTEX_A57_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
136	b.ne    1f
137
138	/* Change the L2 Data and Tag Ram latency to 3 cycles */
139	mov	x0, #(L2_DATA_RAM_LATENCY_3_CYCLES |    \
140			(L2_TAG_RAM_LATENCY_3_CYCLES << \
141			 L2CTLR_TAG_RAM_LATENCY_SHIFT))
142	msr     L2CTLR_EL1, x0
143
1441:
145	/* ---------------------------------------------
146	 * Enable the event stream every 65536 cycles
147	 * ---------------------------------------------
148	 */
149	mov     x0, #(0xf << EVNTI_SHIFT)
150	orr     x0, x0, #EVNTEN_BIT
151	msr     CNTKCTL_EL1, x0
152	isb
153#endif /* FIRST_RESET_HANDLER_CALL */
154	ret
155