1#
2# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are met:
6#
7# Redistributions of source code must retain the above copyright notice, this
8# list of conditions and the following disclaimer.
9#
10# Redistributions in binary form must reproduce the above copyright notice,
11# this list of conditions and the following disclaimer in the documentation
12# and/or other materials provided with the distribution.
13#
14# Neither the name of ARM nor the names of its contributors may be used
15# to endorse or promote products derived from this software without specific
16# prior written permission.
17#
18# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28# POSSIBILITY OF SUCH DAMAGE.
29#
30
31# On Juno, the Secure Payload can be loaded either in Trusted SRAM (default) or
32# Secure DRAM allocated by the TrustZone Controller.
33
34PLAT_TSP_LOCATION	:=	tsram
35
36ifeq (${PLAT_TSP_LOCATION}, tsram)
37  PLAT_TSP_LOCATION_ID := PLAT_TRUSTED_SRAM_ID
38else ifeq (${PLAT_TSP_LOCATION}, dram)
39  PLAT_TSP_LOCATION_ID := PLAT_DRAM_ID
40else
41  $(error "Unsupported PLAT_TSP_LOCATION value")
42endif
43
44# Process flags
45$(eval $(call add_define,PLAT_TSP_LOCATION_ID))
46
47
48PLAT_INCLUDES		:=	-Iplat/juno/include/
49
50PLAT_BL_COMMON_SOURCES	:=	drivers/arm/pl011/pl011_console.S	\
51				drivers/io/io_fip.c			\
52				drivers/io/io_memmap.c			\
53				drivers/io/io_storage.c			\
54				lib/aarch64/xlat_tables.c		\
55				plat/common/aarch64/plat_common.c	\
56				plat/common/plat_gic.c			\
57				plat/juno/plat_io_storage.c
58
59BL1_SOURCES		+=	drivers/arm/cci400/cci400.c		\
60				lib/cpus/aarch64/cortex_a53.S		\
61				lib/cpus/aarch64/cortex_a57.S		\
62				plat/common/aarch64/platform_up_stack.S	\
63				plat/juno/bl1_plat_setup.c		\
64				plat/juno/aarch64/bl1_plat_helpers.S	\
65				plat/juno/aarch64/plat_helpers.S	\
66				plat/juno/aarch64/juno_common.c
67
68BL2_SOURCES		+=	drivers/arm/tzc400/tzc400.c		\
69				plat/common/aarch64/platform_up_stack.S	\
70				plat/juno/bl2_plat_setup.c		\
71				plat/juno/mhu.c				\
72				plat/juno/plat_security.c		\
73				plat/juno/aarch64/plat_helpers.S	\
74				plat/juno/aarch64/juno_common.c		\
75				plat/juno/scp_bootloader.c		\
76				plat/juno/scpi.c
77
78BL31_SOURCES		+=	drivers/arm/cci400/cci400.c		\
79				drivers/arm/gic/arm_gic.c		\
80				drivers/arm/gic/gic_v2.c		\
81				drivers/arm/gic/gic_v3.c		\
82				lib/cpus/aarch64/cortex_a53.S		\
83				lib/cpus/aarch64/cortex_a57.S		\
84				plat/common/aarch64/platform_mp_stack.S	\
85				plat/juno/bl31_plat_setup.c		\
86				plat/juno/mhu.c				\
87				plat/juno/aarch64/plat_helpers.S	\
88				plat/juno/aarch64/juno_common.c		\
89				plat/juno/plat_pm.c			\
90				plat/juno/plat_topology.c		\
91				plat/juno/scpi.c
92
93ifneq (${TRUSTED_BOARD_BOOT},0)
94  BL1_SOURCES		+=	plat/juno/juno_trusted_boot.c
95  BL2_SOURCES		+=	plat/juno/juno_trusted_boot.c
96endif
97
98ifneq (${RESET_TO_BL31},0)
99  $(error "Using BL3-1 as the reset vector is not supported on Juno. \
100  Please set RESET_TO_BL31 to 0.")
101endif
102
103NEED_BL30		:=	yes
104
105# Enable workarounds for selected Cortex-A57 erratas.
106ERRATA_A57_806969	:=	1
107ERRATA_A57_813420	:=	1
108
109# Enable option to skip L1 data cache flush during the Cortex-A57 cluster
110# power down sequence
111SKIP_A57_L1_FLUSH_PWR_DWN	:=	 1
112