1/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <asm_macros.S>
33#include <psci.h>
34#include <xlat_tables.h>
35
36	.globl	psci_aff_on_finish_entry
37	.globl	psci_aff_suspend_finish_entry
38	.globl	psci_power_down_wfi
39
40	/* -----------------------------------------------------
41	 * This cpu has been physically powered up. Depending
42	 * upon whether it was resumed from suspend or simply
43	 * turned on, call the common power on finisher with
44	 * the handlers (chosen depending upon original state).
45	 * -----------------------------------------------------
46	 */
47func psci_aff_on_finish_entry
48	adr	x23, psci_afflvl_on_finishers
49	b	psci_aff_common_finish_entry
50
51psci_aff_suspend_finish_entry:
52	adr	x23, psci_afflvl_suspend_finishers
53
54psci_aff_common_finish_entry:
55#if !RESET_TO_BL31
56	/* ---------------------------------------------
57	 * Perform any processor specific actions which
58	 * undo or are in addition to the actions
59	 * performed by the reset handler in the BootROM
60	 * (BL1) e.g. cache, tlb invalidations, errata
61	 * workarounds etc.
62	 * ---------------------------------------------
63	 */
64	bl      reset_handler
65
66	/* ---------------------------------------------
67	 * Enable the instruction cache, stack pointer
68	 * and data access alignment checks.
69	 * It can be assumed that BL3-1 entrypoint code
70	 * will do this when RESET_TO_BL31 is set. The
71	 * same  assumption cannot be made when another
72	 * boot loader executes before BL3-1 in the warm
73	 * boot path e.g. BL1.
74	 * ---------------------------------------------
75	 */
76	mov	x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
77	mrs	x0, sctlr_el3
78	orr	x0, x0, x1
79	msr	sctlr_el3, x0
80	isb
81#endif
82
83	/* ---------------------------------------------
84	 * Initialise the pcpu cache pointer for the CPU
85	 * ---------------------------------------------
86	 */
87	bl	init_cpu_data_ptr
88
89	/* ---------------------------------------------
90	 * Initialize the cpu_ops pointer.
91	 * ---------------------------------------------
92	 */
93	bl	init_cpu_ops
94
95	/* ---------------------------------------------
96	 * Set the exception vectors
97	 * ---------------------------------------------
98	 */
99	adr	x0, runtime_exceptions
100	msr	vbar_el3, x0
101	isb
102
103	/* ---------------------------------------------
104	 * Enable the SError interrupt now that the
105	 * exception vectors have been setup.
106	 * ---------------------------------------------
107	 */
108	msr	daifclr, #DAIF_ABT_BIT
109
110	/* ---------------------------------------------
111	 * Use SP_EL0 for the C runtime stack.
112	 * ---------------------------------------------
113	 */
114	msr	spsel, #0
115
116	/* --------------------------------------------
117	 * Give ourselves a stack whose memory will be
118	 * marked as Normal-IS-WBWA when the MMU is
119	 * enabled.
120	 * --------------------------------------------
121	 */
122	mrs	x0, mpidr_el1
123	bl	platform_set_stack
124
125	/* --------------------------------------------
126	 * Enable the MMU with the DCache disabled. It
127	 * is safe to use stacks allocated in normal
128	 * memory as a result. All memory accesses are
129	 * marked nGnRnE when the MMU is disabled. So
130	 * all the stack writes will make it to memory.
131	 * All memory accesses are marked Non-cacheable
132	 * when the MMU is enabled but D$ is disabled.
133	 * So used stack memory is guaranteed to be
134	 * visible immediately after the MMU is enabled
135	 * Enabling the DCache at the same time as the
136	 * MMU can lead to speculatively fetched and
137	 * possibly stale stack memory being read from
138	 * other caches. This can lead to coherency
139	 * issues.
140	 * --------------------------------------------
141	 */
142	mov	x0, #DISABLE_DCACHE
143	bl	bl31_plat_enable_mmu
144
145	/* ---------------------------------------------
146	 * Call the finishers starting from affinity
147	 * level 0.
148	 * ---------------------------------------------
149	 */
150	bl	get_power_on_target_afflvl
151	mov	x2, x23
152	mov	x1, x0
153	mov	x0, #MPIDR_AFFLVL0
154	bl	psci_afflvl_power_on_finish
155
156	b	el3_exit
157
158	/* --------------------------------------------
159	 * This function is called to indicate to the
160	 * power controller that it is safe to power
161	 * down this cpu. It should not exit the wfi
162	 * and will be released from reset upon power
163	 * up. 'wfi_spill' is used to catch erroneous
164	 * exits from wfi.
165	 * --------------------------------------------
166	 */
167func psci_power_down_wfi
168	dsb	sy		// ensure write buffer empty
169	wfi
170wfi_spill:
171	b	wfi_spill
172
173