1 /** @file
2   Cache Maintenance Functions. These functions vary by ARM architecture so the MdePkg
3   versions are null functions used to make sure things will compile.
4 
5   Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
6   Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
7   This program and the accompanying materials
8   are licensed and made available under the terms and conditions of the BSD License
9   which accompanies this distribution.  The full text of the license may be found at
10   http://opensource.org/licenses/bsd-license.php.
11 
12   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 
15 **/
16 
17 //
18 // Include common header file for this module.
19 //
20 #include <Base.h>
21 #include <Library/DebugLib.h>
22 
23 /**
24   Invalidates the entire instruction cache in cache coherency domain of the
25   calling CPU.
26 
27   Invalidates the entire instruction cache in cache coherency domain of the
28   calling CPU.
29 
30 **/
31 VOID
32 EFIAPI
InvalidateInstructionCache(VOID)33 InvalidateInstructionCache (
34   VOID
35   )
36 {
37   ASSERT(FALSE);
38 }
39 
40 /**
41   Invalidates a range of instruction cache lines in the cache coherency domain
42   of the calling CPU.
43 
44   Invalidates the instruction cache lines specified by Address and Length. If
45   Address is not aligned on a cache line boundary, then entire instruction
46   cache line containing Address is invalidated. If Address + Length is not
47   aligned on a cache line boundary, then the entire instruction cache line
48   containing Address + Length -1 is invalidated. This function may choose to
49   invalidate the entire instruction cache if that is more efficient than
50   invalidating the specified range. If Length is 0, then no instruction cache
51   lines are invalidated. Address is returned.
52 
53   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
54 
55   @param  Address The base address of the instruction cache lines to
56                   invalidate. If the CPU is in a physical addressing mode, then
57                   Address is a physical address. If the CPU is in a virtual
58                   addressing mode, then Address is a virtual address.
59 
60   @param  Length  The number of bytes to invalidate from the instruction cache.
61 
62   @return Address
63 
64 **/
65 VOID *
66 EFIAPI
InvalidateInstructionCacheRange(IN VOID * Address,IN UINTN Length)67 InvalidateInstructionCacheRange (
68   IN      VOID                      *Address,
69   IN      UINTN                     Length
70   )
71 {
72   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
73   ASSERT(FALSE);
74   return Address;
75 }
76 
77 /**
78   Writes back and invalidates the entire data cache in cache coherency domain
79   of the calling CPU.
80 
81   Writes Back and Invalidates the entire data cache in cache coherency domain
82   of the calling CPU. This function guarantees that all dirty cache lines are
83   written back to system memory, and also invalidates all the data cache lines
84   in the cache coherency domain of the calling CPU.
85 
86 **/
87 VOID
88 EFIAPI
WriteBackInvalidateDataCache(VOID)89 WriteBackInvalidateDataCache (
90   VOID
91   )
92 {
93   ASSERT(FALSE);
94 }
95 
96 /**
97   Writes back and invalidates a range of data cache lines in the cache
98   coherency domain of the calling CPU.
99 
100   Writes back and invalidates the data cache lines specified by Address and
101   Length. If Address is not aligned on a cache line boundary, then entire data
102   cache line containing Address is written back and invalidated. If Address +
103   Length is not aligned on a cache line boundary, then the entire data cache
104   line containing Address + Length -1 is written back and invalidated. This
105   function may choose to write back and invalidate the entire data cache if
106   that is more efficient than writing back and invalidating the specified
107   range. If Length is 0, then no data cache lines are written back and
108   invalidated. Address is returned.
109 
110   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
111 
112   @param  Address The base address of the data cache lines to write back and
113                   invalidate. If the CPU is in a physical addressing mode, then
114                   Address is a physical address. If the CPU is in a virtual
115                   addressing mode, then Address is a virtual address.
116   @param  Length  The number of bytes to write back and invalidate from the
117                   data cache.
118 
119   @return Address
120 
121 **/
122 VOID *
123 EFIAPI
WriteBackInvalidateDataCacheRange(IN VOID * Address,IN UINTN Length)124 WriteBackInvalidateDataCacheRange (
125   IN      VOID                      *Address,
126   IN      UINTN                     Length
127   )
128 {
129   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
130   ASSERT(FALSE);
131   return Address;
132 }
133 
134 /**
135   Writes back the entire data cache in cache coherency domain of the calling
136   CPU.
137 
138   Writes back the entire data cache in cache coherency domain of the calling
139   CPU. This function guarantees that all dirty cache lines are written back to
140   system memory. This function may also invalidate all the data cache lines in
141   the cache coherency domain of the calling CPU.
142 
143 **/
144 VOID
145 EFIAPI
WriteBackDataCache(VOID)146 WriteBackDataCache (
147   VOID
148   )
149 {
150   ASSERT(FALSE);
151 }
152 
153 /**
154   Writes back a range of data cache lines in the cache coherency domain of the
155   calling CPU.
156 
157   Writes back the data cache lines specified by Address and Length. If Address
158   is not aligned on a cache line boundary, then entire data cache line
159   containing Address is written back. If Address + Length is not aligned on a
160   cache line boundary, then the entire data cache line containing Address +
161   Length -1 is written back. This function may choose to write back the entire
162   data cache if that is more efficient than writing back the specified range.
163   If Length is 0, then no data cache lines are written back. This function may
164   also invalidate all the data cache lines in the specified range of the cache
165   coherency domain of the calling CPU. Address is returned.
166 
167   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
168 
169   @param  Address The base address of the data cache lines to write back. If
170                   the CPU is in a physical addressing mode, then Address is a
171                   physical address. If the CPU is in a virtual addressing
172                   mode, then Address is a virtual address.
173   @param  Length  The number of bytes to write back from the data cache.
174 
175   @return Address
176 
177 **/
178 VOID *
179 EFIAPI
WriteBackDataCacheRange(IN VOID * Address,IN UINTN Length)180 WriteBackDataCacheRange (
181   IN      VOID                      *Address,
182   IN      UINTN                     Length
183   )
184 {
185   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
186   ASSERT(FALSE);
187   return Address;
188 }
189 
190 /**
191   Invalidates the entire data cache in cache coherency domain of the calling
192   CPU.
193 
194   Invalidates the entire data cache in cache coherency domain of the calling
195   CPU. This function must be used with care because dirty cache lines are not
196   written back to system memory. It is typically used for cache diagnostics. If
197   the CPU does not support invalidation of the entire data cache, then a write
198   back and invalidate operation should be performed on the entire data cache.
199 
200 **/
201 VOID
202 EFIAPI
InvalidateDataCache(VOID)203 InvalidateDataCache (
204   VOID
205   )
206 {
207   ASSERT(FALSE);
208 }
209 
210 /**
211   Invalidates a range of data cache lines in the cache coherency domain of the
212   calling CPU.
213 
214   Invalidates the data cache lines specified by Address and Length. If Address
215   is not aligned on a cache line boundary, then entire data cache line
216   containing Address is invalidated. If Address + Length is not aligned on a
217   cache line boundary, then the entire data cache line containing Address +
218   Length -1 is invalidated. This function must never invalidate any cache lines
219   outside the specified range. If Length is 0, then no data cache lines are
220   invalidated. Address is returned. This function must be used with care
221   because dirty cache lines are not written back to system memory. It is
222   typically used for cache diagnostics. If the CPU does not support
223   invalidation of a data cache range, then a write back and invalidate
224   operation should be performed on the data cache range.
225 
226   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
227 
228   @param  Address The base address of the data cache lines to invalidate. If
229                   the CPU is in a physical addressing mode, then Address is a
230                   physical address. If the CPU is in a virtual addressing mode,
231                   then Address is a virtual address.
232   @param  Length  The number of bytes to invalidate from the data cache.
233 
234   @return Address
235 
236 **/
237 VOID *
238 EFIAPI
InvalidateDataCacheRange(IN VOID * Address,IN UINTN Length)239 InvalidateDataCacheRange (
240   IN      VOID                      *Address,
241   IN      UINTN                     Length
242   )
243 {
244   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
245   ASSERT(FALSE);
246   return Address;
247 }
248