1 /** @file
2   Cache Maintenance Functions.
3 
4   Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
5   This program and the accompanying materials
6   are licensed and made available under the terms and conditions of the BSD License
7   which accompanies this distribution.  The full text of the license may be found at
8   http://opensource.org/licenses/bsd-license.php.
9 
10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 
13 **/
14 
15 #include <Base.h>
16 #include <Library/CacheMaintenanceLib.h>
17 #include <Library/BaseLib.h>
18 #include <Library/DebugLib.h>
19 #include <Library/PalLib.h>
20 
21 /**
22   Invalidates the entire instruction cache in cache coherency domain of the
23   calling CPU.
24 
25 **/
26 VOID
27 EFIAPI
InvalidateInstructionCache(VOID)28 InvalidateInstructionCache (
29   VOID
30   )
31 {
32   PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_INSTRUCTION_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);
33 }
34 
35 /**
36   Invalidates a range of instruction cache lines in the cache coherency domain
37   of the calling CPU.
38 
39   Invalidates the instruction cache lines specified by Address and Length. If
40   Address is not aligned on a cache line boundary, then entire instruction
41   cache line containing Address is invalidated. If Address + Length is not
42   aligned on a cache line boundary, then the entire instruction cache line
43   containing Address + Length -1 is invalidated. This function may choose to
44   invalidate the entire instruction cache if that is more efficient than
45   invalidating the specified range. If Length is 0, then no instruction cache
46   lines are invalidated. Address is returned.
47 
48   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
49 
50   @param  Address The base address of the instruction cache lines to
51                   invalidate. If the CPU is in a physical addressing mode, then
52                   Address is a physical address. If the CPU is in a virtual
53                   addressing mode, then Address is a virtual address.
54 
55   @param  Length  The number of bytes to invalidate from the instruction cache.
56 
57   @return Address.
58 
59 **/
60 VOID *
61 EFIAPI
InvalidateInstructionCacheRange(IN VOID * Address,IN UINTN Length)62 InvalidateInstructionCacheRange (
63   IN      VOID                      *Address,
64   IN      UINTN                     Length
65   )
66 {
67   return AsmFlushCacheRange (Address, Length);
68 }
69 
70 /**
71   Writes back and invalidates the entire data cache in cache coherency domain
72   of the calling CPU.
73 
74   Writes back and invalidates the entire data cache in cache coherency domain
75   of the calling CPU. This function guarantees that all dirty cache lines are
76   written back to system memory, and also invalidates all the data cache lines
77   in the cache coherency domain of the calling CPU.
78 
79 **/
80 VOID
81 EFIAPI
WriteBackInvalidateDataCache(VOID)82 WriteBackInvalidateDataCache (
83   VOID
84   )
85 {
86   PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);
87 }
88 
89 /**
90   Writes back and invalidates a range of data cache lines in the cache
91   coherency domain of the calling CPU.
92 
93   Writes back and invalidates the data cache lines specified by Address and
94   Length. If Address is not aligned on a cache line boundary, then entire data
95   cache line containing Address is written back and invalidated. If Address +
96   Length is not aligned on a cache line boundary, then the entire data cache
97   line containing Address + Length -1 is written back and invalidated. This
98   function may choose to write back and invalidate the entire data cache if
99   that is more efficient than writing back and invalidating the specified
100   range. If Length is 0, then no data cache lines are written back and
101   invalidated. Address is returned.
102 
103   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
104 
105   @param  Address The base address of the data cache lines to write back and
106                   invalidate. If the CPU is in a physical addressing mode, then
107                   Address is a physical address. If the CPU is in a virtual
108                   addressing mode, then Address is a virtual address.
109   @param  Length  The number of bytes to write back and invalidate from the
110                   data cache.
111 
112   @return Address of cache invalidation.
113 
114 **/
115 VOID *
116 EFIAPI
WriteBackInvalidateDataCacheRange(IN VOID * Address,IN UINTN Length)117 WriteBackInvalidateDataCacheRange (
118   IN      VOID                      *Address,
119   IN      UINTN                     Length
120   )
121 {
122   return AsmFlushCacheRange (Address, Length);
123 }
124 
125 /**
126   Writes Back the entire data cache in cache coherency domain of the calling
127   CPU.
128 
129   Writes Back the entire data cache in cache coherency domain of the calling
130   CPU. This function guarantees that all dirty cache lines are written back to
131   system memory. This function may also invalidate all the data cache lines in
132   the cache coherency domain of the calling CPU.
133 
134 **/
135 VOID
136 EFIAPI
WriteBackDataCache(VOID)137 WriteBackDataCache (
138   VOID
139   )
140 {
141   PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_NO_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);
142 }
143 
144 /**
145   Writes Back a range of data cache lines in the cache coherency domain of the
146   calling CPU.
147 
148   Writes Back the data cache lines specified by Address and Length. If Address
149   is not aligned on a cache line boundary, then entire data cache line
150   containing Address is written back. If Address + Length is not aligned on a
151   cache line boundary, then the entire data cache line containing Address +
152   Length -1 is written back. This function may choose to write back the entire
153   data cache if that is more efficient than writing back the specified range.
154   If Length is 0, then no data cache lines are written back. This function may
155   also invalidate all the data cache lines in the specified range of the cache
156   coherency domain of the calling CPU. Address is returned.
157 
158   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
159 
160   @param  Address The base address of the data cache lines to write back. If
161                   the CPU is in a physical addressing mode, then Address is a
162                   physical address. If the CPU is in a virtual addressing
163                   mode, then Address is a virtual address.
164   @param  Length  The number of bytes to write back from the data cache.
165 
166   @return Address of cache written in main memory.
167 
168 **/
169 VOID *
170 EFIAPI
WriteBackDataCacheRange(IN VOID * Address,IN UINTN Length)171 WriteBackDataCacheRange (
172   IN      VOID                      *Address,
173   IN      UINTN                     Length
174   )
175 {
176   return AsmFlushCacheRange (Address, Length);
177 }
178 
179 /**
180   Invalidates the entire data cache in cache coherency domain of the calling
181   CPU.
182 
183   Invalidates the entire data cache in cache coherency domain of the calling
184   CPU. This function must be used with care because dirty cache lines are not
185   written back to system memory. It is typically used for cache diagnostics. If
186   the CPU does not support invalidation of the entire data cache, then a write
187   back and invalidate operation should be performed on the entire data cache.
188 
189 **/
190 VOID
191 EFIAPI
InvalidateDataCache(VOID)192 InvalidateDataCache (
193   VOID
194   )
195 {
196   //
197   // Invalidation of the entire data cache without writing back is not supported
198   // on IPF architecture, so a write back and invalidate operation is performed.
199   //
200   WriteBackInvalidateDataCache ();
201 }
202 
203 /**
204   Invalidates a range of data cache lines in the cache coherency domain of the
205   calling CPU.
206 
207   Invalidates the data cache lines specified by Address and Length. If Address
208   is not aligned on a cache line boundary, then entire data cache line
209   containing Address is invalidated. If Address + Length is not aligned on a
210   cache line boundary, then the entire data cache line containing Address +
211   Length -1 is invalidated. This function must never invalidate any cache lines
212   outside the specified range. If Length is 0, then no data cache lines are
213   invalidated. Address is returned. This function must be used with care
214   because dirty cache lines are not written back to system memory. It is
215   typically used for cache diagnostics. If the CPU does not support
216   invalidation of a data cache range, then a write back and invalidate
217   operation should be performed on the data cache range.
218 
219   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
220 
221   @param  Address The base address of the data cache lines to invalidate. If
222                   the CPU is in a physical addressing mode, then Address is a
223                   physical address. If the CPU is in a virtual addressing mode,
224                   then Address is a virtual address.
225   @param  Length  The number of bytes to invalidate from the data cache.
226 
227   @return Address.
228 
229 **/
230 VOID *
231 EFIAPI
InvalidateDataCacheRange(IN VOID * Address,IN UINTN Length)232 InvalidateDataCacheRange (
233   IN      VOID                      *Address,
234   IN      UINTN                     Length
235   )
236 {
237   //
238   // Invalidation of a data cache range without writing back is not supported on
239   // IPF architecture, so write back and invalidate operation is performed.
240   //
241   return AsmFlushCacheRange (Address, Length);
242 }
243