1/**************************************************************************; 2;* *; 3;* *; 4;* Intel Corporation - ACPI Reference Code for the Sandy Bridge *; 5;* Family of Customer Reference Boards. *; 6;* *; 7;* *; 8;* Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved *; 9; 10; This program and the accompanying materials are licensed and made available under 11; the terms and conditions of the BSD License that accompanies this distribution. 12; The full text of the license may be found at 13; http://opensource.org/licenses/bsd-license.php. 14; 15; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 16; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 17; 18;* *; 19;* *; 20;**************************************************************************/ 21 22Scope(\_SB) 23{ 24//RTC 25 Device(RTC) // RTC 26 { 27 Name(_HID,EISAID("PNP0B00")) 28 29 Name(_CRS,ResourceTemplate() 30 { 31 IO(Decode16,0x70,0x70,0x01,0x08) 32 }) 33 34 Method(_STA,0,Serialized) { 35 36 // 37 // Report RTC Battery is Prensent or Not Present. 38 // 39 If (LEqual(BATT, 1)) { 40 Return (0xF) 41 } 42 Return (0x0) 43 } 44 } 45//RTC 46 47 Device(HPET) // High Performance Event Timer 48 { 49 Name (_HID, EisaId ("PNP0103")) 50 Name (_UID, 0x00) 51 Method (_STA, 0, NotSerialized) 52 { 53 Return (0x0F) 54 } 55 56 Method (_CRS, 0, Serialized) 57 { 58 Name (RBUF, ResourceTemplate () 59 { 60 Memory32Fixed (ReadWrite, 61 0xFED00000, // Address Base 62 0x00000400, // Address Length 63 ) 64 Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) 65 { 66 0x00000008, //0xB HPET-2 67 } 68 }) 69 Return (RBUF) 70 } 71 } 72//HPET 73 74 Name(PR00, Package() 75 { 76// SD Host #0 - eMMC 77 Package() {0x0010FFFF, 0, LNKA, 0 }, 78// SD Host #1 - SDIO 79 Package() {0x0011FFFF, 0, LNKB, 0 }, 80// SD Host #2 - SD Card 81 Package() {0x0012FFFF, 0, LNKC, 0 }, 82// SATA Controller 83 Package() {0x0013FFFF, 0, LNKD, 0 }, 84// xHCI Host 85 Package() {0x0014FFFF, 0, LNKE, 0 }, 86// Low Power Audio Engine 87 Package() {0x0015FFFF, 0, LNKF, 0 }, 88// USB OTG 89 Package() {0x0016FFFF, 0, LNKG, 0 }, 90// MIPI-HSI/eMMC4.5 91 Package() {0x0017FFFF, 0, LNKH, 0 }, 92// LPSS2 DMA 93// LPSS2 I2C #4 94 Package() {0x0018FFFF, 0, LNKB, 0 }, 95// LPSS2 I2C #1 96// LPSS2 I2C #5 97 Package() {0x0018FFFF, 2, LNKD, 0 }, 98// LPSS2 I2C #2 99// LPSS2 I2C #6 100 Package() {0x0018FFFF, 3, LNKC, 0 }, 101// LPSS2 I2C #3 102// LPSS2 I2C #7 103 Package() {0x0018FFFF, 1, LNKA, 0 }, 104// SeC 105 Package() {0x001AFFFF, 0, LNKF, 0 }, 106// 107// High Definition Audio Controller 108 Package() {0x001BFFFF, 0, LNKG, 0 }, 109// 110// EHCI Controller 111 Package() {0x001DFFFF, 0, LNKH, 0 }, 112// LPSS DMA 113 Package() {0x001EFFFF, 0, LNKD, 0 }, 114// LPSS I2C #0 115 Package() {0x001EFFFF, 3, LNKA, 0 }, 116// LPSS I2C #1 117 Package() {0x001EFFFF, 1, LNKB, 0 }, 118// LPSS PCM 119 Package() {0x001EFFFF, 2, LNKC, 0 }, 120// LPSS I2S 121// LPSS HS-UART #0 122// LPSS HS-UART #1 123// LPSS SPI 124// LPC Bridge 125// 126// SMBus Controller 127 Package() {0x001FFFFF, 1, LNKC, 0 }, 128// 129// PCIE Root Port #1 130 Package() {0x001CFFFF, 0, LNKA, 0 }, 131// PCIE Root Port #2 132 Package() {0x001CFFFF, 1, LNKB, 0 }, 133// PCIE Root Port #3 134 Package() {0x001CFFFF, 2, LNKC, 0 }, 135// PCIE Root Port #4 136 Package() {0x001CFFFF, 3, LNKD, 0 }, 137 138// Host Bridge 139// Mobile IGFX 140 Package() {0x0002FFFF, 0, LNKA, 0 }, 141 }) 142 143 Name(AR00, Package() 144 { 145// SD Host #0 - eMMC 146 Package() {0x0010FFFF, 0, 0, 16 }, 147// SD Host #1 - SDIO 148 Package() {0x0011FFFF, 0, 0, 17 }, 149// SD Host #2 - SD Card 150 Package() {0x0012FFFF, 0, 0, 18 }, 151// SATA Controller 152 Package() {0x0013FFFF, 0, 0, 19 }, 153// xHCI Host 154 Package() {0x0014FFFF, 0, 0, 20 }, 155// Low Power Audio Engine 156 Package() {0x0015FFFF, 0, 0, 21 }, 157// USB OTG 158 Package() {0x0016FFFF, 0, 0, 22 }, 159// 160// MIPI-HSI 161 Package() {0x0017FFFF, 0, 0, 23 }, 162// 163// LPSS2 DMA 164// LPSS2 I2C #4 165 Package() {0x0018FFFF, 0, 0, 17 }, 166// LPSS2 I2C #1 167// LPSS2 I2C #5 168 Package() {0x0018FFFF, 2, 0, 19 }, 169// LPSS2 I2C #2 170// LPSS2 I2C #6 171 Package() {0x0018FFFF, 3, 0, 18 }, 172// LPSS2 I2C #3 173// LPSS2 I2C #7 174 Package() {0x0018FFFF, 1, 0, 16 }, 175 176// SeC 177 Package() {0x001AFFFF, 0, 0, 21 }, 178// 179// High Definition Audio Controller 180 Package() {0x001BFFFF, 0, 0, 22 }, 181// 182// EHCI Controller 183 Package() {0x001DFFFF, 0, 0, 23 }, 184// LPSS DMA 185 Package() {0x001EFFFF, 0, 0, 19 }, 186// LPSS I2C #0 187 Package() {0x001EFFFF, 3, 0, 16 }, 188// LPSS I2C #1 189 Package() {0x001EFFFF, 1, 0, 17 }, 190// LPSS PCM 191 Package() {0x001EFFFF, 2, 0, 18 }, 192// LPSS I2S 193// LPSS HS-UART #0 194// LPSS HS-UART #1 195// LPSS SPI 196// LPC Bridge 197// 198// SMBus Controller 199 Package() {0x001FFFFF, 1, 0, 18 }, 200// 201// PCIE Root Port #1 202 Package() {0x001CFFFF, 0, 0, 16 }, 203// PCIE Root Port #2 204 Package() {0x001CFFFF, 1, 0, 17 }, 205// PCIE Root Port #3 206 Package() {0x001CFFFF, 2, 0, 18 }, 207// PCIE Root Port #4 208 Package() {0x001CFFFF, 3, 0, 19 }, 209// Host Bridge 210// Mobile IGFX 211 Package() {0x0002FFFF, 0, 0, 16 }, 212 }) 213 214 Name(PR04, Package() 215 { 216// PCIE Port #1 Slot 217 Package() {0x0000FFFF, 0, LNKA, 0 }, 218 Package() {0x0000FFFF, 1, LNKB, 0 }, 219 Package() {0x0000FFFF, 2, LNKC, 0 }, 220 Package() {0x0000FFFF, 3, LNKD, 0 }, 221 }) 222 223 Name(AR04, Package() 224 { 225// PCIE Port #1 Slot 226 Package() {0x0000FFFF, 0, 0, 16 }, 227 Package() {0x0000FFFF, 1, 0, 17 }, 228 Package() {0x0000FFFF, 2, 0, 18 }, 229 Package() {0x0000FFFF, 3, 0, 19 }, 230 }) 231 232 Name(PR05, Package() 233 { 234// PCIE Port #2 Slot 235 Package() {0x0000FFFF, 0, LNKB, 0 }, 236 Package() {0x0000FFFF, 1, LNKC, 0 }, 237 Package() {0x0000FFFF, 2, LNKD, 0 }, 238 Package() {0x0000FFFF, 3, LNKA, 0 }, 239 }) 240 241 Name(AR05, Package() 242 { 243// PCIE Port #2 Slot 244 Package() {0x0000FFFF, 0, 0, 17 }, 245 Package() {0x0000FFFF, 1, 0, 18 }, 246 Package() {0x0000FFFF, 2, 0, 19 }, 247 Package() {0x0000FFFF, 3, 0, 16 }, 248 }) 249 250 Name(PR06, Package() 251 { 252// PCIE Port #3 Slot 253 Package() {0x0000FFFF, 0, LNKC, 0 }, 254 Package() {0x0000FFFF, 1, LNKD, 0 }, 255 Package() {0x0000FFFF, 2, LNKA, 0 }, 256 Package() {0x0000FFFF, 3, LNKB, 0 }, 257 }) 258 259 Name(AR06, Package() 260 { 261// PCIE Port #3 Slot 262 Package() {0x0000FFFF, 0, 0, 18 }, 263 Package() {0x0000FFFF, 1, 0, 19 }, 264 Package() {0x0000FFFF, 2, 0, 16 }, 265 Package() {0x0000FFFF, 3, 0, 17 }, 266 }) 267 268 Name(PR07, Package() 269 { 270// PCIE Port #4 Slot 271 Package() {0x0000FFFF, 0, LNKD, 0 }, 272 Package() {0x0000FFFF, 1, LNKA, 0 }, 273 Package() {0x0000FFFF, 2, LNKB, 0 }, 274 Package() {0x0000FFFF, 3, LNKC, 0 }, 275 }) 276 277 Name(AR07, Package() 278 { 279// PCIE Port #4 Slot 280 Package() {0x0000FFFF, 0, 0, 19 }, 281 Package() {0x0000FFFF, 1, 0, 16 }, 282 Package() {0x0000FFFF, 2, 0, 17 }, 283 Package() {0x0000FFFF, 3, 0, 18 }, 284 }) 285 286 Name(PR01, Package() 287 { 288// PCI slot 1 289 Package() {0x0000FFFF, 0, LNKF, 0 }, 290 Package() {0x0000FFFF, 1, LNKG, 0 }, 291 Package() {0x0000FFFF, 2, LNKH, 0 }, 292 Package() {0x0000FFFF, 3, LNKE, 0 }, 293// PCI slot 2 294 Package() {0x0001FFFF, 0, LNKG, 0 }, 295 Package() {0x0001FFFF, 1, LNKF, 0 }, 296 Package() {0x0001FFFF, 2, LNKE, 0 }, 297 Package() {0x0001FFFF, 3, LNKH, 0 }, 298// PCI slot 3 299 Package() {0x0002FFFF, 0, LNKC, 0 }, 300 Package() {0x0002FFFF, 1, LNKD, 0 }, 301 Package() {0x0002FFFF, 2, LNKB, 0 }, 302 Package() {0x0002FFFF, 3, LNKA, 0 }, 303// PCI slot 4 304 Package() {0x0003FFFF, 0, LNKD, 0 }, 305 Package() {0x0003FFFF, 1, LNKC, 0 }, 306 Package() {0x0003FFFF, 2, LNKF, 0 }, 307 Package() {0x0003FFFF, 3, LNKG, 0 }, 308 }) 309 310 Name(AR01, Package() 311 { 312// PCI slot 1 313 Package() {0x0000FFFF, 0, 0, 21 }, 314 Package() {0x0000FFFF, 1, 0, 22 }, 315 Package() {0x0000FFFF, 2, 0, 23 }, 316 Package() {0x0000FFFF, 3, 0, 20 }, 317// PCI slot 2 318 Package() {0x0001FFFF, 0, 0, 22 }, 319 Package() {0x0001FFFF, 1, 0, 21 }, 320 Package() {0x0001FFFF, 2, 0, 20 }, 321 Package() {0x0001FFFF, 3, 0, 23 }, 322// PCI slot 3 323 Package() {0x0002FFFF, 0, 0, 18 }, 324 Package() {0x0002FFFF, 1, 0, 19 }, 325 Package() {0x0002FFFF, 2, 0, 17 }, 326 Package() {0x0002FFFF, 3, 0, 16 }, 327// PCI slot 4 328 Package() {0x0003FFFF, 0, 0, 19 }, 329 Package() {0x0003FFFF, 1, 0, 18 }, 330 Package() {0x0003FFFF, 2, 0, 21 }, 331 Package() {0x0003FFFF, 3, 0, 22 }, 332 }) 333//--------------------------------------------------------------------------- 334// List of IRQ resource buffers compatible with _PRS return format. 335//--------------------------------------------------------------------------- 336// Naming legend: 337// RSxy, PRSy - name of the IRQ resource buffer to be returned by _PRS, "xy" - last two characters of IRQ Link name. 338// Note. PRSy name is generated if IRQ Link name starts from "LNK". 339// HLxy , LLxy - reference names, can be used to access bit mask of available IRQs. HL and LL stand for active High(Low) Level triggered Irq model. 340//--------------------------------------------------------------------------- 341 Name(PRSA, ResourceTemplate() // Link name: LNKA 342 { 343 IRQ(Level, ActiveLow, Shared, LLKA) {3,4,5,6,10,11,12,14,15} 344 }) 345 Alias(PRSA,PRSB) // Link name: LNKB 346 Alias(PRSA,PRSC) // Link name: LNKC 347 Alias(PRSA,PRSD) // Link name: LNKD 348 Alias(PRSA,PRSE) // Link name: LNKE 349 Alias(PRSA,PRSF) // Link name: LNKF 350 Alias(PRSA,PRSG) // Link name: LNKG 351 Alias(PRSA,PRSH) // Link name: LNKH 352//--------------------------------------------------------------------------- 353// Begin PCI tree object scope 354//--------------------------------------------------------------------------- 355 356 Device(PCI0) // PCI Bridge "Host Bridge" 357 { 358 Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2 host hierarchy 359 Name(_CID, EISAID("PNP0A03")) // To support legacy OS that doesn't understand the new HID 360 Name(_ADR, 0x00000000) 361 Method(^BN00, 0) { return(0x0000) } // Returns default Bus number for Peer PCI busses. Name can be overriden with control method placed directly under Device scope 362 Method(_BBN, 0) { return(BN00()) } // Bus number, optional for the Root PCI Bus 363 Name(_UID, 0x0000) // Unique Bus ID, optional 364 Name(_DEP, Package(0x1) 365 { 366 PEPD 367 }) 368 369 Method(_PRT,0) 370 { 371 If(PICM) {Return(AR00)} // APIC mode 372 Return (PR00) // PIC Mode 373 } // end _PRT 374 375 include("HOST_BUS.ASL") 376 Device(LPCB) // LPC Bridge 377 { 378 Name(_ADR, 0x001F0000) 379 include("LpcB.asl") 380 } // end "LPC Bridge" 381 382 } // end PCI0 Bridge "Host Bridge" 383} // end _SB scope 384