1/**************************************************************************; 2;* *; 3;* *; 4;* Intel Corporation - ACPI Reference Code for the Baytrail *; 5;* Family of Customer Reference Boards. *; 6;* *; 7;* *; 8;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *; 9; 10; This program and the accompanying materials are licensed and made available under 11; the terms and conditions of the BSD License that accompanies this distribution. 12; The full text of the license may be found at 13; http://opensource.org/licenses/bsd-license.php. 14; 15; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 16; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 17; 18;* *; 19;* *; 20;**************************************************************************/ 21 22 23// Define the following External variables to prevent a WARNING when 24// using ASL.EXE and an ERROR when using IASL.EXE. 25 26External(PDC0) 27External(PDC1) 28External(PDC2) 29External(PDC3) 30External(CFGD) 31External(\_PR.CPU0._PPC, IntObj) 32External(\_SB.PCI0.LPCB.TPM.PTS, MethodObj) 33External(\_SB.STR3, DeviceObj) 34External(\_SB.I2C1.BATC, DeviceObj) 35External(\_SB.DPTF, DeviceObj) 36External(\_SB.TCHG, DeviceObj) 37External(\_SB.IAOE.PTSL) 38External(\_SB.IAOE.WKRS) 39 40// 41// Create a Global MUTEX. 42// 43Mutex(MUTX,0) 44 45 46 47// Port 80h Update: 48// Update 8 bits of the 32-bit Port 80h. 49// 50// Arguments: 51// Arg0: 0 = Write Port 80h, Bits 7:0 Only. 52// 1 = Write Port 80h, Bits 15:8 Only. 53// 2 = Write Port 80h, Bits 23:16 Only. 54// 3 = Write Port 80h, Bits 31:24 Only. 55// Arg1: 8-bit Value to write 56// 57// Return Value: 58// None 59 60Method(P8XH,2,Serialized) 61{ 62 If(LEqual(Arg0,0)) // Write Port 80h, Bits 7:0. 63 { 64 Store(Or(And(P80D,0xFFFFFF00),Arg1),P80D) 65 } 66 67 If(LEqual(Arg0,1)) // Write Port 80h, Bits 15:8. 68 { 69 Store(Or(And(P80D,0xFFFF00FF),ShiftLeft(Arg1,8)),P80D) 70 } 71 72 If(LEqual(Arg0,2)) // Write Port 80h, Bits 23:16. 73 { 74 Store(Or(And(P80D,0xFF00FFFF),ShiftLeft(Arg1,16)),P80D) 75 } 76 77 If(LEqual(Arg0,3)) // Write Port 80h, Bits 31:24. 78 { 79 Store(Or(And(P80D,0x00FFFFFF),ShiftLeft(Arg1,24)),P80D) 80 } 81 82} 83 84// 85// Define SW SMI port as an ACPI Operating Region to use for generate SW SMI. 86// 87OperationRegion (SPRT, SystemIO, 0xB2, 2) 88Field (SPRT, ByteAcc, Lock, Preserve) 89{ 90 SSMP, 8 91} 92 93// The _PIC Control Method is optional for ACPI design. It allows the 94// OS to inform the ASL code which interrupt controller is being used, 95// the 8259 or APIC. The reference code in this document will address 96// PCI IRQ Routing and resource allocation for both cases. 97// 98// The values passed into _PIC are: 99// 0 = 8259 100// 1 = IOAPIC 101 102Method(\_PIC,1) 103{ 104 Store(Arg0,GPIC) 105 Store(Arg0,PICM) 106} 107 108OperationRegion(SWC0, SystemIO, 0x610, 0x0F) 109Field(SWC0, ByteAcc, NoLock, Preserve) 110{ 111 G1S, 8, //SWC GPE1_STS 112 Offset(0x4), 113 G1E, 8, 114 Offset(0xA), 115 G1S2, 8, //SWC GPE1_STS_2 116 G1S3, 8 //SWC GPE1_STS_3 117} 118 119OperationRegion (SWC1, SystemIO, \PMBS, 0x2C) 120Field(SWC1, DWordAcc, NoLock, Preserve) 121{ 122 Offset(0x20), 123 G0S, 32, //GPE0_STS 124 Offset(0x28), 125 G0EN, 32 //GPE0_EN 126} 127 128// Prepare to Sleep. The hook is called when the OS is about to 129// enter a sleep state. The argument passed is the numeric value of 130// the Sx state. 131 132Method(_PTS,1) 133{ 134 Store(0,P80D) // Zero out the entire Port 80h DWord. 135 P8XH(0,Arg0) // Output Sleep State to Port 80h, Byte 0. 136 137 //clear the 3 SWC status bits 138 Store(Ones, G1S3) 139 Store(Ones, G1S2) 140 Store(1, G1S) 141 142 //set SWC GPE1_EN 143 Store(1,G1E) 144 145 //clear GPE0_STS 146 Store(Ones, G0S) 147 148 149 If(LEqual(Arg0,3)) // If S3 Suspend 150 { 151 // 152 // Disable Digital Thermal Sensor function when doing S3 suspend 153 // 154 If(CondRefOf(DTSE)) 155 { 156 If(LGreaterEqual(DTSE, 0x01)) 157 { 158 Store(30, DTSF) // DISABLE_UPDATE_DTS_EVERY_SMI 159 Store(0xD0, SSMP) // DTS SW SMI 160 } 161 } 162 } 163} 164 165// Wake. This hook is called when the OS is about to wake from a 166// sleep state. The argument passed is the numeric value of the 167// sleep state the system is waking from. 168Method(_WAK,1,Serialized) 169{ 170 P8XH(1,0xAB) // Beginning of _WAK. 171 172 Notify(\_SB.PWRB,0x02) 173 174 If(NEXP) 175 { 176 // Reinitialize the Native PCI Express after resume 177 If(And(OSCC,0x02)) 178 { 179 \_SB.PCI0.NHPG() 180 } 181 182 If(And(OSCC,0x04)) // PME control granted? 183 { 184 \_SB.PCI0.NPME() 185 } 186 } 187 188 If(LOr(LEqual(Arg0,3), LEqual(Arg0,4))) // If S3 or S4 Resume 189 { 190 191 192 // If CMP is enabled, we may need to restore the C-State and/or 193 // P-State configuration, as it may have been saved before the 194 // configuration was finalized based on OS/driver support. 195 // 196 // CFGD[24] = Two or more cores enabled 197 // 198 If(And(CFGD,0x01000000)) 199 { 200 // 201 // If CMP and the OSYS is WinXP SP1, we will enable C1-SMI if 202 // C-States are enabled. 203 // 204 // CFGD[7:4] = C4, C3, C2, C1 Capable/Enabled 205 // 206 // 207 } 208 209 // Windows XP SP2 does not properly restore the P-State 210 // upon resume from S4 or S3 with degrade modes enabled. 211 // Use the existing _PPC methods to cycle the available 212 // P-States such that the processor ends up running at 213 // the proper P-State. 214 // 215 // Note: For S4, another possible W/A is to always boot 216 // the system in LFM. 217 // 218 If(LEqual(OSYS,2002)) 219 { 220 If(And(CFGD,0x01)) 221 { 222 If(LGreater(\_PR.CPU0._PPC,0)) 223 { 224 Subtract(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC) 225 PNOT() 226 Add(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC) 227 PNOT() 228 } 229 Else 230 { 231 Add(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC) 232 PNOT() 233 Subtract(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC) 234 PNOT() 235 } 236 } 237 } 238 } 239 Return(Package() {0,0}) 240} 241 242// Power Notification: 243// Perform all needed OS notifications during a 244// Power Switch. 245// 246// Arguments: 247// None 248// 249// Return Value: 250// None 251 252Method(PNOT,0,Serialized) 253{ 254 // If MP enabled and driver support is present, notify all 255 // processors. 256 257 If(MPEN) 258 { 259 If(And(PDC0,0x0008)) 260 { 261 Notify(\_PR.CPU0,0x80) // Eval CPU0 _PPC. 262 263 If(And(PDC0,0x0010)) 264 { 265 Sleep(100) 266 Notify(\_PR.CPU0,0x81) // Eval _CST. 267 } 268 } 269 270 If(And(PDC1,0x0008)) 271 { 272 Notify(\_PR.CPU1,0x80) // Eval CPU1 _PPC. 273 274 If(And(PDC1,0x0010)) 275 { 276 Sleep(100) 277 Notify(\_PR.CPU1,0x81) // Eval _CST. 278 } 279 } 280 281 If(And(PDC2,0x0008)) 282 { 283 Notify(\_PR.CPU2,0x80) // Eval CPU2 _PPC. 284 285 If(And(PDC2,0x0010)) 286 { 287 Sleep(100) 288 Notify(\_PR.CPU2,0x81) // Eval _CST. 289 } 290 } 291 292 If(And(PDC3,0x0008)) 293 { 294 Notify(\_PR.CPU3,0x80) // Eval CPU3 _PPC. 295 296 If(And(PDC3,0x0010)) 297 { 298 Sleep(100) 299 Notify(\_PR.CPU3,0x81) // Eval _CST. 300 } 301 } 302 } 303 Else 304 { 305 Notify(\_PR.CPU0,0x80) // Eval _PPC. 306 Sleep(100) 307 Notify(\_PR.CPU0,0x81) // Eval _CST 308 } 309} 310 311// 312// System Bus 313// 314Scope(\_SB) 315{ 316 Name(CRTT, 110) // Processor critical temperature 317 Name(ACTT, 77) // Active temperature limit for processor participant 318 Name(GCR0, 70) // Critical temperature for Generic participant 0 in degree celsius 319 Name(GCR1, 70) // Critical temperature for Generic participant 1 in degree celsius 320 Name(GCR2, 70) // Critical temperature for Generic participant 2 in degree celsius 321 Name(GCR3, 70) // Critical temperature for Generic participant 3 in degree celsius 322 Name(GCR4, 70) // Critical temperature for Generic participant 4 in degree celsius 323 Name(GCR5, 70) // Critical temperature for Generic participant 5 in degree celsius 324 Name(GCR6, 70) // Critical temperature for Generic participant 6 in degree celsius 325 Name(PST0, 60) // Passive temperature limit for Generic Participant 0 in degree celsius 326 Name(PST1, 60) // Passive temperature limit for Generic Participant 1 in degree celsius 327 Name(PST2, 60) // Passive temperature limit for Generic Participant 2 in degree celsius 328 Name(PST3, 60) // Passive temperature limit for Generic Participant 3 in degree celsius 329 Name(PST4, 60) // Passive temperature limit for Generic Participant 4 in degree celsius 330 Name(PST5, 60) // Passive temperature limit for Generic Participant 5 in degree celsius 331 Name(PST6, 60) // Passive temperature limit for Generic Participant 6 in degree celsius 332 Name(LPMV, 3) 333 Name(PDBG, 0) // DPTF Super debug option 334 Name(PDPM, 1) // DPTF DPPM enable 335 Name(PDBP, 1) // DPTF DBPT enable (dynamic battery protection technology) 336 Name(DLPO, Package() 337 { 338 0x1, // Revision 339 0x1, // LPO Enable 340 0x1, // LPO StartPState 341 25, // LPO StepSize 342 0x1, // 343 0x1, // 344 }) 345 Name(BRQD, 0x00) // This is used to determine if DPTF display participant requested Brightness level change 346 // or it is from Graphics driver. Value of 1 is for DPTF else it is 0 347 348 Method(_INI,0) 349 { 350 // NVS has stale DTS data. Get and update the values 351 // with current temperatures. Note that this will also 352 // re-arm any AP Thermal Interrupts. 353 // Read temperature settings from global NVS 354 Store(DPCT, CRTT) 355 Store(Subtract(DPPT, 8), ACTT) // Active Trip point = Passive trip point - 8 356 Store(DGC0, GCR0) 357 Store(DGC0, GCR1) 358 Store(DGC1, GCR2) 359 Store(DGC1, GCR3) 360 Store(DGC1, GCR4) 361 Store(DGC2, GCR5) 362 Store(DGC2, GCR6) 363 Store(DGP0, PST0) 364 Store(DGP0, PST1) 365 Store(DGP1, PST2) 366 Store(DGP1, PST3) 367 Store(DGP1, PST4) 368 Store(DGP2, PST5) 369 Store(DGP2, PST6) 370 // Read Current low power mode setting from global NVS 371 Store(DLPM, LPMV) 372 373 374 // Update DPTF Super Debug option 375 Store(DDBG, PDBG) 376 377 378 // Update DPTF LPO Options 379 Store(LPOE, Index(DLPO,1)) 380 Store(LPPS, Index(DLPO,2)) 381 Store(LPST, Index(DLPO,3)) 382 Store(LPPC, Index(DLPO,4)) 383 Store(LPPF, Index(DLPO,5)) 384 Store(DPME, PDPM) 385 } 386 387 // Define a (Control Method) Power Button. 388 Device(PWRB) 389 { 390 Name(_HID,EISAID("PNP0C0C")) 391 392 // GPI_SUS0 = GPE16 = Waketime SCI. The PRW isn't working when 393 // placed in any of the logical locations ( PS2K, PS2M), 394 // so a Power Button Device was created specifically 395 // for the WAKETIME_SCI PRW. 396 397 Name(_PRW, Package() {16,4}) 398 } 399 400 Device(SLPB) 401 { 402 Name(_HID, EISAID("PNP0C0E")) 403 } // END SLPB 404 405 Scope(PCI0) 406 { 407 Method(_INI,0) 408 { 409 // Determine the OS and store the value, where: 410 // 411 // OSYS = 2009 = Windows 7 and Windows Server 2008 R2. 412 // OSYS = 2012 = Windows 8 and Windows Server 2012. 413 // 414 // Assume Windows 7 at a minimum. 415 416 Store(2009,OSYS) 417 418 // Check for a specific OS which supports _OSI. 419 420 If(CondRefOf(\_OSI,Local0)) 421 { 422 // Linux returns _OSI = TRUE for numerous Windows 423 // strings so that it is fully compatible with 424 // BIOSes available in the market today. There are 425 // currently 2 known exceptions to this model: 426 // 1) Video Repost - Linux supports S3 without 427 // requireing a Driver, meaning a Video 428 // Repost will be required. 429 // 2) On-Screen Branding - a full CMT Logo 430 // is limited to the WIN2K and WINXP 431 // Operating Systems only. 432 433 // Use OSYS for Windows Compatibility. 434 If(\_OSI("Windows 2009")) // Windows 7 or Windows Server 2008 R2 435 { 436 Store(2009,OSYS) 437 } 438 If(\_OSI("Windows 2012")) // Windows 8 or Windows Server 2012 439 { 440 Store(2012,OSYS) 441 } 442 If(\_OSI("Windows 2013")) //Windows Blue 443 { 444 Store(2013,OSYS) 445 } 446 447 // 448 // If CMP is enabled, enable SMM C-State 449 // coordination. SMM C-State coordination 450 // will be disabled in _PDC if driver support 451 // for independent C-States deeper than C1 452 // is indicated. 453 } 454 } 455 456 Method(NHPG,0,Serialized) 457 { 458 459 } 460 461 Method(NPME,0,Serialized) 462 { 463 464 } 465 } // end Scope(PCI0) 466 467 Device (GPED) //virtual GPIO device for ASL based AC/Battery/Expection notification 468 { 469 Name (_ADR, 0) 470 Name (_HID, "INT0002") 471 Name (_CID, "INT0002") 472 Name (_DDN, "Virtual GPIO controller" ) 473 Name (_UID, 1) 474 475 Method (_CRS, 0x0, Serialized) 476 { 477 Name (RBUF, ResourceTemplate () 478 { 479 Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x9} // Was 9 480 }) 481 Return (RBUF) 482 } 483 484 Method (_STA, 0x0, NotSerialized) 485 { 486 Return(0x0) 487 } 488 489 Method (_AEI, 0x0, Serialized) 490 { 491 Name(RBUF, ResourceTemplate() 492 { 493 GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullDown,,"\\_SB.GPED",) {2} //pin 2 494 }) 495 Return(RBUF) 496 } 497 498 Method(_E02) // _Exx method will be called when interrupt is raised 499 { 500 If (LEqual (PWBS, 1)) 501 { 502 Store (1, PWBS) //Clear PowerButton Status 503 } 504 If (LEqual (PMEB, 1)) 505 { 506 Store (1, PMEB) //Clear PME_B0_STS 507 } 508 If (LEqual (\_SB.PCI0.SATA.PMES, 1)) 509 { 510 Store (1, \_SB.PCI0.SATA.PMES) 511 Notify (\_SB.PCI0.SATA, 0x02) 512 } 513 // 514 // eMMC 4.41 515 // 516 If (LAnd(LEqual (\_SB.PCI0.EM41.PMES, 1), LEqual(PCIM, 1))) 517 { 518 Store (1, \_SB.PCI0.EM41.PMES) 519 Notify (\_SB.PCI0.EM41, 0x02) 520 } 521 522 // 523 // eMMC 4.5 524 // 525 If (LAnd(LEqual (\_SB.PCI0.EM45.PMES, 1), LEqual(PCIM, 1))) 526 { 527 Store (1, \_SB.PCI0.EM45.PMES) 528 Notify (\_SB.PCI0.EM45, 0x02) 529 } 530 531 If (LEqual(HDAD, 0)) 532 { 533 If (LEqual (\_SB.PCI0.HDEF.PMES, 1)) 534 { 535 Store (1, \_SB.PCI0.HDEF.PMES) 536 Notify (\_SB.PCI0.HDEF, 0x02) 537 } 538 } 539 540 If (LEqual (\_SB.PCI0.EHC1.PMES, 1)) 541 { 542 Store (1, \_SB.PCI0.EHC1.PMES) 543 Notify (\_SB.PCI0.EHC1, 0x02) 544 } 545 If (LEqual (\_SB.PCI0.XHC1.PMES, 1)) 546 { 547 Store (1, \_SB.PCI0.XHC1.PMES) 548 Notify (\_SB.PCI0.XHC1, 0x02) 549 } 550 If (LEqual (\_SB.PCI0.SEC0.PMES, 1)) 551 { 552 Or (\_SB.PCI0.SEC0.PMES, Zero, \_SB.PCI0.SEC0.PMES) 553 Notify (\_SB.PCI0.SEC0, 0x02) 554 } 555 } 556 } // Device (GPED) 557 558 //-------------------- 559 // GPIO 560 //-------------------- 561 Device (GPO0) 562 { 563 Name (_ADR, 0) 564 Name (_HID, "INT33FC") 565 Name (_CID, "INT33B2") 566 Name (_DDN, "ValleyView2 General Purpose Input/Output (GPIO) controller" ) 567 Name (_UID, 1) 568 Method (_CRS, 0x0, Serialized) 569 { 570 Name (RBUF, ResourceTemplate () 571 { 572 Memory32Fixed (ReadWrite, 0x0FED0C000, 0x00001000) 573 Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {49} 574 575 }) 576 Return (RBUF) 577 } 578 579 Method (_STA, 0x0, NotSerialized) 580 { 581 // 582 // GPO driver will report present if any of below New IO bus exist 583 // 584 If (LOr(LEqual(L11D, 0), LEqual(L12D, 0))) // LPIO1 PWM #1 or #2 exist 585 { Return(0xF) } 586 If (LOr(LEqual(L13D, 0), LEqual(L14D, 0))) // LPIO1 HS-UART #1 or #2 exist 587 { Return(0xF) } 588 If (LOr(LEqual(L15D, 0), LEqual(SD1D, 0))) // LPIO1 SPI or SCC SDIO #1 exist 589 { Return(0xF) } 590 If (LOr(LEqual(SD2D, 0), LEqual(SD3D, 0))) // SCC SDIO #2 or #3 exist 591 { Return(0xF) } 592 If (LOr(LEqual(L21D, 0), LEqual(L22D, 0))) // LPIO2 I2C #1 or #2 exist 593 { Return(0xF) } 594 If (LOr(LEqual(L23D, 0), LEqual(L24D, 0))) // LPIO2 I2C #3 or #4 exist 595 { Return(0xF) } 596 If (LOr(LEqual(L25D, 0), LEqual(L26D, 0))) // LPIO2 I2C #5 or #6 exist 597 { Return(0xF) } 598 If (LEqual(L27D, 0)) // LPIO2 I2C #7 exist 599 { Return(0xF) } 600 601 Return(0x0) 602 } 603 604 // Track status of GPIO OpRegion availability for this controller 605 Name(AVBL, 0) 606 Method(_REG,2) 607 { 608 If (Lequal(Arg0, 8)) 609 { 610 Store(Arg1, ^AVBL) 611 } 612 } 613 614 OperationRegion(GPOP, SystemIo, \GPBS, 0x50) 615 Field(GPOP, ByteAcc, NoLock, Preserve) { 616 Offset(0x28), // cfio_ioreg_SC_GP_LVL_63_32_ - [GPIO_BASE_ADDRESS] + 28h 617 , 21, 618 BTD3, 1, //This field is not used. Pin not defined in schematics. Closest is GPIO_S5_35 - COMBO_BT_WAKEUP 619 Offset(0x48), // cfio_ioreg_SC_GP_LVL_95_64_ - [GPIO_BASE_ADDRESS] + 48h 620 , 30, 621 SHD3, 1 //GPIO_S0_SC_95 - SENS_HUB_RST_N 622 } 623 624 625 626 } // Device (GPO0) 627 628 Device (GPO1) 629 { 630 Name (_ADR, 0) 631 Name (_HID, "INT33FC") 632 Name (_CID, "INT33B2") 633 Name (_DDN, "ValleyView2 GPNCORE controller" ) 634 Name (_UID, 2) 635 Method (_CRS, 0x0, Serialized) 636 { 637 Name (RBUF, ResourceTemplate () 638 { 639 Memory32Fixed (ReadWrite, 0x0FED0D000, 0x00001000) 640 Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {48} 641 }) 642 Return (RBUF) 643 } 644 645 Method (_STA, 0x0, NotSerialized) 646 { 647 Return(\_SB.GPO0._STA) 648 } 649 } // Device (GPO1) 650 651 Device (GPO2) 652 { 653 Name (_ADR, 0) 654 Name (_HID, "INT33FC") 655 Name (_CID, "INT33B2") 656 Name (_DDN, "ValleyView2 GPSUS controller" ) 657 Name (_UID, 3) 658 Method (_CRS, 0x0, Serialized) 659 { 660 Name (RBUF, ResourceTemplate () 661 { 662 Memory32Fixed (ReadWrite, 0x0FED0E000, 0x00001000) 663 Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {50} 664 }) 665 Return (RBUF) 666 } 667 668 Method (_STA, 0x0, NotSerialized) 669 { 670 Return(^^GPO0._STA) 671 } 672 673 // Track status of GPIO OpRegion availability for this controller 674 Name(AVBL, 0) 675 Method(_REG,2) 676 { 677 If (Lequal(Arg0, 8)) 678 { 679 Store(Arg1, ^AVBL) 680 } 681 } 682 //Manipulate GPIO line using GPIO operation regions. 683 Name (GMOD, ResourceTemplate () //One method of creating a Connection for OpRegion accesses in Field definitions 684 { 685 //is creating a named object that refers to the connection attributes 686 GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO2") {21} //sus 21+128 BT+WLAN_ENABLE 687 }) 688 689 OperationRegion(GPOP, SystemIo, \GPBS, 0x100) 690 Field(GPOP, ByteAcc, NoLock, Preserve) { 691 Offset(0x88), // cfio_ioreg_SUS_GP_LVL_31_0_ - [GPIO_BASE_ADDRESS] + 88h 692 , 20, 693 WFD3, 1 694 } 695 696 697 } // Device (GPO2) 698 include ("PchScc.asl") 699 include ("PchLpss.asl") 700 701 Scope(I2C7) 702 { 703 704 } //End Scope(I2C7) 705 706} // end Scope(\_SB) 707 708Name(PICM, 0) // Global Name, returns current Interrupt controller mode; updated from _PIC control method 709 710