1 /*++ 2 3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR> 4 5 6 This program and the accompanying materials are licensed and made available under 7 8 the terms and conditions of the BSD License that accompanies this distribution. 9 10 The full text of the license may be found at 11 12 http://opensource.org/licenses/bsd-license.php. 13 14 15 16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 17 18 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 19 20 21 22 23 **/ 24 25 26 #ifndef _EFI_PCI_BUS_H_ 27 #define _EFI_PCI_BUS_H_ 28 29 #include <PiDxe.h> 30 31 #include <Protocol/LoadedImage.h> 32 #include <Protocol/PciHostBridgeResourceAllocation.h> 33 #include <Protocol/PciIo.h> 34 #include <Protocol/LoadFile2.h> 35 #include <Protocol/PciRootBridgeIo.h> 36 #include <Protocol/PciHotPlugRequest.h> 37 #include <Protocol/DevicePath.h> 38 #include <Protocol/PciPlatform.h> 39 #include <Protocol/PciHotPlugInit.h> 40 #include <Protocol/Decompress.h> 41 #include <Protocol/BusSpecificDriverOverride.h> 42 #include <Protocol/IncompatiblePciDeviceSupport.h> 43 #include <Protocol/PciOverride.h> 44 #include <Protocol/PciEnumerationComplete.h> 45 46 #include <Library/DebugLib.h> 47 #include <Library/UefiDriverEntryPoint.h> 48 #include <Library/BaseLib.h> 49 #include <Library/UefiLib.h> 50 #include <Library/BaseMemoryLib.h> 51 #include <Library/ReportStatusCodeLib.h> 52 #include <Library/MemoryAllocationLib.h> 53 #include <Library/UefiBootServicesTableLib.h> 54 #include <Library/DevicePathLib.h> 55 #include <Library/PcdLib.h> 56 #include <Library/PeCoffLib.h> 57 58 #include <IndustryStandard/Pci.h> 59 #include <IndustryStandard/PeImage.h> 60 #include <IndustryStandard/Acpi.h> 61 62 typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE; 63 typedef struct _PCI_BAR PCI_BAR; 64 65 #define EFI_PCI_RID(Bus, Device, Function) (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function) 66 #define EFI_PCI_BUS_OF_RID(RID) ((UINT32)RID >> 8) 67 68 #define EFI_PCI_IOV_POLICY_ARI 0x0001 69 #define EFI_PCI_IOV_POLICY_SRIOV 0x0002 70 #define EFI_PCI_IOV_POLICY_MRIOV 0x0004 71 72 typedef enum { 73 PciBarTypeUnknown = 0, 74 PciBarTypeIo16, 75 PciBarTypeIo32, 76 PciBarTypeMem32, 77 PciBarTypePMem32, 78 PciBarTypeMem64, 79 PciBarTypePMem64, 80 PciBarTypeIo, 81 PciBarTypeMem, 82 PciBarTypeMaxType 83 } PCI_BAR_TYPE; 84 85 86 #define VGABASE1 0x3B0 87 #define VGALIMIT1 0x3BB 88 89 #define VGABASE2 0x3C0 90 #define VGALIMIT2 0x3DF 91 92 #define ISABASE 0x100 93 #define ISALIMIT 0x3FF 94 95 // 96 // PCI BAR parameters 97 // 98 struct _PCI_BAR { 99 UINT64 BaseAddress; 100 UINT64 Length; 101 UINT64 Alignment; 102 PCI_BAR_TYPE BarType; 103 BOOLEAN Prefetchable; 104 UINT8 MemType; 105 UINT16 Offset; 106 }; 107 108 // 109 // defined in PCI Card Specification, 8.0 110 // 111 #define PCI_CARD_MEMORY_BASE_0 0x1C 112 #define PCI_CARD_MEMORY_LIMIT_0 0x20 113 #define PCI_CARD_MEMORY_BASE_1 0x24 114 #define PCI_CARD_MEMORY_LIMIT_1 0x28 115 #define PCI_CARD_IO_BASE_0_LOWER 0x2C 116 #define PCI_CARD_IO_BASE_0_UPPER 0x2E 117 #define PCI_CARD_IO_LIMIT_0_LOWER 0x30 118 #define PCI_CARD_IO_LIMIT_0_UPPER 0x32 119 #define PCI_CARD_IO_BASE_1_LOWER 0x34 120 #define PCI_CARD_IO_BASE_1_UPPER 0x36 121 #define PCI_CARD_IO_LIMIT_1_LOWER 0x38 122 #define PCI_CARD_IO_LIMIT_1_UPPER 0x3A 123 #define PCI_CARD_BRIDGE_CONTROL 0x3E 124 125 #define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8 126 #define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9 127 128 #define PPB_BAR_0 0 129 #define PPB_BAR_1 1 130 #define PPB_IO_RANGE 2 131 #define PPB_MEM32_RANGE 3 132 #define PPB_PMEM32_RANGE 4 133 #define PPB_PMEM64_RANGE 5 134 #define PPB_MEM64_RANGE 0xFF 135 136 #define P2C_BAR_0 0 137 #define P2C_MEM_1 1 138 #define P2C_MEM_2 2 139 #define P2C_IO_1 3 140 #define P2C_IO_2 4 141 142 #define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001 143 #define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002 144 #define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004 145 #define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008 146 #define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010 147 #define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020 148 #define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040 149 150 #define PCI_MAX_HOST_BRIDGE_NUM 0x0010 151 152 // 153 // Define option for attribute 154 // 155 #define EFI_SET_SUPPORTS 0 156 #define EFI_SET_ATTRIBUTES 1 157 158 #define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'o') 159 160 struct _PCI_IO_DEVICE { 161 UINT32 Signature; 162 EFI_HANDLE Handle; 163 EFI_PCI_IO_PROTOCOL PciIo; 164 LIST_ENTRY Link; 165 166 EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride; 167 EFI_DEVICE_PATH_PROTOCOL *DevicePath; 168 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo; 169 EFI_LOAD_FILE2_PROTOCOL LoadFile2; 170 171 // 172 // PCI configuration space header type 173 // 174 PCI_TYPE00 Pci; 175 176 // 177 // Bus number, Device number, Function number 178 // 179 UINT8 BusNumber; 180 UINT8 DeviceNumber; 181 UINT8 FunctionNumber; 182 183 // 184 // BAR for this PCI Device 185 // 186 PCI_BAR PciBar[PCI_MAX_BAR]; 187 188 // 189 // The bridge device this pci device is subject to 190 // 191 PCI_IO_DEVICE *Parent; 192 193 // 194 // A linked list for children Pci Device if it is bridge device 195 // 196 LIST_ENTRY ChildList; 197 198 // 199 // TURE if the PCI bus driver creates the handle for this PCI device 200 // 201 BOOLEAN Registered; 202 203 // 204 // TRUE if the PCI bus driver successfully allocates the resource required by 205 // this PCI device 206 // 207 BOOLEAN Allocated; 208 209 // 210 // The attribute this PCI device currently set 211 // 212 UINT64 Attributes; 213 214 // 215 // The attributes this PCI device actually supports 216 // 217 UINT64 Supports; 218 219 // 220 // The resource decode the bridge supports 221 // 222 UINT32 Decodes; 223 224 // 225 // TRUE if the ROM image is from the PCI Option ROM BAR 226 // 227 BOOLEAN EmbeddedRom; 228 229 // 230 // The OptionRom Size 231 // 232 UINT64 RomSize; 233 234 // 235 // The OptionRom Size 236 // 237 UINT64 RomBase; 238 239 // 240 // TRUE if all OpROM (in device or in platform specific position) have been processed 241 // 242 BOOLEAN AllOpRomProcessed; 243 244 // 245 // TRUE if there is any EFI driver in the OptionRom 246 // 247 BOOLEAN BusOverride; 248 249 // 250 // A list tracking reserved resource on a bridge device 251 // 252 LIST_ENTRY ReservedResourceList; 253 254 // 255 // A list tracking image handle of platform specific overriding driver 256 // 257 LIST_ENTRY OptionRomDriverList; 258 259 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors; 260 EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes; 261 262 BOOLEAN IsPciExp; 263 264 // 265 // For SR-IOV 266 // 267 UINT8 PciExpressCapabilityOffset; 268 UINT32 AriCapabilityOffset; 269 UINT32 SrIovCapabilityOffset; 270 UINT32 MrIovCapabilityOffset; 271 PCI_BAR VfPciBar[PCI_MAX_BAR]; 272 UINT32 SystemPageSize; 273 UINT16 InitialVFs; 274 UINT16 ReservedBusNum; 275 276 // 277 // Per PCI to PCI Bridge spec, I/O window is 4K aligned, 278 // but some chipsets support non-stardard I/O window aligments less than 4K. 279 // This field is used to support this case. 280 // 281 UINT16 BridgeIoAlignment; 282 }; 283 284 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \ 285 CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE) 286 287 #define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \ 288 CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE) 289 290 #define PCI_IO_DEVICE_FROM_LINK(a) \ 291 CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE) 292 293 #define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \ 294 CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE) 295 296 297 298 // 299 // Global Variables 300 // 301 extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport; 302 extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding; 303 extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName; 304 extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2; 305 extern BOOLEAN gFullEnumeration; 306 extern UINTN gPciHostBridgeNumber; 307 extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM]; 308 extern UINT64 gAllOne; 309 extern UINT64 gAllZero; 310 extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol; 311 extern EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol; 312 extern BOOLEAN mReserveIsaAliases; 313 extern BOOLEAN mReserveVgaAliases; 314 315 /** 316 Macro that checks whether device is a GFX device. 317 318 @param _p Specified device. 319 320 @retval TRUE Device is a a GFX device. 321 @retval FALSE Device is not a a GFX device. 322 323 **/ 324 #define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER) 325 326 /** 327 Test to see if this driver supports ControllerHandle. Any ControllerHandle 328 than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported. 329 330 @param This Protocol instance pointer. 331 @param Controller Handle of device to test. 332 @param RemainingDevicePath Optional parameter use to pick a specific child. 333 device to start. 334 335 @retval EFI_SUCCESS This driver supports this device. 336 @retval EFI_ALREADY_STARTED This driver is already running on this device. 337 @retval other This driver does not support this device. 338 339 **/ 340 EFI_STATUS 341 EFIAPI 342 PciBusDriverBindingSupported ( 343 IN EFI_DRIVER_BINDING_PROTOCOL *This, 344 IN EFI_HANDLE Controller, 345 IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath 346 ); 347 348 /** 349 Start this driver on ControllerHandle and enumerate Pci bus and start 350 all device under PCI bus. 351 352 @param This Protocol instance pointer. 353 @param Controller Handle of device to bind driver to. 354 @param RemainingDevicePath Optional parameter use to pick a specific child. 355 device to start. 356 357 @retval EFI_SUCCESS This driver is added to ControllerHandle. 358 @retval EFI_ALREADY_STARTED This driver is already running on ControllerHandle. 359 @retval other This driver does not support this device. 360 361 **/ 362 EFI_STATUS 363 EFIAPI 364 PciBusDriverBindingStart ( 365 IN EFI_DRIVER_BINDING_PROTOCOL *This, 366 IN EFI_HANDLE Controller, 367 IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath 368 ); 369 370 /** 371 Stop this driver on ControllerHandle. Support stoping any child handles 372 created by this driver. 373 374 @param This Protocol instance pointer. 375 @param Controller Handle of device to stop driver on. 376 @param NumberOfChildren Number of Handles in ChildHandleBuffer. If number of 377 children is zero stop the entire bus driver. 378 @param ChildHandleBuffer List of Child Handles to Stop. 379 380 @retval EFI_SUCCESS This driver is removed ControllerHandle. 381 @retval other This driver was not removed from this device. 382 383 **/ 384 EFI_STATUS 385 EFIAPI 386 PciBusDriverBindingStop ( 387 IN EFI_DRIVER_BINDING_PROTOCOL *This, 388 IN EFI_HANDLE Controller, 389 IN UINTN NumberOfChildren, 390 IN EFI_HANDLE *ChildHandleBuffer 391 ); 392 393 #endif 394