1	.text
2
3/*
4 * The head of l-loader is defined in below.
5 * struct l_loader_head {
6 *	unsigned int	first_instr;
7 *	unsigned char	magic[16];	@ BOOTMAGICNUMBER!
8 *	unsigned int	l_loader_start;
9 *	unsigned int	l_loader_end;
10 * };
11 */
12
13#define CPU0_CTRL_OFFSET		0x100
14#define CPU7_CTRL_OFFSET		0x800
15#define CPU0_RVBARADDR_OFFSET		0x158
16#define CPU7_RVBARADDR_OFFSET		0x858
17
18#define CPU_CTRL_AARCH64_MODE		(1 << 7)
19
20#define SC_PERIPH_CLKEN3		0x230
21#define SC_PERIPH_RSTDIS3		0x334
22	.global	_start
23_start:
24	b	reset
25@ Android magic number: "BOOTMAGICNUMBER!"
26android_magic:
27	.word	0x544f4f42
28	.word	0x4947414d
29	.word	0x4d554e43
30	.word	0x21524542
31	.word	LLOADER_START		@ LLOADER_START in RAM
32	.word	0			@ LLOADER_END in RAM
33
34entries:
35	@ 5 entries with 7 words
36	.space	140
37
38	.align	7
39
40reset:
41	ldr	r8, =(0xf9800000 + 0x700)
42	str	r0, [r8]		@ download mode (1:usb,2:uart,0:boot)
43
44	ldr	r4, =0xf6504000		@ ACPU_CTRL register base
45	@ set RVBAR for cpu0
46	ldr	r5, =CPU0_RVBARADDR_OFFSET
47	ldr	r6, =LLOADER_BL1_BIN
48	mov	r6, r6, lsr #2
49	str	r6, [r4, r5]
501:
51	ldr	r0, [r4, r5]
52	cmp	r0, r6
53	bne	1b
54
55	mov	r5, #CPU0_CTRL_OFFSET
56	mov	r6, #CPU7_CTRL_OFFSET
572:
58	ldr	r0, [r4, r5]		@ Load ACPU_SC_CPUx_CTRL
59	orr	r0, r0, #CPU_CTRL_AARCH64_MODE
60	str	r0, [r4, r5]		@ Save to ACPU_SC_CPUx_CTRL
61	ldr	r0, [r4, r5]
62
63	add	r5, r5, #0x100		@ Iterate ACPU_SC_CPUx_CTRL
64	cmp	r5, r6
65	ble	2b
66
67	/*
68	 * Prepare UART2 & UART3 without baud rate initialization.
69	 * So always output on UART0 in l-loader.
70	 */
71	ldr	r4, =0xf70100e0		@ UART2_RXD IOMG register
72	mov	r0, #0
73	str	r0, [r4]
74	str	r0, [r4, #4]		@ UART2_TXD IOMG register
75	ldr	r0, [r4]
76
77	ldr	r4, =0xf7010188		@ UART3_RXD IOMG register
78	mov	r0, #1
79	str	r0, [r4]
80	str	r0, [r4, #4]		@ UART3_TXD IOMG register
81	ldr	r1, [r4]
82
83	ldr	r4, =0xf7030000		@ PERI_CTRL register base
84	@ By default, CLK_TXCO is the parent of CLK_UART3 in SC_CLK_SEL0
85
86	ldr	r5, =SC_PERIPH_RSTDIS3	@ unreset
87	ldr	r6, =SC_PERIPH_CLKEN3	@ enable PCLK
88	mov	r0, #(3 << 6)		@ bit'6' & bit'7' (UART2 & UART3)
89	str	r0, [r4, r5]
90	str	r0, [r4, r6]
91
92	@ execute warm reset to switch aarch64
93	mov	r2, #3
94	mcr	p15, 0, r2, c12, c0, 2
95	wfi
96panic:
97	b	panic
98
99str_aarch64:
100	.asciz	"\nSwitch to aarch64 mode. CPU0 executes at 0x"
101