1 //===-- R600RegisterInfo.h - R600 Register Info Interface ------*- C++ -*--===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Interface definition for R600RegisterInfo
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_R600REGISTERINFO_H
16 #define LLVM_LIB_TARGET_AMDGPU_R600REGISTERINFO_H
17 
18 #include "AMDGPURegisterInfo.h"
19 
20 namespace llvm {
21 
22 class AMDGPUSubtarget;
23 
24 struct R600RegisterInfo final : public AMDGPURegisterInfo {
25   RegClassWeight RCW;
26 
27   R600RegisterInfo();
28 
29   BitVector getReservedRegs(const MachineFunction &MF) const override;
30 
31   /// \brief get the HW encoding for a register's channel.
32   unsigned getHWRegChan(unsigned reg) const;
33 
34   unsigned getHWRegIndex(unsigned Reg) const;
35 
36   /// \brief get the register class of the specified type to use in the
37   /// CFGStructurizer
38   const TargetRegisterClass *getCFGStructurizerRegClass(MVT VT) const;
39 
40   const RegClassWeight &
41     getRegClassWeight(const TargetRegisterClass *RC) const override;
42 
43   // \returns true if \p Reg can be defined in one ALU clause and used in
44   // another.
45   bool isPhysRegLiveAcrossClauses(unsigned Reg) const;
46 
47   void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
48                            unsigned FIOperandNum,
49                            RegScavenger *RS = nullptr) const override;
50 };
51 
52 } // End namespace llvm
53 
54 #endif
55