1; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s
2
3; Stackmap Header: no constants - 6 callsites
4; CHECK-LABEL: .section	__LLVM_STACKMAPS,__llvm_stackmaps
5; CHECK-NEXT:  __LLVM_StackMaps:
6; Header
7; CHECK-NEXT:   .byte 1
8; CHECK-NEXT:   .byte 0
9; CHECK-NEXT:   .short 0
10; Num Functions
11; CHECK-NEXT:   .long 8
12; Num LargeConstants
13; CHECK-NEXT:   .long 0
14; Num Callsites
15; CHECK-NEXT:   .long 8
16
17; Functions and stack size
18; CHECK-NEXT:   .quad _test
19; CHECK-NEXT:   .quad 16
20; CHECK-NEXT:   .quad _property_access1
21; CHECK-NEXT:   .quad 16
22; CHECK-NEXT:   .quad _property_access2
23; CHECK-NEXT:   .quad 32
24; CHECK-NEXT:   .quad _property_access3
25; CHECK-NEXT:   .quad 32
26; CHECK-NEXT:   .quad _anyreg_test1
27; CHECK-NEXT:   .quad 16
28; CHECK-NEXT:   .quad _anyreg_test2
29; CHECK-NEXT:   .quad 16
30; CHECK-NEXT:   .quad _patchpoint_spilldef
31; CHECK-NEXT:   .quad 112
32; CHECK-NEXT:   .quad _patchpoint_spillargs
33; CHECK-NEXT:   .quad 128
34
35
36; test
37; CHECK-LABEL:  .long   L{{.*}}-_test
38; CHECK-NEXT:   .short  0
39; 3 locations
40; CHECK-NEXT:   .short  3
41; Loc 0: Register
42; CHECK-NEXT:   .byte 1
43; CHECK-NEXT:   .byte 4
44; CHECK-NEXT:   .short {{[0-9]+}}
45; CHECK-NEXT:   .long 0
46; Loc 1: Register
47; CHECK-NEXT:   .byte 1
48; CHECK-NEXT:   .byte 4
49; CHECK-NEXT:   .short {{[0-9]+}}
50; CHECK-NEXT:   .long 0
51; Loc 2: Constant 3
52; CHECK-NEXT:   .byte 4
53; CHECK-NEXT:   .byte 8
54; CHECK-NEXT:   .short  0
55; CHECK-NEXT:   .long 3
56define i64 @test() nounwind ssp uwtable {
57entry:
58  call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 16, i8* null, i32 2, i32 1, i32 2, i64 3)
59  ret i64 0
60}
61
62; property access 1 - %obj is an anyreg call argument and should therefore be in a register
63; CHECK-LABEL:  .long   L{{.*}}-_property_access1
64; CHECK-NEXT:   .short  0
65; 2 locations
66; CHECK-NEXT:   .short  2
67; Loc 0: Register <-- this is the return register
68; CHECK-NEXT:   .byte 1
69; CHECK-NEXT:   .byte 8
70; CHECK-NEXT:   .short {{[0-9]+}}
71; CHECK-NEXT:   .long 0
72; Loc 1: Register
73; CHECK-NEXT:   .byte 1
74; CHECK-NEXT:   .byte 8
75; CHECK-NEXT:   .short {{[0-9]+}}
76; CHECK-NEXT:   .long 0
77define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
78entry:
79  %f = inttoptr i64 281474417671919 to i8*
80  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 20, i8* %f, i32 1, i8* %obj)
81  ret i64 %ret
82}
83
84; property access 2 - %obj is an anyreg call argument and should therefore be in a register
85; CHECK-LABEL:  .long   L{{.*}}-_property_access2
86; CHECK-NEXT:   .short  0
87; 2 locations
88; CHECK-NEXT:   .short  2
89; Loc 0: Register <-- this is the return register
90; CHECK-NEXT:   .byte 1
91; CHECK-NEXT:   .byte 8
92; CHECK-NEXT:   .short {{[0-9]+}}
93; CHECK-NEXT:   .long 0
94; Loc 1: Register
95; CHECK-NEXT:   .byte 1
96; CHECK-NEXT:   .byte 8
97; CHECK-NEXT:   .short {{[0-9]+}}
98; CHECK-NEXT:   .long 0
99define i64 @property_access2() nounwind ssp uwtable {
100entry:
101  %obj = alloca i64, align 8
102  %f = inttoptr i64 281474417671919 to i8*
103  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 20, i8* %f, i32 1, i64* %obj)
104  ret i64 %ret
105}
106
107; property access 3 - %obj is a frame index
108; CHECK-LABEL:  .long   L{{.*}}-_property_access3
109; CHECK-NEXT:   .short  0
110; 2 locations
111; CHECK-NEXT:   .short  2
112; Loc 0: Register <-- this is the return register
113; CHECK-NEXT:   .byte 1
114; CHECK-NEXT:   .byte 8
115; CHECK-NEXT:   .short {{[0-9]+}}
116; CHECK-NEXT:   .long 0
117; Loc 1: Direct FP - 8
118; CHECK-NEXT:   .byte 2
119; CHECK-NEXT:   .byte 8
120; CHECK-NEXT:   .short 29
121; CHECK-NEXT:   .long -8
122define i64 @property_access3() nounwind ssp uwtable {
123entry:
124  %obj = alloca i64, align 8
125  %f = inttoptr i64 281474417671919 to i8*
126  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 20, i8* %f, i32 0, i64* %obj)
127  ret i64 %ret
128}
129
130; anyreg_test1
131; CHECK-LABEL:  .long   L{{.*}}-_anyreg_test1
132; CHECK-NEXT:   .short  0
133; 14 locations
134; CHECK-NEXT:   .short  14
135; Loc 0: Register <-- this is the return register
136; CHECK-NEXT:   .byte 1
137; CHECK-NEXT:   .byte 8
138; CHECK-NEXT:   .short {{[0-9]+}}
139; CHECK-NEXT:   .long 0
140; Loc 1: Register
141; CHECK-NEXT:   .byte 1
142; CHECK-NEXT:   .byte 8
143; CHECK-NEXT:   .short {{[0-9]+}}
144; CHECK-NEXT:   .long 0
145; Loc 2: Register
146; CHECK-NEXT:   .byte 1
147; CHECK-NEXT:   .byte 8
148; CHECK-NEXT:   .short {{[0-9]+}}
149; CHECK-NEXT:   .long 0
150; Loc 3: Register
151; CHECK-NEXT:   .byte 1
152; CHECK-NEXT:   .byte 8
153; CHECK-NEXT:   .short {{[0-9]+}}
154; CHECK-NEXT:   .long 0
155; Loc 4: Register
156; CHECK-NEXT:   .byte 1
157; CHECK-NEXT:   .byte 8
158; CHECK-NEXT:   .short {{[0-9]+}}
159; CHECK-NEXT:   .long 0
160; Loc 5: Register
161; CHECK-NEXT:   .byte 1
162; CHECK-NEXT:   .byte 8
163; CHECK-NEXT:   .short {{[0-9]+}}
164; CHECK-NEXT:   .long 0
165; Loc 6: Register
166; CHECK-NEXT:   .byte 1
167; CHECK-NEXT:   .byte 8
168; CHECK-NEXT:   .short {{[0-9]+}}
169; CHECK-NEXT:   .long 0
170; Loc 7: Register
171; CHECK-NEXT:   .byte 1
172; CHECK-NEXT:   .byte 8
173; CHECK-NEXT:   .short {{[0-9]+}}
174; CHECK-NEXT:   .long 0
175; Loc 8: Register
176; CHECK-NEXT:   .byte 1
177; CHECK-NEXT:   .byte 8
178; CHECK-NEXT:   .short {{[0-9]+}}
179; CHECK-NEXT:   .long 0
180; Loc 9: Register
181; CHECK-NEXT:   .byte 1
182; CHECK-NEXT:   .byte 8
183; CHECK-NEXT:   .short {{[0-9]+}}
184; CHECK-NEXT:   .long 0
185; Loc 10: Register
186; CHECK-NEXT:   .byte 1
187; CHECK-NEXT:   .byte 8
188; CHECK-NEXT:   .short {{[0-9]+}}
189; CHECK-NEXT:   .long 0
190; Loc 11: Register
191; CHECK-NEXT:   .byte 1
192; CHECK-NEXT:   .byte 8
193; CHECK-NEXT:   .short {{[0-9]+}}
194; CHECK-NEXT:   .long 0
195; Loc 12: Register
196; CHECK-NEXT:   .byte 1
197; CHECK-NEXT:   .byte 8
198; CHECK-NEXT:   .short {{[0-9]+}}
199; CHECK-NEXT:   .long 0
200; Loc 13: Register
201; CHECK-NEXT:   .byte 1
202; CHECK-NEXT:   .byte 8
203; CHECK-NEXT:   .short {{[0-9]+}}
204; CHECK-NEXT:   .long 0
205define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
206entry:
207  %f = inttoptr i64 281474417671919 to i8*
208  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 20, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
209  ret i64 %ret
210}
211
212; anyreg_test2
213; CHECK-LABEL:  .long   L{{.*}}-_anyreg_test2
214; CHECK-NEXT:   .short  0
215; 14 locations
216; CHECK-NEXT:   .short  14
217; Loc 0: Register <-- this is the return register
218; CHECK-NEXT:   .byte 1
219; CHECK-NEXT:   .byte 8
220; CHECK-NEXT:   .short {{[0-9]+}}
221; CHECK-NEXT:   .long 0
222; Loc 1: Register
223; CHECK-NEXT:   .byte 1
224; CHECK-NEXT:   .byte 8
225; CHECK-NEXT:   .short {{[0-9]+}}
226; CHECK-NEXT:   .long 0
227; Loc 2: Register
228; CHECK-NEXT:   .byte 1
229; CHECK-NEXT:   .byte 8
230; CHECK-NEXT:   .short {{[0-9]+}}
231; CHECK-NEXT:   .long 0
232; Loc 3: Register
233; CHECK-NEXT:   .byte 1
234; CHECK-NEXT:   .byte 8
235; CHECK-NEXT:   .short {{[0-9]+}}
236; CHECK-NEXT:   .long 0
237; Loc 4: Register
238; CHECK-NEXT:   .byte 1
239; CHECK-NEXT:   .byte 8
240; CHECK-NEXT:   .short {{[0-9]+}}
241; CHECK-NEXT:   .long 0
242; Loc 5: Register
243; CHECK-NEXT:   .byte 1
244; CHECK-NEXT:   .byte 8
245; CHECK-NEXT:   .short {{[0-9]+}}
246; CHECK-NEXT:   .long 0
247; Loc 6: Register
248; CHECK-NEXT:   .byte 1
249; CHECK-NEXT:   .byte 8
250; CHECK-NEXT:   .short {{[0-9]+}}
251; CHECK-NEXT:   .long 0
252; Loc 7: Register
253; CHECK-NEXT:   .byte 1
254; CHECK-NEXT:   .byte 8
255; CHECK-NEXT:   .short {{[0-9]+}}
256; CHECK-NEXT:   .long 0
257; Loc 8: Register
258; CHECK-NEXT:   .byte 1
259; CHECK-NEXT:   .byte 8
260; CHECK-NEXT:   .short {{[0-9]+}}
261; CHECK-NEXT:   .long 0
262; Loc 9: Register
263; CHECK-NEXT:   .byte 1
264; CHECK-NEXT:   .byte 8
265; CHECK-NEXT:   .short {{[0-9]+}}
266; CHECK-NEXT:   .long 0
267; Loc 10: Register
268; CHECK-NEXT:   .byte 1
269; CHECK-NEXT:   .byte 8
270; CHECK-NEXT:   .short {{[0-9]+}}
271; CHECK-NEXT:   .long 0
272; Loc 11: Register
273; CHECK-NEXT:   .byte 1
274; CHECK-NEXT:   .byte 8
275; CHECK-NEXT:   .short {{[0-9]+}}
276; CHECK-NEXT:   .long 0
277; Loc 12: Register
278; CHECK-NEXT:   .byte 1
279; CHECK-NEXT:   .byte 8
280; CHECK-NEXT:   .short {{[0-9]+}}
281; CHECK-NEXT:   .long 0
282; Loc 13: Register
283; CHECK-NEXT:   .byte 1
284; CHECK-NEXT:   .byte 8
285; CHECK-NEXT:   .short {{[0-9]+}}
286; CHECK-NEXT:   .long 0
287define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
288entry:
289  %f = inttoptr i64 281474417671919 to i8*
290  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
291  ret i64 %ret
292}
293
294; Test spilling the return value of an anyregcc call.
295;
296; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
297;
298; CHECK-LABEL: .long L{{.*}}-_patchpoint_spilldef
299; CHECK-NEXT: .short 0
300; CHECK-NEXT: .short 3
301; Loc 0: Register (some register that will be spilled to the stack)
302; CHECK-NEXT: .byte  1
303; CHECK-NEXT: .byte  8
304; CHECK-NEXT: .short {{[0-9]+}}
305; CHECK-NEXT: .long  0
306; Loc 1: Register
307; CHECK-NEXT: .byte  1
308; CHECK-NEXT: .byte  8
309; CHECK-NEXT: .short {{[0-9]+}}
310; CHECK-NEXT: .long  0
311; Loc 1: Register
312; CHECK-NEXT: .byte  1
313; CHECK-NEXT: .byte  8
314; CHECK-NEXT: .short {{[0-9]+}}
315; CHECK-NEXT: .long  0
316define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
317entry:
318  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
319  tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind
320  ret i64 %result
321}
322
323; Test spilling the arguments of an anyregcc call.
324;
325; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
326;
327; CHECK-LABEL: .long L{{.*}}-_patchpoint_spillargs
328; CHECK-NEXT: .short 0
329; CHECK-NEXT: .short 5
330; Loc 0: Return a register
331; CHECK-NEXT: .byte  1
332; CHECK-NEXT: .byte  8
333; CHECK-NEXT: .short {{[0-9]+}}
334; CHECK-NEXT: .long  0
335; Loc 1: Arg0 in a Register
336; CHECK-NEXT: .byte  1
337; CHECK-NEXT: .byte  8
338; CHECK-NEXT: .short {{[0-9]+}}
339; CHECK-NEXT: .long  0
340; Loc 2: Arg1 in a Register
341; CHECK-NEXT: .byte  1
342; CHECK-NEXT: .byte  8
343; CHECK-NEXT: .short {{[0-9]+}}
344; CHECK-NEXT: .long  0
345; Loc 3: Arg2 spilled to FP -96
346; CHECK-NEXT: .byte  3
347; CHECK-NEXT: .byte  8
348; CHECK-NEXT: .short 29
349; CHECK-NEXT: .long -96
350; Loc 4: Arg3 spilled to FP - 88
351; CHECK-NEXT: .byte  3
352; CHECK-NEXT: .byte  8
353; CHECK-NEXT: .short 29
354; CHECK-NEXT: .long -88
355define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
356entry:
357  tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind
358  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
359  ret i64 %result
360}
361
362declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
363declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
364