1; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
2;
3; This checks that predicate registers are moved to GPRs instead of spilling
4; where possible.
5
6; CHECK: p0 =
7; CHECK-NOT: memw(r29
8
9define i32 @f(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
10entry:
11  %cmp = icmp eq i32 %a, 1
12  %cmp1 = icmp eq i32 %b, 2
13  %or.cond = and i1 %cmp, %cmp1
14  %cmp3 = icmp eq i32 %c, 3
15  %or.cond30 = and i1 %or.cond, %cmp3
16  %cmp5 = icmp eq i32 %d, 4
17  %or.cond31 = and i1 %or.cond30, %cmp5
18  %cmp7 = icmp eq i32 %e, 5
19  %or.cond32 = and i1 %or.cond31, %cmp7
20  %ret.0 = zext i1 %or.cond32 to i32
21  %cmp8 = icmp eq i32 %a, 3
22  %cmp10 = icmp eq i32 %b, 4
23  %or.cond33 = and i1 %cmp8, %cmp10
24  %cmp12 = icmp eq i32 %c, 5
25  %or.cond34 = and i1 %or.cond33, %cmp12
26  %cmp14 = icmp eq i32 %d, 6
27  %or.cond35 = and i1 %or.cond34, %cmp14
28  %cmp16 = icmp eq i32 %e, 7
29  %or.cond36 = and i1 %or.cond35, %cmp16
30  %ret.1 = select i1 %or.cond36, i32 2, i32 %ret.0
31  %cmp21 = icmp eq i32 %b, 8
32  %or.cond37 = and i1 %cmp, %cmp21
33  %cmp23 = icmp eq i32 %c, 2
34  %or.cond38 = and i1 %or.cond37, %cmp23
35  %cmp25 = icmp eq i32 %d, 1
36  %or.cond39 = and i1 %or.cond38, %cmp25
37  %cmp27 = icmp eq i32 %e, 3
38  %or.cond40 = and i1 %or.cond39, %cmp27
39  %ret.2 = select i1 %or.cond40, i32 3, i32 %ret.1
40  ret i32 %ret.2
41}
42
43