1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: llc < %s -o - -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE
3; RUN: llc < %s -o - -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
4
5define <8 x i16> @foo(<8 x i16> %a, <8 x i16> %b) {
6; SSE-LABEL: foo:
7; SSE:       # BB#0:
8; SSE-NEXT:    pcmpeqw %xmm1, %xmm0
9; SSE-NEXT:    pand {{.*}}(%rip), %xmm0
10; SSE-NEXT:    retq
11;
12; AVX-LABEL: foo:
13; AVX:       # BB#0:
14; AVX-NEXT:    vpcmpeqw %xmm1, %xmm0, %xmm0
15; AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
16; AVX-NEXT:    retq
17;
18  %icmp = icmp eq <8 x i16> %a, %b
19  %zext = zext <8 x i1> %icmp to <8 x i16>
20  %shl = shl nuw nsw <8 x i16> %zext, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
21  ret <8 x i16> %shl
22}
23
24; Don't fail with an assert due to an undef in the buildvector
25define <8 x i16> @bar(<8 x i16> %a, <8 x i16> %b) {
26; SSE-LABEL: bar:
27; SSE:       # BB#0:
28; SSE-NEXT:    pcmpeqw %xmm1, %xmm0
29; SSE-NEXT:    psrlw $15, %xmm0
30; SSE-NEXT:    psllw $5, %xmm0
31; SSE-NEXT:    retq
32;
33; AVX-LABEL: bar:
34; AVX:       # BB#0:
35; AVX-NEXT:    vpcmpeqw %xmm1, %xmm0, %xmm0
36; AVX-NEXT:    vpsrlw $15, %xmm0, %xmm0
37; AVX-NEXT:    vpsllw $5, %xmm0, %xmm0
38; AVX-NEXT:    retq
39;
40  %icmp = icmp eq <8 x i16> %a, %b
41  %zext = zext <8 x i1> %icmp to <8 x i16>
42  %shl = shl nuw nsw <8 x i16> %zext, <i16 5, i16 undef, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
43  ret <8 x i16> %shl
44}
45
46