1; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
2
3; test vector shifts converted to proper SSE2 vector shifts when the shift
4; amounts are the same.
5
6; Note that x86 does have ashr
7
8define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
9entry:
10; CHECK-LABEL: shift1a:
11; CHECK: psrad $31
12  %ashr = ashr <2 x i64> %val, < i64 32, i64 32 >
13  store <2 x i64> %ashr, <2 x i64>* %dst
14  ret void
15}
16
17define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
18entry:
19; CHECK-LABEL: shift2a:
20; CHECK: psrad	$5
21  %ashr = ashr <4 x i32> %val, < i32 5, i32 5, i32 5, i32 5 >
22  store <4 x i32> %ashr, <4 x i32>* %dst
23  ret void
24}
25
26define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
27entry:
28; CHECK-LABEL: shift2b:
29; CHECK: movd
30; CHECK: psrad
31  %0 = insertelement <4 x i32> undef, i32 %amt, i32 0
32  %1 = insertelement <4 x i32> %0, i32 %amt, i32 1
33  %2 = insertelement <4 x i32> %1, i32 %amt, i32 2
34  %3 = insertelement <4 x i32> %2, i32 %amt, i32 3
35  %ashr = ashr <4 x i32> %val, %3
36  store <4 x i32> %ashr, <4 x i32>* %dst
37  ret void
38}
39
40define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
41entry:
42; CHECK-LABEL: shift3a:
43; CHECK: psraw	$5
44  %ashr = ashr <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
45  store <8 x i16> %ashr, <8 x i16>* %dst
46  ret void
47}
48
49define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
50entry:
51; CHECK-LABEL: shift3b:
52; CHECK: movzwl
53; CHECK: movd
54; CHECK: psraw
55  %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
56  %1 = insertelement <8 x i16> %0, i16 %amt, i32 1
57  %2 = insertelement <8 x i16> %1, i16 %amt, i32 2
58  %3 = insertelement <8 x i16> %2, i16 %amt, i32 3
59  %4 = insertelement <8 x i16> %3, i16 %amt, i32 4
60  %5 = insertelement <8 x i16> %4, i16 %amt, i32 5
61  %6 = insertelement <8 x i16> %5, i16 %amt, i32 6
62  %7 = insertelement <8 x i16> %6, i16 %amt, i32 7
63  %ashr = ashr <8 x i16> %val, %7
64  store <8 x i16> %ashr, <8 x i16>* %dst
65  ret void
66}
67