1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -instcombine -S | FileCheck %s
3
4; PR1738
5define i1 @test1(double %X, double %Y) {
6; CHECK-LABEL: @test1(
7; CHECK-NEXT:    [[TMP1:%.*]] = fcmp ord double %Y, %X
8; CHECK-NEXT:    ret i1 [[TMP1]]
9;
10  %tmp9 = fcmp ord double %X, 0.000000e+00
11  %tmp13 = fcmp ord double %Y, 0.000000e+00
12  %bothcond = and i1 %tmp13, %tmp9
13  ret i1 %bothcond
14}
15
16define i1 @test2(i1 %X, i1 %Y) {
17; CHECK-LABEL: @test2(
18; CHECK-NEXT:    [[B:%.*]] = and i1 %X, %Y
19; CHECK-NEXT:    ret i1 [[B]]
20;
21  %a = and i1 %X, %Y
22  %b = and i1 %a, %X
23  ret i1 %b
24}
25
26define i32 @test3(i32 %X, i32 %Y) {
27; CHECK-LABEL: @test3(
28; CHECK-NEXT:    [[B:%.*]] = and i32 %X, %Y
29; CHECK-NEXT:    ret i32 [[B]]
30;
31  %a = and i32 %X, %Y
32  %b = and i32 %Y, %a
33  ret i32 %b
34}
35
36; Make sure we don't go into an infinite loop with this test
37define <4 x i32> @test5(<4 x i32> %A) {
38; CHECK-LABEL: @test5(
39; CHECK-NEXT:    [[TMP1:%.*]] = xor <4 x i32> %A, <i32 1, i32 2, i32 3, i32 4>
40; CHECK-NEXT:    [[TMP2:%.*]] = and <4 x i32> [[TMP1]], <i32 1, i32 2, i32 3, i32 4>
41; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
42;
43  %1 = xor <4 x i32> %A, <i32 1, i32 2, i32 3, i32 4>
44  %2 = and <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %1
45  ret <4 x i32> %2
46}
47
48; Check that we combine "if x!=0 && x!=-1" into "if x+1u>1"
49define i32 @test6(i64 %x) nounwind {
50; CHECK-LABEL: @test6(
51; CHECK-NEXT:    [[X_OFF:%.*]] = add i64 %x, 1
52; CHECK-NEXT:    [[X_CMP:%.*]] = icmp ugt i64 [[X_OFF]], 1
53; CHECK-NEXT:    [[LAND_EXT:%.*]] = zext i1 [[X_CMP]] to i32
54; CHECK-NEXT:    ret i32 [[LAND_EXT]]
55;
56  %cmp1 = icmp ne i64 %x, -1
57  %not.cmp = icmp ne i64 %x, 0
58  %.cmp1 = and i1 %cmp1, %not.cmp
59  %land.ext = zext i1 %.cmp1 to i32
60  ret i32 %land.ext
61}
62
63define i1 @test7(i32 %i, i1 %b) {
64; CHECK-LABEL: @test7(
65; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i32 %i, 0
66; CHECK-NEXT:    [[TMP2:%.*]] = and i1 [[TMP1]], %b
67; CHECK-NEXT:    ret i1 [[TMP2]]
68;
69  %cmp1 = icmp slt i32 %i, 1
70  %cmp2 = icmp sgt i32 %i, -1
71  %and1 = and i1 %cmp1, %b
72  %and2 = and i1 %and1, %cmp2
73  ret i1 %and2
74}
75
76define i1 @test8(i32 %i) {
77; CHECK-LABEL: @test8(
78; CHECK-NEXT:    [[I_OFF:%.*]] = add i32 %i, -1
79; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i32 [[I_OFF]], 13
80; CHECK-NEXT:    ret i1 [[TMP1]]
81;
82  %cmp1 = icmp ne i32 %i, 0
83  %cmp2 = icmp ult i32 %i, 14
84  %cond = and i1 %cmp1, %cmp2
85  ret i1 %cond
86}
87
88; combine -x & 1 into x & 1
89define i64 @test9(i64 %x) {
90; CHECK-LABEL: @test9(
91; CHECK-NEXT:    [[AND:%.*]] = and i64 %x, 1
92; CHECK-NEXT:    ret i64 [[AND]]
93;
94  %sub = sub nsw i64 0, %x
95  %and = and i64 %sub, 1
96  ret i64 %and
97}
98
99define i64 @test10(i64 %x) {
100; CHECK-LABEL: @test10(
101; CHECK-NEXT:    [[AND:%.*]] = and i64 %x, 1
102; CHECK-NEXT:    [[ADD:%.*]] = sub i64 [[AND]], %x
103; CHECK-NEXT:    ret i64 [[ADD]]
104;
105  %sub = sub nsw i64 0, %x
106  %and = and i64 %sub, 1
107  %add = add i64 %sub, %and
108  ret i64 %add
109}
110
111