1; RUN: llvm-as %s -o %t.bc
2; RUN: llvm-spirv %t.bc -spirv-text -o %t.txt
3; RUN: FileCheck < %t.txt %s --check-prefix=CHECK-SPIRV
4; RUN: llvm-spirv %t.bc -o %t.spv
5; RUN: llvm-spirv -r %t.spv -o %t.rev.bc
6; RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM
7
8; CHECK-LLVM: call spir_func i32 @_Z8isfiniteDh(
9; CHECK-LLVM: call spir_func i32 @_Z5isnanDh(
10; CHECK-LLVM: call spir_func i32 @_Z5isinfDh(
11; CHECK-LLVM: call spir_func i32 @_Z8isnormalDh(
12; CHECK-LLVM: call spir_func i32 @_Z7signbitDh(
13
14; CHECK-LLVM: call spir_func <2 x i16> @_Z8isfiniteDv2_Dh(
15; CHECK-LLVM: call spir_func <2 x i16> @_Z5isnanDv2_Dh(
16; CHECK-LLVM: call spir_func <2 x i16> @_Z5isinfDv2_Dh(
17; CHECK-LLVM: call spir_func <2 x i16> @_Z8isnormalDv2_Dh(
18
19; CHECK-SPIRV: 2 TypeBool [[BoolTypeID:[0-9]+]]
20; CHECK-SPIRV: 4 TypeVector [[BoolVectorTypeID:[0-9]+]] [[BoolTypeID]] 2
21
22; CHECK-SPIRV: 4 IsFinite [[BoolTypeID]]
23; CHECK-SPIRV: 4 IsNan [[BoolTypeID]]
24; CHECK-SPIRV: 4 IsInf [[BoolTypeID]]
25; CHECK-SPIRV: 4 IsNormal [[BoolTypeID]]
26; CHECK-SPIRV: 4 SignBitSet [[BoolTypeID]]
27
28; CHECK-SPIRV: 4 IsFinite [[BoolVectorTypeID]]
29; CHECK-SPIRV: 4 IsNan [[BoolVectorTypeID]]
30; CHECK-SPIRV: 4 IsInf [[BoolVectorTypeID]]
31; CHECK-SPIRV: 4 IsNormal [[BoolVectorTypeID]]
32
33target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
34target triple = "spir-unknown-unknown"
35
36; Function Attrs: nounwind
37define spir_kernel void @test_scalar(i32 addrspace(1)* nocapture %out, half %f) #0 {
38entry:
39  %call = tail call spir_func i32 @_Z8isfiniteDh(half %f) #2
40  %call1 = tail call spir_func i32 @_Z5isnanDh(half %f) #2
41  %add = add nsw i32 %call1, %call
42  %call2 = tail call spir_func i32 @_Z5isinfDh(half %f) #2
43  %add3 = add nsw i32 %add, %call2
44  %call4 = tail call spir_func i32 @_Z8isnormalDh(half %f) #2
45  %add5 = add nsw i32 %add3, %call4
46  %call6 = tail call spir_func i32 @_Z7signbitDh(half %f) #2
47  %add7 = add nsw i32 %add5, %call6
48  store i32 %add7, i32 addrspace(1)* %out, align 4
49  ret void
50}
51
52declare spir_func i32 @_Z8isfiniteDh(half) #1
53
54declare spir_func i32 @_Z5isnanDh(half) #1
55
56declare spir_func i32 @_Z5isinfDh(half) #1
57
58declare spir_func i32 @_Z8isnormalDh(half) #1
59
60declare spir_func i32 @_Z7signbitDh(half) #1
61
62; Function Attrs: nounwind
63define spir_kernel void @test_vector(<2 x i16> addrspace(1)* nocapture %out, <2 x half> %f) #0 {
64entry:
65  %call = tail call spir_func <2 x i16> @_Z8isfiniteDv2_Dh(<2 x half> %f) #2
66  %call1 = tail call spir_func <2 x i16> @_Z5isnanDv2_Dh(<2 x half> %f) #2
67  %add = add <2 x i16> %call, %call1
68  %call2 = tail call spir_func <2 x i16> @_Z5isinfDv2_Dh(<2 x half> %f) #2
69  %add3 = add <2 x i16> %add, %call2
70  %call4 = tail call spir_func <2 x i16> @_Z8isnormalDv2_Dh(<2 x half> %f) #2
71  %add5 = add <2 x i16> %add3, %call4
72  store <2 x i16> %add5, <2 x i16> addrspace(1)* %out, align 8
73  ret void
74}
75
76declare spir_func <2 x i16> @_Z8isfiniteDv2_Dh(<2 x half>) #1
77
78declare spir_func <2 x i16> @_Z5isnanDv2_Dh(<2 x half>) #1
79
80declare spir_func <2 x i16> @_Z5isinfDv2_Dh(<2 x half>) #1
81
82declare spir_func <2 x i16> @_Z8isnormalDv2_Dh(<2 x half>) #1
83
84attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
85attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
86attributes #2 = { nounwind }
87
88!opencl.kernels = !{!0, !6}
89!opencl.enable.FP_CONTRACT = !{}
90!opencl.spir.version = !{!9}
91!opencl.ocl.version = !{!10}
92!opencl.used.extensions = !{!11}
93!opencl.used.optional.core.features = !{!11}
94!opencl.compiler.options = !{!11}
95
96!0 = !{void (i32 addrspace(1)*, half)* @test_scalar, !1, !2, !3, !4, !5}
97!1 = !{!"kernel_arg_addr_space", i32 1, i32 0}
98!2 = !{!"kernel_arg_access_qual", !"none", !"none"}
99!3 = !{!"kernel_arg_type", !"int*", !"half"}
100!4 = !{!"kernel_arg_base_type", !"int*", !"half"}
101!5 = !{!"kernel_arg_type_qual", !"", !""}
102!6 = !{void (<2 x i16> addrspace(1)*, <2 x half>)* @test_vector, !1, !2, !7, !8, !5}
103!7 = !{!"kernel_arg_type", !"short2*", !"half2"}
104!8 = !{!"kernel_arg_base_type", !"short2*", !"half2"}
105!9 = !{i32 1, i32 2}
106!10 = !{i32 2, i32 0}
107!11 = !{}
108