1; RUN: llc < %s -mtriple=thumb-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s -check-prefix=THUMB
2; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic -disable-fp-elim   | FileCheck %s -check-prefix=ARM
3; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic -disable-fp-elim -mattr=+v6t2 | FileCheck %s -check-prefix=MOVT
4; rdar://7353541
5; rdar://7354376
6; rdar://8887598
7
8; The generated code is no where near ideal. It's not recognizing the two
9; constantpool entries being loaded can be merged into one.
10
11@GV = external global i32                         ; <i32*> [#uses=2]
12
13define void @t(i32* nocapture %vals, i32 %c) nounwind {
14entry:
15; ARM: t:
16; ARM: ldr [[REGISTER_1:r[0-9]+]], LCPI0_0
17; Unfortunately currently ARM codegen doesn't cse the ldr from constantpool.
18; The issue is it can be read by an "add pc" or a "ldr [pc]" so it's messy
19; to add the pseudo instructions to make sure they are CSE'ed at the same
20; time as the "ldr cp".
21; ARM: ldr r{{[0-9]+}}, LCPI0_1
22; ARM: LPC0_0:
23; ARM: ldr r{{[0-9]+}}, [pc, [[REGISTER_1]]]
24; ARM: ldr r{{[0-9]+}}, [r{{[0-9]+}}]
25
26; MOVT: t:
27; MOVT: movw [[REGISTER_2:r[0-9]+]], :lower16:(L_GV$non_lazy_ptr-(LPC0_0+8))
28; MOVT: movt [[REGISTER_2]], :upper16:(L_GV$non_lazy_ptr-(LPC0_0+8))
29; MOVT: LPC0_0:
30; MOVT: ldr r{{[0-9]+}}, [pc, [[REGISTER_2]]]
31; MOVT: ldr r{{[0-9]+}}, [r{{[0-9]+}}]
32
33; THUMB: t:
34  %0 = icmp eq i32 %c, 0                          ; <i1> [#uses=1]
35  br i1 %0, label %return, label %bb.nph
36
37bb.nph:                                           ; preds = %entry
38; ARM: LCPI0_0:
39; ARM: LCPI0_1:
40; ARM: .section
41
42; THUMB: BB#1
43; THUMB: ldr.n r2, LCPI0_0
44; THUMB: add r2, pc
45; THUMB: ldr r{{[0-9]+}}, [r2]
46; THUMB: LBB0_2
47; THUMB: LCPI0_0:
48; THUMB-NOT: LCPI0_1:
49; THUMB: .section
50  %.pre = load i32* @GV, align 4                  ; <i32> [#uses=1]
51  br label %bb
52
53bb:                                               ; preds = %bb, %bb.nph
54  %1 = phi i32 [ %.pre, %bb.nph ], [ %3, %bb ]    ; <i32> [#uses=1]
55  %i.03 = phi i32 [ 0, %bb.nph ], [ %4, %bb ]     ; <i32> [#uses=2]
56  %scevgep = getelementptr i32* %vals, i32 %i.03  ; <i32*> [#uses=1]
57  %2 = load i32* %scevgep, align 4                ; <i32> [#uses=1]
58  %3 = add nsw i32 %1, %2                         ; <i32> [#uses=2]
59  store i32 %3, i32* @GV, align 4
60  %4 = add i32 %i.03, 1                           ; <i32> [#uses=2]
61  %exitcond = icmp eq i32 %4, %c                  ; <i1> [#uses=1]
62  br i1 %exitcond, label %return, label %bb
63
64return:                                           ; preds = %bb, %entry
65  ret void
66}
67