1; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s
2; If-conversion defeats the purpose of this test, which is to check conditional
3; branch generation, so use memory barrier instruction to make sure it doesn't
4; happen and we get actual branches.
5
6define i32 @f1(i32 %a, i32 %b, i32* %v) {
7entry:
8; CHECK: f1:
9; CHECK: bne LBB
10        %tmp = icmp eq i32 %a, %b               ; <i1> [#uses=1]
11        br i1 %tmp, label %cond_true, label %return
12
13cond_true:              ; preds = %entry
14        fence seq_cst
15        store i32 0, i32* %v
16        ret i32 0
17
18return:         ; preds = %entry
19        fence seq_cst
20        ret i32 1
21}
22
23define i32 @f2(i32 %a, i32 %b, i32* %v) {
24entry:
25; CHECK: f2:
26; CHECK: bge LBB
27        %tmp = icmp slt i32 %a, %b              ; <i1> [#uses=1]
28        br i1 %tmp, label %cond_true, label %return
29
30cond_true:              ; preds = %entry
31        fence seq_cst
32        store i32 0, i32* %v
33        ret i32 0
34
35return:         ; preds = %entry
36        fence seq_cst
37        ret i32 1
38}
39
40define i32 @f3(i32 %a, i32 %b, i32* %v) {
41entry:
42; CHECK: f3:
43; CHECK: bhs LBB
44        %tmp = icmp ult i32 %a, %b              ; <i1> [#uses=1]
45        br i1 %tmp, label %cond_true, label %return
46
47cond_true:              ; preds = %entry
48        fence seq_cst
49        store i32 0, i32* %v
50        ret i32 0
51
52return:         ; preds = %entry
53        fence seq_cst
54        ret i32 1
55}
56
57define i32 @f4(i32 %a, i32 %b, i32* %v) {
58entry:
59; CHECK: f4:
60; CHECK: blo LBB
61        %tmp = icmp ult i32 %a, %b              ; <i1> [#uses=1]
62        br i1 %tmp, label %return, label %cond_true
63
64cond_true:              ; preds = %entry
65        fence seq_cst
66        store i32 0, i32* %v
67        ret i32 0
68
69return:         ; preds = %entry
70        fence seq_cst
71        ret i32 1
72}
73