1; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86-64 -mcpu=corei7 -mattr=avx | FileCheck %s
2
3define i64 @test_x86_sse2_cvtsd2si64(<2 x double> %a0) {
4  ; CHECK: vcvtsd2si
5  %res = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %a0) ; <i64> [#uses=1]
6  ret i64 %res
7}
8declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) nounwind readnone
9
10
11define <2 x double> @test_x86_sse2_cvtsi642sd(<2 x double> %a0, i64 %a1) {
12  ; CHECK: vcvtsi2sd
13  %res = call <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double> %a0, i64 %a1) ; <<2 x double>> [#uses=1]
14  ret <2 x double> %res
15}
16declare <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double>, i64) nounwind readnone
17
18
19define i64 @test_x86_sse2_cvttsd2si64(<2 x double> %a0) {
20  ; CHECK: vcvttsd2si
21  %res = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %a0) ; <i64> [#uses=1]
22  ret i64 %res
23}
24declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) nounwind readnone
25
26
27define i64 @test_x86_sse_cvtss2si64(<4 x float> %a0) {
28  ; CHECK: vcvtss2si
29  %res = call i64 @llvm.x86.sse.cvtss2si64(<4 x float> %a0) ; <i64> [#uses=1]
30  ret i64 %res
31}
32declare i64 @llvm.x86.sse.cvtss2si64(<4 x float>) nounwind readnone
33
34
35define <4 x float> @test_x86_sse_cvtsi642ss(<4 x float> %a0, i64 %a1) {
36  ; CHECK: vcvtsi2ss
37  %res = call <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float> %a0, i64 %a1) ; <<4 x float>> [#uses=1]
38  ret <4 x float> %res
39}
40declare <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float>, i64) nounwind readnone
41
42
43define i64 @test_x86_sse_cvttss2si64(<4 x float> %a0) {
44  ; CHECK: vcvttss2si
45  %res = call i64 @llvm.x86.sse.cvttss2si64(<4 x float> %a0) ; <i64> [#uses=1]
46  ret i64 %res
47}
48declare i64 @llvm.x86.sse.cvttss2si64(<4 x float>) nounwind readnone
49
50
51