1; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
2
3;;; Shift left
4; CHECK: vpslld
5; CHECK: vpslld
6define <8 x i32> @vshift00(<8 x i32> %a) nounwind readnone {
7  %s = shl <8 x i32> %a, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32
82>
9  ret <8 x i32> %s
10}
11
12; CHECK: vpsllw
13; CHECK: vpsllw
14define <16 x i16> @vshift01(<16 x i16> %a) nounwind readnone {
15  %s = shl <16 x i16> %a, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
16  ret <16 x i16> %s
17}
18
19; CHECK: vpsllq
20; CHECK: vpsllq
21define <4 x i64> @vshift02(<4 x i64> %a) nounwind readnone {
22  %s = shl <4 x i64> %a, <i64 2, i64 2, i64 2, i64 2>
23  ret <4 x i64> %s
24}
25
26;;; Logical Shift right
27; CHECK: vpsrld
28; CHECK: vpsrld
29define <8 x i32> @vshift03(<8 x i32> %a) nounwind readnone {
30  %s = lshr <8 x i32> %a, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32
312>
32  ret <8 x i32> %s
33}
34
35; CHECK: vpsrlw
36; CHECK: vpsrlw
37define <16 x i16> @vshift04(<16 x i16> %a) nounwind readnone {
38  %s = lshr <16 x i16> %a, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
39  ret <16 x i16> %s
40}
41
42; CHECK: vpsrlq
43; CHECK: vpsrlq
44define <4 x i64> @vshift05(<4 x i64> %a) nounwind readnone {
45  %s = lshr <4 x i64> %a, <i64 2, i64 2, i64 2, i64 2>
46  ret <4 x i64> %s
47}
48
49;;; Arithmetic Shift right
50; CHECK: vpsrad
51; CHECK: vpsrad
52define <8 x i32> @vshift06(<8 x i32> %a) nounwind readnone {
53  %s = ashr <8 x i32> %a, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32
542>
55  ret <8 x i32> %s
56}
57
58; CHECK: vpsraw
59; CHECK: vpsraw
60define <16 x i16> @vshift07(<16 x i16> %a) nounwind readnone {
61  %s = ashr <16 x i16> %a, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
62  ret <16 x i16> %s
63}
64
65;;; Support variable shifts
66; CHECK: _vshift08
67; CHECK: vextractf128 $1
68; CHECK: vpslld $23
69; CHECK: vextractf128 $1
70; CHECK: vpslld $23
71define <8 x i32> @vshift08(<8 x i32> %a) nounwind {
72  %bitop = shl <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, %a
73  ret <8 x i32> %bitop
74}
75
76