1// Copyright 2016, VIXL authors
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are met:
6//
7//   * Redistributions of source code must retain the above copyright notice,
8//     this list of conditions and the following disclaimer.
9//   * Redistributions in binary form must reproduce the above copyright notice,
10//     this list of conditions and the following disclaimer in the documentation
11//     and/or other materials provided with the distribution.
12//   * Neither the name of ARM Limited nor the names of its contributors may be
13//     used to endorse or promote products derived from this software without
14//     specific prior written permission.
15//
16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
17// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
20// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
23// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27// Test description for instructions of the following form:
28//   MNEMONIC.W <Rd>, <Rn>, <Rm>
29
30{
31  "mnemonics" : [
32    "Crc32b",  // CRC32B{<q>} <Rd>, <Rn>, <Rm> ; T1
33    "Crc32cb", // CRC32CB{<q>} <Rd>, <Rn>, <Rm> ; T1
34    "Crc32ch", // CRC32CH{<q>} <Rd>, <Rn>, <Rm> ; T1
35    "Crc32cw", // CRC32CW{<q>} <Rd>, <Rn>, <Rm> ; T1
36    "Crc32h",  // CRC32H{<q>} <Rd>, <Rn>, <Rm> ; T1
37    "Crc32w"   // CRC32W{<q>} <Rd>, <Rn>, <Rm> ; T1
38  ],
39  "description" : {
40    "operands": [
41      {
42        "name": "rd",
43        "type": "AllRegistersButPC"
44      },
45      {
46        "name": "rn",
47        "type": "AllRegistersButPC"
48      },
49      {
50        "name": "rm",
51        "type": "AllRegistersButPC"
52      }
53    ],
54    "inputs": [
55      {
56        "name": "rd",
57        "type": "Register"
58      },
59      {
60        "name": "rn",
61        "type": "Register"
62      },
63      {
64        "name": "rm",
65        "type": "Register"
66      }
67    ]
68  },
69  "test-files": [
70    {
71      "type": "assembler",
72      "test-cases": [
73        {
74          "name": "Registers",
75          "operands": [
76            "rd", "rn", "rm"
77          ],
78          "operand-limit": 500
79        }
80      ]
81    },
82    {
83      "type": "simulator",
84      "test-cases": [
85        {
86          "name": "RnIsRm",
87          "operands": [
88            "rd", "rn", "rm"
89          ],
90          "inputs": [
91            "rd", "rn", "rm"
92          ],
93          "operand-filter": "rn == rm",
94          "operand-limit": 10,
95          "input-filter": "rn == rm",
96          "input-limit": 200
97        },
98        {
99          "name": "RnIsNotRm",
100          "operands": [
101            "rd", "rn", "rm"
102          ],
103          "inputs": [
104            "rd", "rn", "rm"
105          ],
106          "operand-filter": "rn != rm",
107          "operand-limit": 10,
108          "input-filter": "rn != rm",
109          "input-limit": 200
110        }
111      ]
112    }
113  ]
114}
115