1 // Copyright 2016, VIXL authors
2 // All rights reserved.
3 //
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are met:
6 //
7 // * Redistributions of source code must retain the above copyright notice,
8 // this list of conditions and the following disclaimer.
9 // * Redistributions in binary form must reproduce the above copyright notice,
10 // this list of conditions and the following disclaimer in the documentation
11 // and/or other materials provided with the distribution.
12 // * Neither the name of ARM Limited nor the names of its contributors may be
13 // used to endorse or promote products derived from this software without
14 // specific prior written permission.
15 //
16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27
28 // -----------------------------------------------------------------------------
29 // This file is auto generated from the
30 // test/aarch32/config/template-simulator-aarch32.cc.in template file using
31 // tools/generate_tests.py.
32 //
33 // PLEASE DO NOT EDIT.
34 // -----------------------------------------------------------------------------
35
36
37 #include "test-runner.h"
38
39 #include "test-utils.h"
40 #include "test-utils-aarch32.h"
41
42 #include "aarch32/assembler-aarch32.h"
43 #include "aarch32/macro-assembler-aarch32.h"
44 #include "aarch32/disasm-aarch32.h"
45
46 #define __ masm.
47 #define BUF_SIZE (4096)
48
49 #ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
50 // Run tests with the simulator.
51
52 #define SETUP() MacroAssembler masm(BUF_SIZE)
53
54 #define START() masm.GetBuffer()->Reset()
55
56 #define END() \
57 __ Hlt(0); \
58 __ FinalizeCode();
59
60 // TODO: Run the tests in the simulator.
61 #define RUN()
62
63 #define TEARDOWN()
64
65 #else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
66
67 #define SETUP() \
68 MacroAssembler masm(BUF_SIZE); \
69 UseScratchRegisterScope harness_scratch(&masm); \
70 harness_scratch.ExcludeAll();
71
72 #define START() \
73 masm.GetBuffer()->Reset(); \
74 __ Push(r4); \
75 __ Push(r5); \
76 __ Push(r6); \
77 __ Push(r7); \
78 __ Push(r8); \
79 __ Push(r9); \
80 __ Push(r10); \
81 __ Push(r11); \
82 __ Push(lr); \
83 harness_scratch.Include(ip);
84
85 #define END() \
86 harness_scratch.Exclude(ip); \
87 __ Pop(lr); \
88 __ Pop(r11); \
89 __ Pop(r10); \
90 __ Pop(r9); \
91 __ Pop(r8); \
92 __ Pop(r7); \
93 __ Pop(r6); \
94 __ Pop(r5); \
95 __ Pop(r4); \
96 __ Bx(lr); \
97 __ FinalizeCode();
98
99 #define RUN() \
100 { \
101 int pcs_offset = masm.IsUsingT32() ? 1 : 0; \
102 masm.GetBuffer()->SetExecutable(); \
103 ExecuteMemory(masm.GetBuffer()->GetStartAddress<byte*>(), \
104 masm.GetSizeOfCodeGenerated(), \
105 pcs_offset); \
106 masm.GetBuffer()->SetWritable(); \
107 }
108
109 #define TEARDOWN() harness_scratch.Close();
110
111 #endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
112
113 namespace vixl {
114 namespace aarch32 {
115
116 // List of instruction encodings:
117 #define FOREACH_INSTRUCTION(M) \
118 M(Cmn) \
119 M(Cmp) \
120 M(Mov) \
121 M(Movs) \
122 M(Mvn) \
123 M(Mvns) \
124 M(Teq) \
125 M(Tst)
126
127
128 // The following definitions are defined again in each generated test, therefore
129 // we need to place them in an anomymous namespace. It expresses that they are
130 // local to this file only, and the compiler is not allowed to share these types
131 // across test files during template instantiation. Specifically, `Operands` and
132 // `Inputs` have various layouts across generated tests so they absolutely
133 // cannot be shared.
134
135 #ifdef VIXL_INCLUDE_TARGET_A32
136 namespace {
137
138 // Values to be passed to the assembler to produce the instruction under test.
139 struct Operands {
140 Condition cond;
141 Register rd;
142 Register rn;
143 ShiftType shift;
144 uint32_t amount;
145 };
146
147 // Input data to feed to the instruction.
148 struct Inputs {
149 uint32_t apsr;
150 uint32_t rd;
151 uint32_t rn;
152 };
153
154 // This structure contains all input data needed to test one specific encoding.
155 // It used to generate a loop over an instruction.
156 struct TestLoopData {
157 // The `operands` fields represents the values to pass to the assembler to
158 // produce the instruction.
159 Operands operands;
160 // Description of the operands, used for error reporting.
161 const char* operands_description;
162 // Unique identifier, used for generating traces.
163 const char* identifier;
164 // Array of values to be fed to the instruction.
165 size_t input_size;
166 const Inputs* inputs;
167 };
168
169 static const Inputs kCondition[] = {{NFlag, 0xabababab, 0xabababab},
170 {ZFlag, 0xabababab, 0xabababab},
171 {CFlag, 0xabababab, 0xabababab},
172 {VFlag, 0xabababab, 0xabababab},
173 {NZFlag, 0xabababab, 0xabababab},
174 {NCFlag, 0xabababab, 0xabababab},
175 {NVFlag, 0xabababab, 0xabababab},
176 {ZCFlag, 0xabababab, 0xabababab},
177 {ZVFlag, 0xabababab, 0xabababab},
178 {CVFlag, 0xabababab, 0xabababab},
179 {NZCFlag, 0xabababab, 0xabababab},
180 {NZVFlag, 0xabababab, 0xabababab},
181 {NCVFlag, 0xabababab, 0xabababab},
182 {ZCVFlag, 0xabababab, 0xabababab},
183 {NZCVFlag, 0xabababab, 0xabababab}};
184
185 static const Inputs kRdIsRn[] = {{NoFlag, 0x00000000, 0x00000000},
186 {NoFlag, 0x00000001, 0x00000001},
187 {NoFlag, 0x00000002, 0x00000002},
188 {NoFlag, 0x00000020, 0x00000020},
189 {NoFlag, 0x0000007d, 0x0000007d},
190 {NoFlag, 0x0000007e, 0x0000007e},
191 {NoFlag, 0x0000007f, 0x0000007f},
192 {NoFlag, 0x00007ffd, 0x00007ffd},
193 {NoFlag, 0x00007ffe, 0x00007ffe},
194 {NoFlag, 0x00007fff, 0x00007fff},
195 {NoFlag, 0x33333333, 0x33333333},
196 {NoFlag, 0x55555555, 0x55555555},
197 {NoFlag, 0x7ffffffd, 0x7ffffffd},
198 {NoFlag, 0x7ffffffe, 0x7ffffffe},
199 {NoFlag, 0x7fffffff, 0x7fffffff},
200 {NoFlag, 0x80000000, 0x80000000},
201 {NoFlag, 0x80000001, 0x80000001},
202 {NoFlag, 0xaaaaaaaa, 0xaaaaaaaa},
203 {NoFlag, 0xcccccccc, 0xcccccccc},
204 {NoFlag, 0xffff8000, 0xffff8000},
205 {NoFlag, 0xffff8001, 0xffff8001},
206 {NoFlag, 0xffff8002, 0xffff8002},
207 {NoFlag, 0xffff8003, 0xffff8003},
208 {NoFlag, 0xffffff80, 0xffffff80},
209 {NoFlag, 0xffffff81, 0xffffff81},
210 {NoFlag, 0xffffff82, 0xffffff82},
211 {NoFlag, 0xffffff83, 0xffffff83},
212 {NoFlag, 0xffffffe0, 0xffffffe0},
213 {NoFlag, 0xfffffffd, 0xfffffffd},
214 {NoFlag, 0xfffffffe, 0xfffffffe},
215 {NoFlag, 0xffffffff, 0xffffffff}};
216
217 static const Inputs kRdIsNotRn[] = {{NoFlag, 0x00000002, 0xcccccccc},
218 {NoFlag, 0x7ffffffd, 0x00007ffe},
219 {NoFlag, 0xffffff80, 0x00000020},
220 {NoFlag, 0xaaaaaaaa, 0xaaaaaaaa},
221 {NoFlag, 0x33333333, 0xffffff82},
222 {NoFlag, 0xffff8001, 0x7ffffffe},
223 {NoFlag, 0xfffffffd, 0x00007ffe},
224 {NoFlag, 0xffffff80, 0x80000000},
225 {NoFlag, 0x00000001, 0x33333333},
226 {NoFlag, 0xcccccccc, 0x7ffffffe},
227 {NoFlag, 0x00000000, 0xcccccccc},
228 {NoFlag, 0x00000000, 0x55555555},
229 {NoFlag, 0xffffffff, 0xffffffff},
230 {NoFlag, 0x0000007e, 0xffff8002},
231 {NoFlag, 0x80000000, 0x7ffffffd},
232 {NoFlag, 0xffffff81, 0x0000007e},
233 {NoFlag, 0x0000007f, 0xffff8001},
234 {NoFlag, 0xffffffe0, 0x00007ffd},
235 {NoFlag, 0xffff8003, 0x00000002},
236 {NoFlag, 0xffffff83, 0x55555555},
237 {NoFlag, 0xffffff83, 0xffffff80},
238 {NoFlag, 0xffffff81, 0xffff8000},
239 {NoFlag, 0x00000020, 0x7ffffffe},
240 {NoFlag, 0xffffffe0, 0x00000000},
241 {NoFlag, 0x7fffffff, 0x0000007e},
242 {NoFlag, 0x80000001, 0xffffffff},
243 {NoFlag, 0x00000001, 0x80000001},
244 {NoFlag, 0x00000002, 0x0000007f},
245 {NoFlag, 0x7fffffff, 0xcccccccc},
246 {NoFlag, 0x80000001, 0x00007ffe},
247 {NoFlag, 0xffff8002, 0x0000007e},
248 {NoFlag, 0x00007ffe, 0xcccccccc},
249 {NoFlag, 0x80000000, 0xffff8002},
250 {NoFlag, 0xffffff83, 0x7ffffffe},
251 {NoFlag, 0xffff8001, 0x00000001},
252 {NoFlag, 0xffffff81, 0x00000020},
253 {NoFlag, 0xfffffffe, 0xffff8001},
254 {NoFlag, 0xffffffff, 0xfffffffe},
255 {NoFlag, 0xcccccccc, 0x55555555},
256 {NoFlag, 0x00000020, 0xffffff83},
257 {NoFlag, 0xffffff83, 0xffff8001},
258 {NoFlag, 0xffffff83, 0xffff8000},
259 {NoFlag, 0x00007fff, 0x00000002},
260 {NoFlag, 0x55555555, 0xffff8000},
261 {NoFlag, 0x80000001, 0xffffff81},
262 {NoFlag, 0x00000002, 0x00000000},
263 {NoFlag, 0x33333333, 0xffffff81},
264 {NoFlag, 0xffff8001, 0xffffff82},
265 {NoFlag, 0xcccccccc, 0xffff8003},
266 {NoFlag, 0xffff8003, 0x7ffffffd},
267 {NoFlag, 0x0000007d, 0x00007ffe},
268 {NoFlag, 0xffffff80, 0x0000007d},
269 {NoFlag, 0xaaaaaaaa, 0x00007ffd},
270 {NoFlag, 0x80000000, 0xffffff82},
271 {NoFlag, 0x00000002, 0x7ffffffe},
272 {NoFlag, 0x00000002, 0xffffff83},
273 {NoFlag, 0x55555555, 0x00000002},
274 {NoFlag, 0xffffffff, 0xffffff82},
275 {NoFlag, 0xaaaaaaaa, 0x00000020},
276 {NoFlag, 0x00000001, 0xffffff82},
277 {NoFlag, 0x0000007f, 0xffffff82},
278 {NoFlag, 0x7ffffffd, 0xaaaaaaaa},
279 {NoFlag, 0x00007ffe, 0x00000001},
280 {NoFlag, 0xfffffffd, 0xffffffe0},
281 {NoFlag, 0xffffff81, 0xffffff83},
282 {NoFlag, 0x0000007d, 0x00000000},
283 {NoFlag, 0x0000007d, 0xffff8000},
284 {NoFlag, 0xffffff81, 0x7fffffff},
285 {NoFlag, 0xffffffff, 0x80000000},
286 {NoFlag, 0x00000000, 0x00000001},
287 {NoFlag, 0x55555555, 0xffffff82},
288 {NoFlag, 0x00007ffe, 0x00007ffe},
289 {NoFlag, 0x80000001, 0xfffffffd},
290 {NoFlag, 0x00007fff, 0x33333333},
291 {NoFlag, 0x00007fff, 0x80000000},
292 {NoFlag, 0xcccccccc, 0x00007fff},
293 {NoFlag, 0xfffffffe, 0xffffffe0},
294 {NoFlag, 0x7ffffffe, 0x0000007f},
295 {NoFlag, 0x00007ffd, 0xffff8001},
296 {NoFlag, 0x00000002, 0x00000001},
297 {NoFlag, 0x80000000, 0xffffffff},
298 {NoFlag, 0xffffff83, 0xcccccccc},
299 {NoFlag, 0xffff8002, 0x7ffffffe},
300 {NoFlag, 0xaaaaaaaa, 0x00000000},
301 {NoFlag, 0xffffff80, 0xcccccccc},
302 {NoFlag, 0x33333333, 0xffffff83},
303 {NoFlag, 0x0000007e, 0xffffffe0},
304 {NoFlag, 0x0000007e, 0x00007fff},
305 {NoFlag, 0x0000007f, 0x00000002},
306 {NoFlag, 0x7ffffffe, 0xcccccccc},
307 {NoFlag, 0x0000007d, 0xffffff80},
308 {NoFlag, 0x00007fff, 0x00000020},
309 {NoFlag, 0x7ffffffe, 0xfffffffe},
310 {NoFlag, 0xfffffffe, 0xffffff81},
311 {NoFlag, 0xffffffff, 0x0000007f},
312 {NoFlag, 0xffff8002, 0x7ffffffd},
313 {NoFlag, 0xffff8001, 0xfffffffe},
314 {NoFlag, 0x33333333, 0xffff8002},
315 {NoFlag, 0x00000000, 0xffffffff},
316 {NoFlag, 0x33333333, 0xffffff80},
317 {NoFlag, 0x0000007f, 0x00007fff},
318 {NoFlag, 0xffffffff, 0xffff8001},
319 {NoFlag, 0x7fffffff, 0xffff8002},
320 {NoFlag, 0x7ffffffd, 0xffffff83},
321 {NoFlag, 0x7fffffff, 0x0000007f},
322 {NoFlag, 0xffffff83, 0xfffffffe},
323 {NoFlag, 0x7ffffffe, 0xffff8003},
324 {NoFlag, 0xffff8002, 0xffff8002},
325 {NoFlag, 0x80000001, 0x0000007f},
326 {NoFlag, 0x00000020, 0x00000002},
327 {NoFlag, 0xffffff82, 0xffff8001},
328 {NoFlag, 0xffffffff, 0x00000001},
329 {NoFlag, 0xffffff80, 0xffff8002},
330 {NoFlag, 0xffff8003, 0x7fffffff},
331 {NoFlag, 0xffffffff, 0xffff8000},
332 {NoFlag, 0xffff8002, 0x00007ffd},
333 {NoFlag, 0x00000020, 0xffffff81},
334 {NoFlag, 0x00000001, 0x55555555},
335 {NoFlag, 0x7ffffffe, 0x00000020},
336 {NoFlag, 0x80000000, 0x00000001},
337 {NoFlag, 0x00007ffd, 0xffff8002},
338 {NoFlag, 0x7fffffff, 0xfffffffe},
339 {NoFlag, 0xcccccccc, 0x00007ffd},
340 {NoFlag, 0x00000000, 0xfffffffd},
341 {NoFlag, 0xffff8003, 0xffffff80},
342 {NoFlag, 0x80000001, 0xffffff80},
343 {NoFlag, 0xffffffff, 0xffff8002},
344 {NoFlag, 0x00007ffe, 0xffff8002},
345 {NoFlag, 0xffffff80, 0x00007ffe},
346 {NoFlag, 0x80000001, 0xffff8001},
347 {NoFlag, 0x0000007f, 0xffffff80},
348 {NoFlag, 0xffffff81, 0x80000000},
349 {NoFlag, 0x00007fff, 0x00007ffe},
350 {NoFlag, 0x33333333, 0xffff8000},
351 {NoFlag, 0x33333333, 0x00007fff},
352 {NoFlag, 0x00000000, 0x0000007d},
353 {NoFlag, 0x80000001, 0x00000000},
354 {NoFlag, 0xffffffff, 0x55555555},
355 {NoFlag, 0x80000001, 0x80000000},
356 {NoFlag, 0xffffffff, 0xffffff80},
357 {NoFlag, 0xffffff81, 0xffff8003},
358 {NoFlag, 0x55555555, 0x80000001},
359 {NoFlag, 0x7fffffff, 0xffff8001},
360 {NoFlag, 0xffffff83, 0x00000002},
361 {NoFlag, 0x0000007e, 0xffffff81},
362 {NoFlag, 0x80000000, 0xffff8001},
363 {NoFlag, 0xffffff80, 0xfffffffe},
364 {NoFlag, 0x0000007e, 0xfffffffd},
365 {NoFlag, 0xffffffe0, 0xffffffff},
366 {NoFlag, 0x55555555, 0x80000000},
367 {NoFlag, 0x0000007d, 0x80000001},
368 {NoFlag, 0xffffffe0, 0x7ffffffd},
369 {NoFlag, 0x00000000, 0x00000000},
370 {NoFlag, 0x55555555, 0x00000001},
371 {NoFlag, 0x00007ffd, 0x7fffffff},
372 {NoFlag, 0x55555555, 0xffffffff},
373 {NoFlag, 0xffff8003, 0x00007fff},
374 {NoFlag, 0xffffff82, 0x00007fff},
375 {NoFlag, 0x33333333, 0x55555555},
376 {NoFlag, 0x00000020, 0x33333333},
377 {NoFlag, 0x7ffffffe, 0xfffffffd},
378 {NoFlag, 0x7ffffffe, 0x00000001},
379 {NoFlag, 0xffffff83, 0xffffffe0},
380 {NoFlag, 0xfffffffe, 0xaaaaaaaa},
381 {NoFlag, 0xffff8002, 0x33333333},
382 {NoFlag, 0xffff8002, 0xffff8003},
383 {NoFlag, 0x33333333, 0x7fffffff},
384 {NoFlag, 0xfffffffd, 0xffffff83},
385 {NoFlag, 0x00000000, 0xffff8000},
386 {NoFlag, 0xffffff82, 0x55555555},
387 {NoFlag, 0xffffff82, 0xffffff81},
388 {NoFlag, 0xcccccccc, 0xfffffffe},
389 {NoFlag, 0xfffffffd, 0x7fffffff},
390 {NoFlag, 0x00007fff, 0x7fffffff},
391 {NoFlag, 0xffffff83, 0xffff8003},
392 {NoFlag, 0xfffffffe, 0xffffffff},
393 {NoFlag, 0x7ffffffd, 0x00007ffd},
394 {NoFlag, 0x7ffffffd, 0x00007fff},
395 {NoFlag, 0x00007ffd, 0xffffffff},
396 {NoFlag, 0x00000001, 0xffff8003},
397 {NoFlag, 0xffffff80, 0xfffffffd},
398 {NoFlag, 0x33333333, 0x80000000},
399 {NoFlag, 0xffff8001, 0x00000020},
400 {NoFlag, 0xcccccccc, 0x00000002},
401 {NoFlag, 0x00000000, 0x00000002},
402 {NoFlag, 0x0000007d, 0x00007fff},
403 {NoFlag, 0xcccccccc, 0x00000001},
404 {NoFlag, 0xffffff83, 0x00007fff},
405 {NoFlag, 0x80000001, 0x00000020},
406 {NoFlag, 0xffff8003, 0xffffffe0},
407 {NoFlag, 0x00007ffd, 0xaaaaaaaa},
408 {NoFlag, 0x33333333, 0xffff8001},
409 {NoFlag, 0xffffff83, 0x80000001},
410 {NoFlag, 0xffff8000, 0xffff8000},
411 {NoFlag, 0x00007ffe, 0xffff8001},
412 {NoFlag, 0x7ffffffd, 0x00000000},
413 {NoFlag, 0x00007ffe, 0x33333333},
414 {NoFlag, 0xffff8001, 0xffffff80},
415 {NoFlag, 0xfffffffe, 0x55555555},
416 {NoFlag, 0xffffff82, 0xffffffff}};
417
418 static const Inputs kShiftTypes[] = {{NoFlag, 0xabababab, 0x00000000},
419 {NoFlag, 0xabababab, 0x00000001},
420 {NoFlag, 0xabababab, 0x00000002},
421 {NoFlag, 0xabababab, 0x00000020},
422 {NoFlag, 0xabababab, 0x0000007d},
423 {NoFlag, 0xabababab, 0x0000007e},
424 {NoFlag, 0xabababab, 0x0000007f},
425 {NoFlag, 0xabababab, 0x00007ffd},
426 {NoFlag, 0xabababab, 0x00007ffe},
427 {NoFlag, 0xabababab, 0x00007fff},
428 {NoFlag, 0xabababab, 0x33333333},
429 {NoFlag, 0xabababab, 0x55555555},
430 {NoFlag, 0xabababab, 0x7ffffffd},
431 {NoFlag, 0xabababab, 0x7ffffffe},
432 {NoFlag, 0xabababab, 0x7fffffff},
433 {NoFlag, 0xabababab, 0x80000000},
434 {NoFlag, 0xabababab, 0x80000001},
435 {NoFlag, 0xabababab, 0xaaaaaaaa},
436 {NoFlag, 0xabababab, 0xcccccccc},
437 {NoFlag, 0xabababab, 0xffff8000},
438 {NoFlag, 0xabababab, 0xffff8001},
439 {NoFlag, 0xabababab, 0xffff8002},
440 {NoFlag, 0xabababab, 0xffff8003},
441 {NoFlag, 0xabababab, 0xffffff80},
442 {NoFlag, 0xabababab, 0xffffff81},
443 {NoFlag, 0xabababab, 0xffffff82},
444 {NoFlag, 0xabababab, 0xffffff83},
445 {NoFlag, 0xabababab, 0xffffffe0},
446 {NoFlag, 0xabababab, 0xfffffffd},
447 {NoFlag, 0xabababab, 0xfffffffe},
448 {NoFlag, 0xabababab, 0xffffffff}};
449
450
451 // A loop will be generated for each element of this array.
452 const TestLoopData kTests[] = {{{eq, r0, r0, LSR, 1},
453 "eq r0 r0 LSR 1",
454 "Condition_eq_r0_r0_LSR_1",
455 ARRAY_SIZE(kCondition),
456 kCondition},
457 {{ne, r0, r0, LSR, 1},
458 "ne r0 r0 LSR 1",
459 "Condition_ne_r0_r0_LSR_1",
460 ARRAY_SIZE(kCondition),
461 kCondition},
462 {{cs, r0, r0, LSR, 1},
463 "cs r0 r0 LSR 1",
464 "Condition_cs_r0_r0_LSR_1",
465 ARRAY_SIZE(kCondition),
466 kCondition},
467 {{cc, r0, r0, LSR, 1},
468 "cc r0 r0 LSR 1",
469 "Condition_cc_r0_r0_LSR_1",
470 ARRAY_SIZE(kCondition),
471 kCondition},
472 {{mi, r0, r0, LSR, 1},
473 "mi r0 r0 LSR 1",
474 "Condition_mi_r0_r0_LSR_1",
475 ARRAY_SIZE(kCondition),
476 kCondition},
477 {{pl, r0, r0, LSR, 1},
478 "pl r0 r0 LSR 1",
479 "Condition_pl_r0_r0_LSR_1",
480 ARRAY_SIZE(kCondition),
481 kCondition},
482 {{vs, r0, r0, LSR, 1},
483 "vs r0 r0 LSR 1",
484 "Condition_vs_r0_r0_LSR_1",
485 ARRAY_SIZE(kCondition),
486 kCondition},
487 {{vc, r0, r0, LSR, 1},
488 "vc r0 r0 LSR 1",
489 "Condition_vc_r0_r0_LSR_1",
490 ARRAY_SIZE(kCondition),
491 kCondition},
492 {{hi, r0, r0, LSR, 1},
493 "hi r0 r0 LSR 1",
494 "Condition_hi_r0_r0_LSR_1",
495 ARRAY_SIZE(kCondition),
496 kCondition},
497 {{ls, r0, r0, LSR, 1},
498 "ls r0 r0 LSR 1",
499 "Condition_ls_r0_r0_LSR_1",
500 ARRAY_SIZE(kCondition),
501 kCondition},
502 {{ge, r0, r0, LSR, 1},
503 "ge r0 r0 LSR 1",
504 "Condition_ge_r0_r0_LSR_1",
505 ARRAY_SIZE(kCondition),
506 kCondition},
507 {{lt, r0, r0, LSR, 1},
508 "lt r0 r0 LSR 1",
509 "Condition_lt_r0_r0_LSR_1",
510 ARRAY_SIZE(kCondition),
511 kCondition},
512 {{gt, r0, r0, LSR, 1},
513 "gt r0 r0 LSR 1",
514 "Condition_gt_r0_r0_LSR_1",
515 ARRAY_SIZE(kCondition),
516 kCondition},
517 {{le, r0, r0, LSR, 1},
518 "le r0 r0 LSR 1",
519 "Condition_le_r0_r0_LSR_1",
520 ARRAY_SIZE(kCondition),
521 kCondition},
522 {{al, r0, r0, LSR, 1},
523 "al r0 r0 LSR 1",
524 "Condition_al_r0_r0_LSR_1",
525 ARRAY_SIZE(kCondition),
526 kCondition},
527 {{al, r0, r0, LSR, 1},
528 "al r0 r0 LSR 1",
529 "RdIsRn_al_r0_r0_LSR_1",
530 ARRAY_SIZE(kRdIsRn),
531 kRdIsRn},
532 {{al, r1, r1, LSR, 1},
533 "al r1 r1 LSR 1",
534 "RdIsRn_al_r1_r1_LSR_1",
535 ARRAY_SIZE(kRdIsRn),
536 kRdIsRn},
537 {{al, r2, r2, LSR, 1},
538 "al r2 r2 LSR 1",
539 "RdIsRn_al_r2_r2_LSR_1",
540 ARRAY_SIZE(kRdIsRn),
541 kRdIsRn},
542 {{al, r3, r3, LSR, 1},
543 "al r3 r3 LSR 1",
544 "RdIsRn_al_r3_r3_LSR_1",
545 ARRAY_SIZE(kRdIsRn),
546 kRdIsRn},
547 {{al, r4, r4, LSR, 1},
548 "al r4 r4 LSR 1",
549 "RdIsRn_al_r4_r4_LSR_1",
550 ARRAY_SIZE(kRdIsRn),
551 kRdIsRn},
552 {{al, r5, r5, LSR, 1},
553 "al r5 r5 LSR 1",
554 "RdIsRn_al_r5_r5_LSR_1",
555 ARRAY_SIZE(kRdIsRn),
556 kRdIsRn},
557 {{al, r6, r6, LSR, 1},
558 "al r6 r6 LSR 1",
559 "RdIsRn_al_r6_r6_LSR_1",
560 ARRAY_SIZE(kRdIsRn),
561 kRdIsRn},
562 {{al, r7, r7, LSR, 1},
563 "al r7 r7 LSR 1",
564 "RdIsRn_al_r7_r7_LSR_1",
565 ARRAY_SIZE(kRdIsRn),
566 kRdIsRn},
567 {{al, r8, r8, LSR, 1},
568 "al r8 r8 LSR 1",
569 "RdIsRn_al_r8_r8_LSR_1",
570 ARRAY_SIZE(kRdIsRn),
571 kRdIsRn},
572 {{al, r9, r9, LSR, 1},
573 "al r9 r9 LSR 1",
574 "RdIsRn_al_r9_r9_LSR_1",
575 ARRAY_SIZE(kRdIsRn),
576 kRdIsRn},
577 {{al, r10, r10, LSR, 1},
578 "al r10 r10 LSR 1",
579 "RdIsRn_al_r10_r10_LSR_1",
580 ARRAY_SIZE(kRdIsRn),
581 kRdIsRn},
582 {{al, r11, r11, LSR, 1},
583 "al r11 r11 LSR 1",
584 "RdIsRn_al_r11_r11_LSR_1",
585 ARRAY_SIZE(kRdIsRn),
586 kRdIsRn},
587 {{al, r12, r12, LSR, 1},
588 "al r12 r12 LSR 1",
589 "RdIsRn_al_r12_r12_LSR_1",
590 ARRAY_SIZE(kRdIsRn),
591 kRdIsRn},
592 {{al, r14, r14, LSR, 1},
593 "al r14 r14 LSR 1",
594 "RdIsRn_al_r14_r14_LSR_1",
595 ARRAY_SIZE(kRdIsRn),
596 kRdIsRn},
597 {{al, r1, r8, LSR, 1},
598 "al r1 r8 LSR 1",
599 "RdIsNotRn_al_r1_r8_LSR_1",
600 ARRAY_SIZE(kRdIsNotRn),
601 kRdIsNotRn},
602 {{al, r7, r4, LSR, 1},
603 "al r7 r4 LSR 1",
604 "RdIsNotRn_al_r7_r4_LSR_1",
605 ARRAY_SIZE(kRdIsNotRn),
606 kRdIsNotRn},
607 {{al, r14, r10, LSR, 1},
608 "al r14 r10 LSR 1",
609 "RdIsNotRn_al_r14_r10_LSR_1",
610 ARRAY_SIZE(kRdIsNotRn),
611 kRdIsNotRn},
612 {{al, r10, r6, LSR, 1},
613 "al r10 r6 LSR 1",
614 "RdIsNotRn_al_r10_r6_LSR_1",
615 ARRAY_SIZE(kRdIsNotRn),
616 kRdIsNotRn},
617 {{al, r6, r5, LSR, 1},
618 "al r6 r5 LSR 1",
619 "RdIsNotRn_al_r6_r5_LSR_1",
620 ARRAY_SIZE(kRdIsNotRn),
621 kRdIsNotRn},
622 {{al, r12, r2, LSR, 1},
623 "al r12 r2 LSR 1",
624 "RdIsNotRn_al_r12_r2_LSR_1",
625 ARRAY_SIZE(kRdIsNotRn),
626 kRdIsNotRn},
627 {{al, r0, r11, LSR, 1},
628 "al r0 r11 LSR 1",
629 "RdIsNotRn_al_r0_r11_LSR_1",
630 ARRAY_SIZE(kRdIsNotRn),
631 kRdIsNotRn},
632 {{al, r10, r14, LSR, 1},
633 "al r10 r14 LSR 1",
634 "RdIsNotRn_al_r10_r14_LSR_1",
635 ARRAY_SIZE(kRdIsNotRn),
636 kRdIsNotRn},
637 {{al, r0, r5, LSR, 1},
638 "al r0 r5 LSR 1",
639 "RdIsNotRn_al_r0_r5_LSR_1",
640 ARRAY_SIZE(kRdIsNotRn),
641 kRdIsNotRn},
642 {{al, r0, r3, LSR, 1},
643 "al r0 r3 LSR 1",
644 "RdIsNotRn_al_r0_r3_LSR_1",
645 ARRAY_SIZE(kRdIsNotRn),
646 kRdIsNotRn},
647 {{al, r0, r0, LSR, 1},
648 "al r0 r0 LSR 1",
649 "ShiftTypes_al_r0_r0_LSR_1",
650 ARRAY_SIZE(kShiftTypes),
651 kShiftTypes},
652 {{al, r0, r0, LSR, 2},
653 "al r0 r0 LSR 2",
654 "ShiftTypes_al_r0_r0_LSR_2",
655 ARRAY_SIZE(kShiftTypes),
656 kShiftTypes},
657 {{al, r0, r0, LSR, 3},
658 "al r0 r0 LSR 3",
659 "ShiftTypes_al_r0_r0_LSR_3",
660 ARRAY_SIZE(kShiftTypes),
661 kShiftTypes},
662 {{al, r0, r0, LSR, 4},
663 "al r0 r0 LSR 4",
664 "ShiftTypes_al_r0_r0_LSR_4",
665 ARRAY_SIZE(kShiftTypes),
666 kShiftTypes},
667 {{al, r0, r0, LSR, 5},
668 "al r0 r0 LSR 5",
669 "ShiftTypes_al_r0_r0_LSR_5",
670 ARRAY_SIZE(kShiftTypes),
671 kShiftTypes},
672 {{al, r0, r0, LSR, 6},
673 "al r0 r0 LSR 6",
674 "ShiftTypes_al_r0_r0_LSR_6",
675 ARRAY_SIZE(kShiftTypes),
676 kShiftTypes},
677 {{al, r0, r0, LSR, 7},
678 "al r0 r0 LSR 7",
679 "ShiftTypes_al_r0_r0_LSR_7",
680 ARRAY_SIZE(kShiftTypes),
681 kShiftTypes},
682 {{al, r0, r0, LSR, 8},
683 "al r0 r0 LSR 8",
684 "ShiftTypes_al_r0_r0_LSR_8",
685 ARRAY_SIZE(kShiftTypes),
686 kShiftTypes},
687 {{al, r0, r0, LSR, 9},
688 "al r0 r0 LSR 9",
689 "ShiftTypes_al_r0_r0_LSR_9",
690 ARRAY_SIZE(kShiftTypes),
691 kShiftTypes},
692 {{al, r0, r0, LSR, 10},
693 "al r0 r0 LSR 10",
694 "ShiftTypes_al_r0_r0_LSR_10",
695 ARRAY_SIZE(kShiftTypes),
696 kShiftTypes},
697 {{al, r0, r0, LSR, 11},
698 "al r0 r0 LSR 11",
699 "ShiftTypes_al_r0_r0_LSR_11",
700 ARRAY_SIZE(kShiftTypes),
701 kShiftTypes},
702 {{al, r0, r0, LSR, 12},
703 "al r0 r0 LSR 12",
704 "ShiftTypes_al_r0_r0_LSR_12",
705 ARRAY_SIZE(kShiftTypes),
706 kShiftTypes},
707 {{al, r0, r0, LSR, 13},
708 "al r0 r0 LSR 13",
709 "ShiftTypes_al_r0_r0_LSR_13",
710 ARRAY_SIZE(kShiftTypes),
711 kShiftTypes},
712 {{al, r0, r0, LSR, 14},
713 "al r0 r0 LSR 14",
714 "ShiftTypes_al_r0_r0_LSR_14",
715 ARRAY_SIZE(kShiftTypes),
716 kShiftTypes},
717 {{al, r0, r0, LSR, 15},
718 "al r0 r0 LSR 15",
719 "ShiftTypes_al_r0_r0_LSR_15",
720 ARRAY_SIZE(kShiftTypes),
721 kShiftTypes},
722 {{al, r0, r0, LSR, 16},
723 "al r0 r0 LSR 16",
724 "ShiftTypes_al_r0_r0_LSR_16",
725 ARRAY_SIZE(kShiftTypes),
726 kShiftTypes},
727 {{al, r0, r0, LSR, 17},
728 "al r0 r0 LSR 17",
729 "ShiftTypes_al_r0_r0_LSR_17",
730 ARRAY_SIZE(kShiftTypes),
731 kShiftTypes},
732 {{al, r0, r0, LSR, 18},
733 "al r0 r0 LSR 18",
734 "ShiftTypes_al_r0_r0_LSR_18",
735 ARRAY_SIZE(kShiftTypes),
736 kShiftTypes},
737 {{al, r0, r0, LSR, 19},
738 "al r0 r0 LSR 19",
739 "ShiftTypes_al_r0_r0_LSR_19",
740 ARRAY_SIZE(kShiftTypes),
741 kShiftTypes},
742 {{al, r0, r0, LSR, 20},
743 "al r0 r0 LSR 20",
744 "ShiftTypes_al_r0_r0_LSR_20",
745 ARRAY_SIZE(kShiftTypes),
746 kShiftTypes},
747 {{al, r0, r0, LSR, 21},
748 "al r0 r0 LSR 21",
749 "ShiftTypes_al_r0_r0_LSR_21",
750 ARRAY_SIZE(kShiftTypes),
751 kShiftTypes},
752 {{al, r0, r0, LSR, 22},
753 "al r0 r0 LSR 22",
754 "ShiftTypes_al_r0_r0_LSR_22",
755 ARRAY_SIZE(kShiftTypes),
756 kShiftTypes},
757 {{al, r0, r0, LSR, 23},
758 "al r0 r0 LSR 23",
759 "ShiftTypes_al_r0_r0_LSR_23",
760 ARRAY_SIZE(kShiftTypes),
761 kShiftTypes},
762 {{al, r0, r0, LSR, 24},
763 "al r0 r0 LSR 24",
764 "ShiftTypes_al_r0_r0_LSR_24",
765 ARRAY_SIZE(kShiftTypes),
766 kShiftTypes},
767 {{al, r0, r0, LSR, 25},
768 "al r0 r0 LSR 25",
769 "ShiftTypes_al_r0_r0_LSR_25",
770 ARRAY_SIZE(kShiftTypes),
771 kShiftTypes},
772 {{al, r0, r0, LSR, 26},
773 "al r0 r0 LSR 26",
774 "ShiftTypes_al_r0_r0_LSR_26",
775 ARRAY_SIZE(kShiftTypes),
776 kShiftTypes},
777 {{al, r0, r0, LSR, 27},
778 "al r0 r0 LSR 27",
779 "ShiftTypes_al_r0_r0_LSR_27",
780 ARRAY_SIZE(kShiftTypes),
781 kShiftTypes},
782 {{al, r0, r0, LSR, 28},
783 "al r0 r0 LSR 28",
784 "ShiftTypes_al_r0_r0_LSR_28",
785 ARRAY_SIZE(kShiftTypes),
786 kShiftTypes},
787 {{al, r0, r0, LSR, 29},
788 "al r0 r0 LSR 29",
789 "ShiftTypes_al_r0_r0_LSR_29",
790 ARRAY_SIZE(kShiftTypes),
791 kShiftTypes},
792 {{al, r0, r0, LSR, 30},
793 "al r0 r0 LSR 30",
794 "ShiftTypes_al_r0_r0_LSR_30",
795 ARRAY_SIZE(kShiftTypes),
796 kShiftTypes},
797 {{al, r0, r0, LSR, 31},
798 "al r0 r0 LSR 31",
799 "ShiftTypes_al_r0_r0_LSR_31",
800 ARRAY_SIZE(kShiftTypes),
801 kShiftTypes},
802 {{al, r0, r0, LSR, 32},
803 "al r0 r0 LSR 32",
804 "ShiftTypes_al_r0_r0_LSR_32",
805 ARRAY_SIZE(kShiftTypes),
806 kShiftTypes},
807 {{al, r0, r0, ASR, 1},
808 "al r0 r0 ASR 1",
809 "ShiftTypes_al_r0_r0_ASR_1",
810 ARRAY_SIZE(kShiftTypes),
811 kShiftTypes},
812 {{al, r0, r0, ASR, 2},
813 "al r0 r0 ASR 2",
814 "ShiftTypes_al_r0_r0_ASR_2",
815 ARRAY_SIZE(kShiftTypes),
816 kShiftTypes},
817 {{al, r0, r0, ASR, 3},
818 "al r0 r0 ASR 3",
819 "ShiftTypes_al_r0_r0_ASR_3",
820 ARRAY_SIZE(kShiftTypes),
821 kShiftTypes},
822 {{al, r0, r0, ASR, 4},
823 "al r0 r0 ASR 4",
824 "ShiftTypes_al_r0_r0_ASR_4",
825 ARRAY_SIZE(kShiftTypes),
826 kShiftTypes},
827 {{al, r0, r0, ASR, 5},
828 "al r0 r0 ASR 5",
829 "ShiftTypes_al_r0_r0_ASR_5",
830 ARRAY_SIZE(kShiftTypes),
831 kShiftTypes},
832 {{al, r0, r0, ASR, 6},
833 "al r0 r0 ASR 6",
834 "ShiftTypes_al_r0_r0_ASR_6",
835 ARRAY_SIZE(kShiftTypes),
836 kShiftTypes},
837 {{al, r0, r0, ASR, 7},
838 "al r0 r0 ASR 7",
839 "ShiftTypes_al_r0_r0_ASR_7",
840 ARRAY_SIZE(kShiftTypes),
841 kShiftTypes},
842 {{al, r0, r0, ASR, 8},
843 "al r0 r0 ASR 8",
844 "ShiftTypes_al_r0_r0_ASR_8",
845 ARRAY_SIZE(kShiftTypes),
846 kShiftTypes},
847 {{al, r0, r0, ASR, 9},
848 "al r0 r0 ASR 9",
849 "ShiftTypes_al_r0_r0_ASR_9",
850 ARRAY_SIZE(kShiftTypes),
851 kShiftTypes},
852 {{al, r0, r0, ASR, 10},
853 "al r0 r0 ASR 10",
854 "ShiftTypes_al_r0_r0_ASR_10",
855 ARRAY_SIZE(kShiftTypes),
856 kShiftTypes},
857 {{al, r0, r0, ASR, 11},
858 "al r0 r0 ASR 11",
859 "ShiftTypes_al_r0_r0_ASR_11",
860 ARRAY_SIZE(kShiftTypes),
861 kShiftTypes},
862 {{al, r0, r0, ASR, 12},
863 "al r0 r0 ASR 12",
864 "ShiftTypes_al_r0_r0_ASR_12",
865 ARRAY_SIZE(kShiftTypes),
866 kShiftTypes},
867 {{al, r0, r0, ASR, 13},
868 "al r0 r0 ASR 13",
869 "ShiftTypes_al_r0_r0_ASR_13",
870 ARRAY_SIZE(kShiftTypes),
871 kShiftTypes},
872 {{al, r0, r0, ASR, 14},
873 "al r0 r0 ASR 14",
874 "ShiftTypes_al_r0_r0_ASR_14",
875 ARRAY_SIZE(kShiftTypes),
876 kShiftTypes},
877 {{al, r0, r0, ASR, 15},
878 "al r0 r0 ASR 15",
879 "ShiftTypes_al_r0_r0_ASR_15",
880 ARRAY_SIZE(kShiftTypes),
881 kShiftTypes},
882 {{al, r0, r0, ASR, 16},
883 "al r0 r0 ASR 16",
884 "ShiftTypes_al_r0_r0_ASR_16",
885 ARRAY_SIZE(kShiftTypes),
886 kShiftTypes},
887 {{al, r0, r0, ASR, 17},
888 "al r0 r0 ASR 17",
889 "ShiftTypes_al_r0_r0_ASR_17",
890 ARRAY_SIZE(kShiftTypes),
891 kShiftTypes},
892 {{al, r0, r0, ASR, 18},
893 "al r0 r0 ASR 18",
894 "ShiftTypes_al_r0_r0_ASR_18",
895 ARRAY_SIZE(kShiftTypes),
896 kShiftTypes},
897 {{al, r0, r0, ASR, 19},
898 "al r0 r0 ASR 19",
899 "ShiftTypes_al_r0_r0_ASR_19",
900 ARRAY_SIZE(kShiftTypes),
901 kShiftTypes},
902 {{al, r0, r0, ASR, 20},
903 "al r0 r0 ASR 20",
904 "ShiftTypes_al_r0_r0_ASR_20",
905 ARRAY_SIZE(kShiftTypes),
906 kShiftTypes},
907 {{al, r0, r0, ASR, 21},
908 "al r0 r0 ASR 21",
909 "ShiftTypes_al_r0_r0_ASR_21",
910 ARRAY_SIZE(kShiftTypes),
911 kShiftTypes},
912 {{al, r0, r0, ASR, 22},
913 "al r0 r0 ASR 22",
914 "ShiftTypes_al_r0_r0_ASR_22",
915 ARRAY_SIZE(kShiftTypes),
916 kShiftTypes},
917 {{al, r0, r0, ASR, 23},
918 "al r0 r0 ASR 23",
919 "ShiftTypes_al_r0_r0_ASR_23",
920 ARRAY_SIZE(kShiftTypes),
921 kShiftTypes},
922 {{al, r0, r0, ASR, 24},
923 "al r0 r0 ASR 24",
924 "ShiftTypes_al_r0_r0_ASR_24",
925 ARRAY_SIZE(kShiftTypes),
926 kShiftTypes},
927 {{al, r0, r0, ASR, 25},
928 "al r0 r0 ASR 25",
929 "ShiftTypes_al_r0_r0_ASR_25",
930 ARRAY_SIZE(kShiftTypes),
931 kShiftTypes},
932 {{al, r0, r0, ASR, 26},
933 "al r0 r0 ASR 26",
934 "ShiftTypes_al_r0_r0_ASR_26",
935 ARRAY_SIZE(kShiftTypes),
936 kShiftTypes},
937 {{al, r0, r0, ASR, 27},
938 "al r0 r0 ASR 27",
939 "ShiftTypes_al_r0_r0_ASR_27",
940 ARRAY_SIZE(kShiftTypes),
941 kShiftTypes},
942 {{al, r0, r0, ASR, 28},
943 "al r0 r0 ASR 28",
944 "ShiftTypes_al_r0_r0_ASR_28",
945 ARRAY_SIZE(kShiftTypes),
946 kShiftTypes},
947 {{al, r0, r0, ASR, 29},
948 "al r0 r0 ASR 29",
949 "ShiftTypes_al_r0_r0_ASR_29",
950 ARRAY_SIZE(kShiftTypes),
951 kShiftTypes},
952 {{al, r0, r0, ASR, 30},
953 "al r0 r0 ASR 30",
954 "ShiftTypes_al_r0_r0_ASR_30",
955 ARRAY_SIZE(kShiftTypes),
956 kShiftTypes},
957 {{al, r0, r0, ASR, 31},
958 "al r0 r0 ASR 31",
959 "ShiftTypes_al_r0_r0_ASR_31",
960 ARRAY_SIZE(kShiftTypes),
961 kShiftTypes},
962 {{al, r0, r0, ASR, 32},
963 "al r0 r0 ASR 32",
964 "ShiftTypes_al_r0_r0_ASR_32",
965 ARRAY_SIZE(kShiftTypes),
966 kShiftTypes}};
967
968 // We record all inputs to the instructions as outputs. This way, we also check
969 // that what shouldn't change didn't change.
970 struct TestResult {
971 size_t output_size;
972 const Inputs* outputs;
973 };
974
975 // These headers each contain an array of `TestResult` with the reference output
976 // values. The reference arrays are names `kReference{mnemonic}`.
977 #include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-cmn.h"
978 #include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-cmp.h"
979 #include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-mov.h"
980 #include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-movs.h"
981 #include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-mvn.h"
982 #include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-mvns.h"
983 #include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-teq.h"
984 #include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-tst.h"
985
986
987 // The maximum number of errors to report in detail for each test.
988 const unsigned kErrorReportLimit = 8;
989
990 typedef void (MacroAssembler::*Fn)(Condition cond,
991 Register rd,
992 const Operand& op);
993
TestHelper(Fn instruction,const char * mnemonic,const TestResult reference[])994 void TestHelper(Fn instruction,
995 const char* mnemonic,
996 const TestResult reference[]) {
997 SETUP();
998 masm.UseA32();
999 START();
1000
1001 // Data to compare to `reference`.
1002 TestResult* results[ARRAY_SIZE(kTests)];
1003
1004 // Test cases for memory bound instructions may allocate a buffer and save its
1005 // address in this array.
1006 byte* scratch_memory_buffers[ARRAY_SIZE(kTests)];
1007
1008 // Generate a loop for each element in `kTests`. Each loop tests one specific
1009 // instruction.
1010 for (unsigned i = 0; i < ARRAY_SIZE(kTests); i++) {
1011 // Allocate results on the heap for this test.
1012 results[i] = new TestResult;
1013 results[i]->outputs = new Inputs[kTests[i].input_size];
1014 results[i]->output_size = kTests[i].input_size;
1015
1016 size_t input_stride = sizeof(kTests[i].inputs[0]) * kTests[i].input_size;
1017 VIXL_ASSERT(IsUint32(input_stride));
1018
1019 scratch_memory_buffers[i] = NULL;
1020
1021 Label loop;
1022 UseScratchRegisterScope scratch_registers(&masm);
1023 // Include all registers from r0 ro r12.
1024 scratch_registers.Include(RegisterList(0x1fff));
1025
1026 // Values to pass to the macro-assembler.
1027 Condition cond = kTests[i].operands.cond;
1028 Register rd = kTests[i].operands.rd;
1029 Register rn = kTests[i].operands.rn;
1030 ShiftType shift = kTests[i].operands.shift;
1031 uint32_t amount = kTests[i].operands.amount;
1032 Operand op(rn, shift, amount);
1033 scratch_registers.Exclude(rd);
1034 scratch_registers.Exclude(rn);
1035
1036 // Allocate reserved registers for our own use.
1037 Register input_ptr = scratch_registers.Acquire();
1038 Register input_end = scratch_registers.Acquire();
1039 Register result_ptr = scratch_registers.Acquire();
1040
1041 // Initialize `input_ptr` to the first element and `input_end` the address
1042 // after the array.
1043 __ Mov(input_ptr, Operand::From(kTests[i].inputs));
1044 __ Add(input_end, input_ptr, static_cast<uint32_t>(input_stride));
1045 __ Mov(result_ptr, Operand::From(results[i]->outputs));
1046 __ Bind(&loop);
1047
1048 {
1049 UseScratchRegisterScope temp_registers(&masm);
1050 Register nzcv_bits = temp_registers.Acquire();
1051 Register saved_q_bit = temp_registers.Acquire();
1052 // Save the `Q` bit flag.
1053 __ Mrs(saved_q_bit, APSR);
1054 __ And(saved_q_bit, saved_q_bit, QFlag);
1055 // Set the `NZCV` and `Q` flags together.
1056 __ Ldr(nzcv_bits, MemOperand(input_ptr, offsetof(Inputs, apsr)));
1057 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit);
1058 __ Msr(APSR_nzcvq, nzcv_bits);
1059 }
1060 __ Ldr(rd, MemOperand(input_ptr, offsetof(Inputs, rd)));
1061 __ Ldr(rn, MemOperand(input_ptr, offsetof(Inputs, rn)));
1062
1063 (masm.*instruction)(cond, rd, op);
1064
1065 {
1066 UseScratchRegisterScope temp_registers(&masm);
1067 Register nzcv_bits = temp_registers.Acquire();
1068 __ Mrs(nzcv_bits, APSR);
1069 // Only record the NZCV bits.
1070 __ And(nzcv_bits, nzcv_bits, NZCVFlag);
1071 __ Str(nzcv_bits, MemOperand(result_ptr, offsetof(Inputs, apsr)));
1072 }
1073 __ Str(rd, MemOperand(result_ptr, offsetof(Inputs, rd)));
1074 __ Str(rn, MemOperand(result_ptr, offsetof(Inputs, rn)));
1075
1076 // Advance the result pointer.
1077 __ Add(result_ptr, result_ptr, Operand::From(sizeof(kTests[i].inputs[0])));
1078 // Loop back until `input_ptr` is lower than `input_base`.
1079 __ Add(input_ptr, input_ptr, Operand::From(sizeof(kTests[i].inputs[0])));
1080 __ Cmp(input_ptr, input_end);
1081 __ B(ne, &loop);
1082 }
1083
1084 END();
1085
1086 RUN();
1087
1088 if (Test::generate_test_trace()) {
1089 // Print the results.
1090 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) {
1091 printf("const Inputs kOutputs_%s_%s[] = {\n",
1092 mnemonic,
1093 kTests[i].identifier);
1094 for (size_t j = 0; j < results[i]->output_size; j++) {
1095 printf(" { ");
1096 printf("0x%08" PRIx32, results[i]->outputs[j].apsr);
1097 printf(", ");
1098 printf("0x%08" PRIx32, results[i]->outputs[j].rd);
1099 printf(", ");
1100 printf("0x%08" PRIx32, results[i]->outputs[j].rn);
1101 printf(" },\n");
1102 }
1103 printf("};\n");
1104 }
1105 printf("const TestResult kReference%s[] = {\n", mnemonic);
1106 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) {
1107 printf(" {\n");
1108 printf(" ARRAY_SIZE(kOutputs_%s_%s),\n",
1109 mnemonic,
1110 kTests[i].identifier);
1111 printf(" kOutputs_%s_%s,\n", mnemonic, kTests[i].identifier);
1112 printf(" },\n");
1113 }
1114 printf("};\n");
1115 } else if (kCheckSimulatorTestResults) {
1116 // Check the results.
1117 unsigned total_error_count = 0;
1118 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) {
1119 bool instruction_has_errors = false;
1120 for (size_t j = 0; j < kTests[i].input_size; j++) {
1121 uint32_t apsr = results[i]->outputs[j].apsr;
1122 uint32_t rd = results[i]->outputs[j].rd;
1123 uint32_t rn = results[i]->outputs[j].rn;
1124 uint32_t apsr_input = kTests[i].inputs[j].apsr;
1125 uint32_t rd_input = kTests[i].inputs[j].rd;
1126 uint32_t rn_input = kTests[i].inputs[j].rn;
1127 uint32_t apsr_ref = reference[i].outputs[j].apsr;
1128 uint32_t rd_ref = reference[i].outputs[j].rd;
1129 uint32_t rn_ref = reference[i].outputs[j].rn;
1130
1131 if (((apsr != apsr_ref) || (rd != rd_ref) || (rn != rn_ref)) &&
1132 (++total_error_count <= kErrorReportLimit)) {
1133 // Print the instruction once even if it triggered multiple failures.
1134 if (!instruction_has_errors) {
1135 printf("Error(s) when testing \"%s %s\":\n",
1136 mnemonic,
1137 kTests[i].operands_description);
1138 instruction_has_errors = true;
1139 }
1140 // Print subsequent errors.
1141 printf(" Input: ");
1142 printf("0x%08" PRIx32, apsr_input);
1143 printf(", ");
1144 printf("0x%08" PRIx32, rd_input);
1145 printf(", ");
1146 printf("0x%08" PRIx32, rn_input);
1147 printf("\n");
1148 printf(" Expected: ");
1149 printf("0x%08" PRIx32, apsr_ref);
1150 printf(", ");
1151 printf("0x%08" PRIx32, rd_ref);
1152 printf(", ");
1153 printf("0x%08" PRIx32, rn_ref);
1154 printf("\n");
1155 printf(" Found: ");
1156 printf("0x%08" PRIx32, apsr);
1157 printf(", ");
1158 printf("0x%08" PRIx32, rd);
1159 printf(", ");
1160 printf("0x%08" PRIx32, rn);
1161 printf("\n\n");
1162 }
1163 }
1164 }
1165
1166 if (total_error_count > kErrorReportLimit) {
1167 printf("%u other errors follow.\n",
1168 total_error_count - kErrorReportLimit);
1169 }
1170 VIXL_CHECK(total_error_count == 0);
1171 } else {
1172 VIXL_WARNING("Assembled the code, but did not run anything.\n");
1173 }
1174
1175 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) {
1176 delete[] results[i]->outputs;
1177 delete results[i];
1178 delete[] scratch_memory_buffers[i];
1179 }
1180
1181 TEARDOWN();
1182 }
1183
1184 // Instantiate tests for each instruction in the list.
1185 // TODO: Remove this limitation by having a sandboxing mechanism.
1186 #if defined(VIXL_HOST_POINTER_32)
1187 #define TEST(mnemonic) \
1188 void Test_##mnemonic() { \
1189 TestHelper(&MacroAssembler::mnemonic, #mnemonic, kReference##mnemonic); \
1190 } \
1191 Test test_##mnemonic( \
1192 "AARCH32_SIMULATOR_COND_RD_OPERAND_RN_SHIFT_AMOUNT_1TO32_" \
1193 "A32_" #mnemonic, \
1194 &Test_##mnemonic);
1195 #else
1196 #define TEST(mnemonic) \
1197 void Test_##mnemonic() { \
1198 VIXL_WARNING("This test can only run on a 32-bit host.\n"); \
1199 USE(TestHelper); \
1200 } \
1201 Test test_##mnemonic( \
1202 "AARCH32_SIMULATOR_COND_RD_OPERAND_RN_SHIFT_AMOUNT_1TO32_" \
1203 "A32_" #mnemonic, \
1204 &Test_##mnemonic);
1205 #endif
1206
1207 FOREACH_INSTRUCTION(TEST)
1208 #undef TEST
1209
1210 } // namespace
1211 #endif
1212
1213 } // namespace aarch32
1214 } // namespace vixl
1215