1 /* 2 // Copyright (c) 2014 Intel Corporation 3 // 4 // Licensed under the Apache License, Version 2.0 (the "License"); 5 // you may not use this file except in compliance with the License. 6 // You may obtain a copy of the License at 7 // 8 // http://www.apache.org/licenses/LICENSE-2.0 9 // 10 // Unless required by applicable law or agreed to in writing, software 11 // distributed under the License is distributed on an "AS IS" BASIS, 12 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 // See the License for the specific language governing permissions and 14 // limitations under the License. 15 */ 16 #ifndef OVERLAY_HARDWARE_H 17 #define OVERLAY_HARDWARE_H 18 19 namespace android { 20 namespace intel { 21 22 // only one overlay data buffer for testing 23 #define INTEL_OVERLAY_BUFFER_NUM 1 24 #define INTEL_OVERLAY_MAX_WIDTH 2048 25 #define INTEL_OVERLAY_MAX_HEIGHT 2048 26 #define INTEL_OVERLAY_MIN_STRIDE 512 27 #define INTEL_OVERLAY_MAX_STRIDE_PACKED (8 * 1024) 28 #define INTEL_OVERLAY_MAX_STRIDE_LINEAR (4 * 1024) 29 #define INTEL_OVERLAY_MAX_SCALING_RATIO 7 30 31 // Polyphase filter coefficients 32 #define N_HORIZ_Y_TAPS 5 33 #define N_VERT_Y_TAPS 3 34 #define N_HORIZ_UV_TAPS 3 35 #define N_VERT_UV_TAPS 3 36 #define N_PHASES 17 37 #define MAX_TAPS 5 38 39 // Filter cutoff frequency limits. 40 #define MIN_CUTOFF_FREQ 1.0 41 #define MAX_CUTOFF_FREQ 3.0 42 43 // Overlay init micros 44 #define OVERLAY_INIT_CONTRAST 0x4b 45 #define OVERLAY_INIT_BRIGHTNESS -19 46 #define OVERLAY_INIT_SATURATION 0x92 47 #define OVERLAY_INIT_GAMMA0 0x080808 48 #define OVERLAY_INIT_GAMMA1 0x101010 49 #define OVERLAY_INIT_GAMMA2 0x202020 50 #define OVERLAY_INIT_GAMMA3 0x404040 51 #define OVERLAY_INIT_GAMMA4 0x808080 52 #define OVERLAY_INIT_GAMMA5 0xc0c0c0 53 #define OVERLAY_INIT_COLORKEY 0 54 #define OVERLAY_INIT_COLORKEYMASK ((0x0 << 31) | (0X0 << 30)) 55 #define OVERLAY_INIT_CONFIG ((0x1 << 18) | (0x1 << 3)) 56 57 // overlay register values 58 #define OVERLAY_FORMAT_MASK (0xf << 10) 59 #define OVERLAY_FORMAT_PACKED_YUV422 (0x8 << 10) 60 #define OVERLAY_FORMAT_PLANAR_NV12_1 (0x7 << 10) 61 #define OVERLAY_FORMAT_PLANAR_NV12_2 (0xb << 10) 62 #define OVERLAY_FORMAT_PLANAR_YUV420 (0xc << 10) 63 #define OVERLAY_FORMAT_PLANAR_YUV422 (0xd << 10) 64 #define OVERLAY_FORMAT_PLANAR_YUV41X (0xe << 10) 65 66 #define OVERLAY_PACKED_ORDER_YUY2 (0x0 << 14) 67 #define OVERLAY_PACKED_ORDER_YVYU (0x1 << 14) 68 #define OVERLAY_PACKED_ORDER_UYVY (0x2 << 14) 69 #define OVERLAY_PACKED_ORDER_VYUY (0x3 << 14) 70 #define OVERLAY_PACKED_ORDER_MASK (0x3 << 14) 71 72 #define OVERLAY_MEMORY_LAYOUT_TILED (0x1 << 19) 73 #define OVERLAY_MEMORY_LAYOUT_LINEAR (0x0 << 19) 74 75 #define OVERLAY_MIRRORING_NORMAL (0x0 << 17) 76 #define OVERLAY_MIRRORING_HORIZONTAL (0x1 << 17) 77 #define OVERLAY_MIRRORING_VERTIACAL (0x2 << 17) 78 #define OVERLAY_MIRRORING_BOTH (0x3 << 17) 79 80 #define BUF_TYPE (0x1<<5) 81 #define BUF_TYPE_FRAME (0x0<<5) 82 #define BUF_TYPE_FIELD (0x1<<5) 83 #define TEST_MODE (0x1<<4) 84 #define BUFFER_SELECT (0x3<<2) 85 #define BUFFER0 (0x0<<2) 86 #define BUFFER1 (0x1<<2) 87 #define FIELD_SELECT (0x1<<1) 88 #define FIELD0 (0x0<<1) 89 #define FIELD1 (0x1<<1) 90 #define OVERLAY_ENABLE 0x1 91 92 93 // Overlay contorl registers 94 typedef struct { 95 uint32_t OBUF_0Y; 96 uint32_t OBUF_1Y; 97 uint32_t OBUF_0U; 98 uint32_t OBUF_0V; 99 uint32_t OBUF_1U; 100 uint32_t OBUF_1V; 101 uint32_t OSTRIDE; 102 uint32_t YRGB_VPH; 103 uint32_t UV_VPH; 104 uint32_t HORZ_PH; 105 uint32_t INIT_PHS; 106 uint32_t DWINPOS; 107 uint32_t DWINSZ; 108 uint32_t SWIDTH; 109 uint32_t SWIDTHSW; 110 uint32_t SHEIGHT; 111 uint32_t YRGBSCALE; 112 uint32_t UVSCALE; 113 uint32_t OCLRC0; 114 uint32_t OCLRC1; 115 uint32_t DCLRKV; 116 uint32_t DCLRKM; 117 uint32_t SCHRKVH; 118 uint32_t SCHRKVL; 119 uint32_t SCHRKEN; 120 uint32_t OCONFIG; 121 uint32_t OCMD; 122 uint32_t RESERVED1; 123 uint32_t OSTART_0Y; 124 uint32_t OSTART_1Y; 125 uint32_t OSTART_0U; 126 uint32_t OSTART_0V; 127 uint32_t OSTART_1U; 128 uint32_t OSTART_1V; 129 uint32_t OTILEOFF_0Y; 130 uint32_t OTILEOFF_1Y; 131 uint32_t OTILEOFF_0U; 132 uint32_t OTILEOFF_0V; 133 uint32_t OTILEOFF_1U; 134 uint32_t OTILEOFF_1V; 135 uint32_t FASTHSCALE; 136 uint32_t UVSCALEV; 137 138 uint32_t RESERVEDC[(0x200 - 0xA8) / 4]; 139 uint16_t Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; 140 uint16_t RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; 141 uint16_t Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; 142 uint16_t RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; 143 uint16_t UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; 144 uint16_t RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; 145 uint16_t UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; 146 uint16_t RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; 147 } OverlayBackBufferBlk; 148 149 typedef struct { 150 uint8_t sign; 151 uint16_t mantissa; 152 uint8_t exponent; 153 } coeffRec, *coeffPtr; 154 155 156 } // namespace intel 157 } // nam 158 159 160 #endif 161