1 #ifndef _UAPI_MSM_MDP_H_ 2 #define _UAPI_MSM_MDP_H_ 3 4 #include <linux/types.h> 5 #include <linux/fb.h> 6 7 #define MSMFB_IOCTL_MAGIC 'm' 8 #define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int) 9 #define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int) 10 #define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int) 11 #define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int) 12 #define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor) 13 #define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap) 14 #define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data) 15 /* new ioctls's for set/get ccs matrix */ 16 #define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs) 17 #define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs) 18 #define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, \ 19 struct mdp_overlay) 20 #define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int) 21 22 #define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, \ 23 struct msmfb_overlay_data) 24 #define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY 25 26 #define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, \ 27 struct mdp_page_protection) 28 #define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, \ 29 struct mdp_page_protection) 30 #define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, \ 31 struct mdp_overlay) 32 #define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int) 33 #define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, \ 34 struct msmfb_overlay_blt) 35 #define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int) 36 #define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, \ 37 struct mdp_histogram_start_req) 38 #define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int) 39 #define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int) 40 41 #define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, \ 42 struct msmfb_overlay_3d) 43 44 #define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, \ 45 struct msmfb_mixer_info_req) 46 #define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, \ 47 struct msmfb_overlay_data) 48 #define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150) 49 #define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151) 50 #define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152) 51 #define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, \ 52 struct msmfb_data) 53 #define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, \ 54 struct msmfb_data) 55 #define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155) 56 #define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp) 57 #define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) 58 #define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) 59 #define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) 60 #define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163) 61 #define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, \ 62 struct mdp_display_commit) 63 #define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata) 64 #define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) 65 #define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, \ 66 unsigned int) 67 #define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) 68 #define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, \ 69 struct mdp_overlay_list) 70 #define MSMFB_LPM_ENABLE _IOWR(MSMFB_IOCTL_MAGIC, 170, unsigned int) 71 #define MSMFB_MDP_PP_GET_FEATURE_VERSION _IOWR(MSMFB_IOCTL_MAGIC, 171, \ 72 struct mdp_pp_feature_version) 73 74 #define FB_TYPE_3D_PANEL 0x10101010 75 #define MDP_IMGTYPE2_START 0x10000 76 #define MSMFB_DRIVER_VERSION 0xF9E8D701 77 78 /* HW Revisions for different MDSS targets */ 79 #define MDSS_GET_MAJOR(rev) ((rev) >> 28) 80 #define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) 81 #define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) 82 #define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) 83 84 #define IS_MDSS_MAJOR_MINOR_SAME(rev1, rev2) \ 85 (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) 86 87 #define MDSS_MDP_REV(major, minor, step) \ 88 ((((major) & 0x000F) << 28) | \ 89 (((minor) & 0x0FFF) << 16) | \ 90 ((step) & 0xFFFF)) 91 92 #define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) /* 8974 v1.0 */ 93 #define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) /* 8x26 v1.0 */ 94 #define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) /* 8x26 v2.0, 8926 v1.0 */ 95 #define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) /* 8926 v2.0 */ 96 #define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) /* 8974 v2.0 */ 97 #define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) /* 8974 v3.0 (Pro) */ 98 #define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) /* 8084 v1.0 */ 99 #define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) /* 8084 v1.1 */ 100 #define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) /* 8994 v1.0 */ 101 #define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) /* 8916 v1.0 */ 102 #define MDSS_MDP_HW_REV_107 MDSS_MDP_REV(1, 7, 0) /* 8996 v1 */ 103 #define MDSS_MDP_HW_REV_107_1 MDSS_MDP_REV(1, 7, 1) /* 8996 v2 */ 104 #define MDSS_MDP_HW_REV_107_2 MDSS_MDP_REV(1, 7, 2) /* 8996 v3 */ 105 #define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) /* 8939 v1.0 */ 106 #define MDSS_MDP_HW_REV_109 MDSS_MDP_REV(1, 9, 0) /* 8994 v2.0 */ 107 #define MDSS_MDP_HW_REV_110 MDSS_MDP_REV(1, 10, 0) /* 8992 v1.0 */ 108 #define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */ 109 #define MDSS_MDP_HW_REV_112 MDSS_MDP_REV(1, 12, 0) /* 8952 v1.0 */ 110 #define MDSS_MDP_HW_REV_114 MDSS_MDP_REV(1, 14, 0) /* 8937 v1.0 */ 111 #define MDSS_MDP_HW_REV_115 MDSS_MDP_REV(1, 15, 0) /* msmgold */ 112 #define MDSS_MDP_HW_REV_116 MDSS_MDP_REV(1, 16, 0) /* msmtitanium */ 113 114 enum { 115 NOTIFY_UPDATE_INIT, 116 NOTIFY_UPDATE_DEINIT, 117 NOTIFY_UPDATE_START, 118 NOTIFY_UPDATE_STOP, 119 NOTIFY_UPDATE_POWER_OFF, 120 }; 121 122 enum { 123 NOTIFY_TYPE_NO_UPDATE, 124 NOTIFY_TYPE_SUSPEND, 125 NOTIFY_TYPE_UPDATE, 126 NOTIFY_TYPE_BL_UPDATE, 127 NOTIFY_TYPE_BL_AD_ATTEN_UPDATE, 128 }; 129 130 enum { 131 MDP_RGB_565, /* RGB 565 planer */ 132 MDP_XRGB_8888, /* RGB 888 padded */ 133 MDP_Y_CBCR_H2V2, /* Y and CbCr, pseudo planer w/ Cb is in MSB */ 134 MDP_Y_CBCR_H2V2_ADRENO, 135 MDP_ARGB_8888, /* ARGB 888 */ 136 MDP_RGB_888, /* RGB 888 planer */ 137 MDP_Y_CRCB_H2V2, /* Y and CrCb, pseudo planer w/ Cr is in MSB */ 138 MDP_YCRYCB_H2V1, /* YCrYCb interleave */ 139 MDP_CBYCRY_H2V1, /* CbYCrY interleave */ 140 MDP_Y_CRCB_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 141 MDP_Y_CBCR_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 142 MDP_Y_CRCB_H1V2, 143 MDP_Y_CBCR_H1V2, 144 MDP_RGBA_8888, /* ARGB 888 */ 145 MDP_BGRA_8888, /* ABGR 888 */ 146 MDP_RGBX_8888, /* RGBX 888 */ 147 MDP_Y_CRCB_H2V2_TILE, /* Y and CrCb, pseudo planer tile */ 148 MDP_Y_CBCR_H2V2_TILE, /* Y and CbCr, pseudo planer tile */ 149 MDP_Y_CR_CB_H2V2, /* Y, Cr and Cb, planar */ 150 MDP_Y_CR_CB_GH2V2, /* Y, Cr and Cb, planar aligned to Android YV12 */ 151 MDP_Y_CB_CR_H2V2, /* Y, Cb and Cr, planar */ 152 MDP_Y_CRCB_H1V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 153 MDP_Y_CBCR_H1V1, /* Y and CbCr, pseduo planer w/ Cb is in MSB */ 154 MDP_YCRCB_H1V1, /* YCrCb interleave */ 155 MDP_YCBCR_H1V1, /* YCbCr interleave */ 156 MDP_BGR_565, /* BGR 565 planer */ 157 MDP_BGR_888, /* BGR 888 */ 158 MDP_Y_CBCR_H2V2_VENUS, 159 MDP_BGRX_8888, /* BGRX 8888 */ 160 MDP_RGBA_8888_TILE, /* RGBA 8888 in tile format */ 161 MDP_ARGB_8888_TILE, /* ARGB 8888 in tile format */ 162 MDP_ABGR_8888_TILE, /* ABGR 8888 in tile format */ 163 MDP_BGRA_8888_TILE, /* BGRA 8888 in tile format */ 164 MDP_RGBX_8888_TILE, /* RGBX 8888 in tile format */ 165 MDP_XRGB_8888_TILE, /* XRGB 8888 in tile format */ 166 MDP_XBGR_8888_TILE, /* XBGR 8888 in tile format */ 167 MDP_BGRX_8888_TILE, /* BGRX 8888 in tile format */ 168 MDP_YCBYCR_H2V1, /* YCbYCr interleave */ 169 MDP_RGB_565_TILE, /* RGB 565 in tile format */ 170 MDP_BGR_565_TILE, /* BGR 565 in tile format */ 171 MDP_ARGB_1555, /*ARGB 1555*/ 172 MDP_RGBA_5551, /*RGBA 5551*/ 173 MDP_ARGB_4444, /*ARGB 4444*/ 174 MDP_RGBA_4444, /*RGBA 4444*/ 175 MDP_RGB_565_UBWC, 176 MDP_RGBA_8888_UBWC, 177 MDP_Y_CBCR_H2V2_UBWC, 178 MDP_RGBX_8888_UBWC, 179 MDP_Y_CRCB_H2V2_VENUS, 180 MDP_IMGTYPE_LIMIT, 181 MDP_RGB_BORDERFILL, /* border fill pipe */ 182 MDP_FB_FORMAT = MDP_IMGTYPE2_START, /* framebuffer format */ 183 MDP_IMGTYPE_LIMIT2 /* Non valid image type after this enum */ 184 }; 185 186 enum { 187 PMEM_IMG, 188 FB_IMG, 189 }; 190 191 enum { 192 HSIC_HUE = 0, 193 HSIC_SAT, 194 HSIC_INT, 195 HSIC_CON, 196 NUM_HSIC_PARAM, 197 }; 198 199 enum mdss_mdp_max_bw_mode { 200 MDSS_MAX_BW_LIMIT_DEFAULT = 0x1, 201 MDSS_MAX_BW_LIMIT_CAMERA = 0x2, 202 MDSS_MAX_BW_LIMIT_HFLIP = 0x4, 203 MDSS_MAX_BW_LIMIT_VFLIP = 0x8, 204 }; 205 206 #define MDSS_MDP_ROT_ONLY 0x80 207 #define MDSS_MDP_RIGHT_MIXER 0x100 208 #define MDSS_MDP_DUAL_PIPE 0x200 209 210 /* mdp_blit_req flag values */ 211 #define MDP_ROT_NOP 0 212 #define MDP_FLIP_LR 0x1 213 #define MDP_FLIP_UD 0x2 214 #define MDP_ROT_90 0x4 215 #define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR) 216 #define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR) 217 #define MDP_DITHER 0x8 218 #define MDP_BLUR 0x10 219 #define MDP_BLEND_FG_PREMULT 0x20000 220 #define MDP_IS_FG 0x40000 221 #define MDP_SOLID_FILL 0x00000020 222 #define MDP_VPU_PIPE 0x00000040 223 #define MDP_DEINTERLACE 0x80000000 224 #define MDP_SHARPENING 0x40000000 225 #define MDP_NO_DMA_BARRIER_START 0x20000000 226 #define MDP_NO_DMA_BARRIER_END 0x10000000 227 #define MDP_NO_BLIT 0x08000000 228 #define MDP_BLIT_WITH_DMA_BARRIERS 0x000 229 #define MDP_BLIT_WITH_NO_DMA_BARRIERS \ 230 (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) 231 #define MDP_BLIT_SRC_GEM 0x04000000 232 #define MDP_BLIT_DST_GEM 0x02000000 233 #define MDP_BLIT_NON_CACHED 0x01000000 234 #define MDP_OV_PIPE_SHARE 0x00800000 235 #define MDP_DEINTERLACE_ODD 0x00400000 236 #define MDP_OV_PLAY_NOWAIT 0x00200000 237 #define MDP_SOURCE_ROTATED_90 0x00100000 238 #define MDP_OVERLAY_PP_CFG_EN 0x00080000 239 #define MDP_BACKEND_COMPOSITION 0x00040000 240 #define MDP_BORDERFILL_SUPPORTED 0x00010000 241 #define MDP_SECURE_OVERLAY_SESSION 0x00008000 242 #define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000 243 #define MDP_OV_PIPE_FORCE_DMA 0x00004000 244 #define MDP_MEMORY_ID_TYPE_FB 0x00001000 245 #define MDP_BWC_EN 0x00000400 246 #define MDP_DECIMATION_EN 0x00000800 247 #define MDP_SMP_FORCE_ALLOC 0x00200000 248 #define MDP_TRANSP_NOP 0xffffffff 249 #define MDP_ALPHA_NOP 0xff 250 251 #define MDP_FB_PAGE_PROTECTION_NONCACHED (0) 252 #define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) 253 #define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) 254 #define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) 255 #define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) 256 /* Sentinel: Don't use! */ 257 #define MDP_FB_PAGE_PROTECTION_INVALID (5) 258 /* Count of the number of MDP_FB_PAGE_PROTECTION_... values. */ 259 #define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) 260 261 struct mdp_rect { 262 uint32_t x; 263 uint32_t y; 264 uint32_t w; 265 uint32_t h; 266 }; 267 268 struct mdp_img { 269 uint32_t width; 270 uint32_t height; 271 uint32_t format; 272 uint32_t offset; 273 int memory_id; /* the file descriptor */ 274 uint32_t priv; 275 }; 276 277 struct mult_factor { 278 uint32_t numer; 279 uint32_t denom; 280 }; 281 282 /* 283 * {3x3} + {3} ccs matrix 284 */ 285 286 #define MDP_CCS_RGB2YUV 0 287 #define MDP_CCS_YUV2RGB 1 288 289 #define MDP_CCS_SIZE 9 290 #define MDP_BV_SIZE 3 291 292 struct mdp_ccs { 293 int direction; /* MDP_CCS_RGB2YUV or YUV2RGB */ 294 uint16_t ccs[MDP_CCS_SIZE]; /* 3x3 color coefficients */ 295 uint16_t bv[MDP_BV_SIZE]; /* 1x3 bias vector */ 296 }; 297 298 struct mdp_csc { 299 int id; 300 uint32_t csc_mv[9]; 301 uint32_t csc_pre_bv[3]; 302 uint32_t csc_post_bv[3]; 303 uint32_t csc_pre_lv[6]; 304 uint32_t csc_post_lv[6]; 305 }; 306 307 /* The version of the mdp_blit_req structure so that 308 * user applications can selectively decide which functionality 309 * to include 310 */ 311 312 #define MDP_BLIT_REQ_VERSION 3 313 314 struct color { 315 uint32_t r; 316 uint32_t g; 317 uint32_t b; 318 uint32_t alpha; 319 }; 320 321 struct mdp_blit_req { 322 struct mdp_img src; 323 struct mdp_img dst; 324 struct mdp_rect src_rect; 325 struct mdp_rect dst_rect; 326 struct color const_color; 327 uint32_t alpha; 328 uint32_t transp_mask; 329 uint32_t flags; 330 int sharpening_strength; /* -127 <--> 127, default 64 */ 331 uint8_t color_space; 332 uint32_t fps; 333 }; 334 335 struct mdp_blit_req_list { 336 uint32_t count; 337 struct mdp_blit_req req[]; 338 }; 339 340 #define MSMFB_DATA_VERSION 2 341 342 struct msmfb_data { 343 uint32_t offset; 344 int memory_id; 345 int id; 346 uint32_t flags; 347 uint32_t priv; 348 uint32_t iova; 349 }; 350 351 #define MSMFB_NEW_REQUEST -1 352 353 struct msmfb_overlay_data { 354 uint32_t id; 355 struct msmfb_data data; 356 uint32_t version_key; 357 struct msmfb_data plane1_data; 358 struct msmfb_data plane2_data; 359 struct msmfb_data dst_data; 360 }; 361 362 struct msmfb_img { 363 uint32_t width; 364 uint32_t height; 365 uint32_t format; 366 }; 367 368 #define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 369 struct msmfb_writeback_data { 370 struct msmfb_data buf_info; 371 struct msmfb_img img; 372 }; 373 374 #define MDP_PP_OPS_ENABLE 0x1 375 #define MDP_PP_OPS_READ 0x2 376 #define MDP_PP_OPS_WRITE 0x4 377 #define MDP_PP_OPS_DISABLE 0x8 378 #define MDP_PP_IGC_FLAG_ROM0 0x10 379 #define MDP_PP_IGC_FLAG_ROM1 0x20 380 381 382 #define MDSS_PP_DSPP_CFG 0x000 383 #define MDSS_PP_SSPP_CFG 0x100 384 #define MDSS_PP_LM_CFG 0x200 385 #define MDSS_PP_WB_CFG 0x300 386 387 #define MDSS_PP_ARG_MASK 0x3C00 388 #define MDSS_PP_ARG_NUM 4 389 #define MDSS_PP_ARG_SHIFT 10 390 #define MDSS_PP_LOCATION_MASK 0x0300 391 #define MDSS_PP_LOGICAL_MASK 0x00FF 392 393 #define MDSS_PP_ADD_ARG(var, arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) 394 #define PP_ARG(x, var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) 395 #define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) 396 #define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) 397 398 399 struct mdp_qseed_cfg { 400 uint32_t table_num; 401 uint32_t ops; 402 uint32_t len; 403 uint32_t *data; 404 }; 405 406 struct mdp_sharp_cfg { 407 uint32_t flags; 408 uint32_t strength; 409 uint32_t edge_thr; 410 uint32_t smooth_thr; 411 uint32_t noise_thr; 412 }; 413 414 struct mdp_qseed_cfg_data { 415 uint32_t block; 416 struct mdp_qseed_cfg qseed_data; 417 }; 418 419 #define MDP_OVERLAY_PP_CSC_CFG 0x1 420 #define MDP_OVERLAY_PP_QSEED_CFG 0x2 421 #define MDP_OVERLAY_PP_PA_CFG 0x4 422 #define MDP_OVERLAY_PP_IGC_CFG 0x8 423 #define MDP_OVERLAY_PP_SHARP_CFG 0x10 424 #define MDP_OVERLAY_PP_HIST_CFG 0x20 425 #define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 426 #define MDP_OVERLAY_PP_PA_V2_CFG 0x80 427 #define MDP_OVERLAY_PP_PCC_CFG 0x100 428 429 #define MDP_CSC_FLAG_ENABLE 0x1 430 #define MDP_CSC_FLAG_YUV_IN 0x2 431 #define MDP_CSC_FLAG_YUV_OUT 0x4 432 433 #define MDP_CSC_MATRIX_COEFF_SIZE 9 434 #define MDP_CSC_CLAMP_SIZE 6 435 #define MDP_CSC_BIAS_SIZE 3 436 437 struct mdp_csc_cfg { 438 /* flags for enable CSC, toggling RGB,YUV input/output */ 439 uint32_t flags; 440 uint32_t csc_mv[MDP_CSC_MATRIX_COEFF_SIZE]; 441 uint32_t csc_pre_bv[MDP_CSC_BIAS_SIZE]; 442 uint32_t csc_post_bv[MDP_CSC_BIAS_SIZE]; 443 uint32_t csc_pre_lv[MDP_CSC_CLAMP_SIZE]; 444 uint32_t csc_post_lv[MDP_CSC_CLAMP_SIZE]; 445 }; 446 447 struct mdp_csc_cfg_data { 448 uint32_t block; 449 struct mdp_csc_cfg csc_data; 450 }; 451 452 struct mdp_pa_cfg { 453 uint32_t flags; 454 uint32_t hue_adj; 455 uint32_t sat_adj; 456 uint32_t val_adj; 457 uint32_t cont_adj; 458 }; 459 460 struct mdp_pa_mem_col_cfg { 461 uint32_t color_adjust_p0; 462 uint32_t color_adjust_p1; 463 uint32_t hue_region; 464 uint32_t sat_region; 465 uint32_t val_region; 466 }; 467 468 #define MDP_SIX_ZONE_LUT_SIZE 384 469 470 /* PA Write/Read extension flags */ 471 #define MDP_PP_PA_HUE_ENABLE 0x10 472 #define MDP_PP_PA_SAT_ENABLE 0x20 473 #define MDP_PP_PA_VAL_ENABLE 0x40 474 #define MDP_PP_PA_CONT_ENABLE 0x80 475 #define MDP_PP_PA_SIX_ZONE_ENABLE 0x100 476 #define MDP_PP_PA_SKIN_ENABLE 0x200 477 #define MDP_PP_PA_SKY_ENABLE 0x400 478 #define MDP_PP_PA_FOL_ENABLE 0x800 479 480 /* PA masks */ 481 /* Masks used in PA v1_7 only */ 482 #define MDP_PP_PA_MEM_PROT_HUE_EN 0x1 483 #define MDP_PP_PA_MEM_PROT_SAT_EN 0x2 484 #define MDP_PP_PA_MEM_PROT_VAL_EN 0x4 485 #define MDP_PP_PA_MEM_PROT_CONT_EN 0x8 486 #define MDP_PP_PA_MEM_PROT_SIX_EN 0x10 487 #define MDP_PP_PA_MEM_PROT_BLEND_EN 0x20 488 /* Masks used in all PAv2 versions */ 489 #define MDP_PP_PA_HUE_MASK 0x1000 490 #define MDP_PP_PA_SAT_MASK 0x2000 491 #define MDP_PP_PA_VAL_MASK 0x4000 492 #define MDP_PP_PA_CONT_MASK 0x8000 493 #define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000 494 #define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000 495 #define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000 496 #define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000 497 #define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000 498 #define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000 499 #define MDP_PP_PA_MEM_PROTECT_EN 0x400000 500 #define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000 501 502 /* Flags for setting PA saturation and value hold */ 503 #define MDP_PP_PA_LEFT_HOLD 0x1 504 #define MDP_PP_PA_RIGHT_HOLD 0x2 505 506 struct mdp_pa_v2_data { 507 /* Mask bits for PA features */ 508 uint32_t flags; 509 uint32_t global_hue_adj; 510 uint32_t global_sat_adj; 511 uint32_t global_val_adj; 512 uint32_t global_cont_adj; 513 struct mdp_pa_mem_col_cfg skin_cfg; 514 struct mdp_pa_mem_col_cfg sky_cfg; 515 struct mdp_pa_mem_col_cfg fol_cfg; 516 uint32_t six_zone_len; 517 uint32_t six_zone_thresh; 518 uint32_t *six_zone_curve_p0; 519 uint32_t *six_zone_curve_p1; 520 }; 521 522 struct mdp_pa_mem_col_data_v1_7 { 523 uint32_t color_adjust_p0; 524 uint32_t color_adjust_p1; 525 uint32_t color_adjust_p2; 526 uint32_t blend_gain; 527 uint8_t sat_hold; 528 uint8_t val_hold; 529 uint32_t hue_region; 530 uint32_t sat_region; 531 uint32_t val_region; 532 }; 533 534 struct mdp_pa_data_v1_7 { 535 uint32_t mode; 536 uint32_t global_hue_adj; 537 uint32_t global_sat_adj; 538 uint32_t global_val_adj; 539 uint32_t global_cont_adj; 540 struct mdp_pa_mem_col_data_v1_7 skin_cfg; 541 struct mdp_pa_mem_col_data_v1_7 sky_cfg; 542 struct mdp_pa_mem_col_data_v1_7 fol_cfg; 543 uint32_t six_zone_thresh; 544 uint32_t six_zone_adj_p0; 545 uint32_t six_zone_adj_p1; 546 uint8_t six_zone_sat_hold; 547 uint8_t six_zone_val_hold; 548 uint32_t six_zone_len; 549 uint32_t *six_zone_curve_p0; 550 uint32_t *six_zone_curve_p1; 551 }; 552 553 554 struct mdp_pa_v2_cfg_data { 555 uint32_t version; 556 uint32_t block; 557 uint32_t flags; 558 struct mdp_pa_v2_data pa_v2_data; 559 void *cfg_payload; 560 }; 561 562 563 enum { 564 mdp_igc_rec601 = 1, 565 mdp_igc_rec709, 566 mdp_igc_srgb, 567 mdp_igc_custom, 568 mdp_igc_rec_max, 569 }; 570 571 struct mdp_igc_lut_data { 572 uint32_t block; 573 uint32_t version; 574 uint32_t len, ops; 575 uint32_t *c0_c1_data; 576 uint32_t *c2_data; 577 void *cfg_payload; 578 }; 579 580 struct mdp_igc_lut_data_v1_7 { 581 uint32_t table_fmt; 582 uint32_t len; 583 uint32_t *c0_c1_data; 584 uint32_t *c2_data; 585 }; 586 587 struct mdp_histogram_cfg { 588 uint32_t ops; 589 uint32_t block; 590 uint8_t frame_cnt; 591 uint8_t bit_mask; 592 uint16_t num_bins; 593 }; 594 595 struct mdp_hist_lut_data_v1_7 { 596 uint32_t len; 597 uint32_t *data; 598 }; 599 600 struct mdp_hist_lut_data { 601 uint32_t block; 602 uint32_t version; 603 uint32_t hist_lut_first; 604 uint32_t ops; 605 uint32_t len; 606 uint32_t *data; 607 void *cfg_payload; 608 }; 609 610 struct mdp_pcc_coeff { 611 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; 612 }; 613 614 struct mdp_pcc_coeff_v1_7 { 615 uint32_t c, r, g, b, rg, gb, rb, rgb; 616 }; 617 618 struct mdp_pcc_data_v1_7 { 619 struct mdp_pcc_coeff_v1_7 r, g, b; 620 }; 621 622 struct mdp_pcc_cfg_data { 623 uint32_t version; 624 uint32_t block; 625 uint32_t ops; 626 struct mdp_pcc_coeff r, g, b; 627 void *cfg_payload; 628 }; 629 630 enum { 631 mdp_lut_igc, 632 mdp_lut_pgc, 633 mdp_lut_hist, 634 mdp_lut_rgb, 635 mdp_lut_max, 636 }; 637 struct mdp_overlay_pp_params { 638 uint32_t config_ops; 639 struct mdp_csc_cfg csc_cfg; 640 struct mdp_qseed_cfg qseed_cfg[2]; 641 struct mdp_pa_cfg pa_cfg; 642 struct mdp_pa_v2_data pa_v2_cfg; 643 struct mdp_igc_lut_data igc_cfg; 644 struct mdp_sharp_cfg sharp_cfg; 645 struct mdp_histogram_cfg hist_cfg; 646 struct mdp_hist_lut_data hist_lut_cfg; 647 /* PAv2 cfg data for PA 2.x versions */ 648 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 649 struct mdp_pcc_cfg_data pcc_cfg_data; 650 }; 651 652 /** 653 * enum mdss_mdp_blend_op - Different blend operations set by userspace 654 * 655 * @BLEND_OP_NOT_DEFINED: No blend operation defined for the layer. 656 * @BLEND_OP_OPAQUE: Apply a constant blend operation. The layer 657 * would appear opaque in case fg plane alpha is 658 * 0xff. 659 * @BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already has 660 * alpha pre-multiplication done. If fg plane alpha 661 * is less than 0xff, apply modulation as well. This 662 * operation is intended on layers having alpha 663 * channel. 664 * @BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not alpha 665 * pre-multiplied. Apply pre-multiplication. If fg 666 * plane alpha is less than 0xff, apply modulation as 667 * well. 668 * @BLEND_OP_MAX: Used to track maximum blend operation possible by 669 * mdp. 670 */ 671 enum mdss_mdp_blend_op { 672 BLEND_OP_NOT_DEFINED = 0, 673 BLEND_OP_OPAQUE, 674 BLEND_OP_PREMULTIPLIED, 675 BLEND_OP_COVERAGE, 676 BLEND_OP_MAX, 677 }; 678 679 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 680 #define MAX_PLANES 4 681 struct mdp_scale_data { 682 uint8_t enable_pxl_ext; 683 684 int init_phase_x[MAX_PLANES]; 685 int phase_step_x[MAX_PLANES]; 686 int init_phase_y[MAX_PLANES]; 687 int phase_step_y[MAX_PLANES]; 688 689 int num_ext_pxls_left[MAX_PLANES]; 690 int num_ext_pxls_right[MAX_PLANES]; 691 int num_ext_pxls_top[MAX_PLANES]; 692 int num_ext_pxls_btm[MAX_PLANES]; 693 694 int left_ftch[MAX_PLANES]; 695 int left_rpt[MAX_PLANES]; 696 int right_ftch[MAX_PLANES]; 697 int right_rpt[MAX_PLANES]; 698 699 int top_rpt[MAX_PLANES]; 700 int btm_rpt[MAX_PLANES]; 701 int top_ftch[MAX_PLANES]; 702 int btm_ftch[MAX_PLANES]; 703 704 uint32_t roi_w[MAX_PLANES]; 705 }; 706 707 /** 708 * enum mdp_overlay_pipe_type - Different pipe type set by userspace 709 * 710 * @PIPE_TYPE_AUTO: Not specified, pipe will be selected according to flags. 711 * @PIPE_TYPE_VIG: VIG pipe. 712 * @PIPE_TYPE_RGB: RGB pipe. 713 * @PIPE_TYPE_DMA: DMA pipe. 714 * @PIPE_TYPE_CURSOR: CURSOR pipe. 715 * @PIPE_TYPE_MAX: Used to track maximum number of pipe type. 716 */ 717 enum mdp_overlay_pipe_type { 718 PIPE_TYPE_AUTO = 0, 719 PIPE_TYPE_VIG, 720 PIPE_TYPE_RGB, 721 PIPE_TYPE_DMA, 722 PIPE_TYPE_CURSOR, 723 PIPE_TYPE_MAX, 724 }; 725 726 /** 727 * struct mdp_overlay - overlay surface structure 728 * @src: Source image information (width, height, format). 729 * @src_rect: Source crop rectangle, portion of image that will be fetched. 730 * This should always be within boundaries of source image. 731 * @dst_rect: Destination rectangle, the position and size of image on screen. 732 * This should always be within panel boundaries. 733 * @z_order: Blending stage to occupy in display, if multiple layers are 734 * present, highest z_order usually means the top most visible 735 * layer. The range acceptable is from 0-3 to support blending 736 * up to 4 layers. 737 * @is_fg: This flag is used to disable blending of any layers with z_order 738 * less than this overlay. It means that any layers with z_order 739 * less than this layer will not be blended and will be replaced 740 * by the background border color. 741 * @alpha: Used to set plane opacity. The range can be from 0-255, where 742 * 0 means completely transparent and 255 means fully opaque. 743 * @transp_mask: Color used as color key for transparency. Any pixel in fetched 744 * image matching this color will be transparent when blending. 745 * The color should be in same format as the source image format. 746 * @flags: This is used to customize operation of overlay. See MDP flags 747 * for more information. 748 * @pipe_type: Used to specify the type of overlay pipe. 749 * @user_data: DEPRECATED* Used to store user application specific information. 750 * @bg_color: Solid color used to fill the overlay surface when no source 751 * buffer is provided. 752 * @horz_deci: Horizontal decimation value, this indicates the amount of pixels 753 * dropped for each pixel that is fetched from a line. The value 754 * given should be power of two of decimation amount. 755 * 0: no decimation 756 * 1: decimate by 2 (drop 1 pixel for each pixel fetched) 757 * 2: decimate by 4 (drop 3 pixels for each pixel fetched) 758 * 3: decimate by 8 (drop 7 pixels for each pixel fetched) 759 * 4: decimate by 16 (drop 15 pixels for each pixel fetched) 760 * @vert_deci: Vertical decimation value, this indicates the amount of lines 761 * dropped for each line that is fetched from overlay. The value 762 * given should be power of two of decimation amount. 763 * 0: no decimation 764 * 1: decimation by 2 (drop 1 line for each line fetched) 765 * 2: decimation by 4 (drop 3 lines for each line fetched) 766 * 3: decimation by 8 (drop 7 lines for each line fetched) 767 * 4: decimation by 16 (drop 15 lines for each line fetched) 768 * @overlay_pp_cfg: Overlay post processing configuration, for more information 769 * see struct mdp_overlay_pp_params. 770 * @priority: Priority is returned by the driver when overlay is set for the 771 * first time. It indicates the priority of the underlying pipe 772 * serving the overlay. This priority can be used by user-space 773 * in source split when pipes are re-used and shuffled around to 774 * reduce fallbacks. 775 */ 776 struct mdp_overlay { 777 struct msmfb_img src; 778 struct mdp_rect src_rect; 779 struct mdp_rect dst_rect; 780 uint32_t z_order; /* stage number */ 781 uint32_t is_fg; /* control alpha & transp */ 782 uint32_t alpha; 783 uint32_t blend_op; 784 uint32_t transp_mask; 785 uint32_t flags; 786 uint32_t pipe_type; 787 uint32_t id; 788 uint8_t priority; 789 uint32_t user_data[6]; 790 uint32_t bg_color; 791 uint8_t horz_deci; 792 uint8_t vert_deci; 793 struct mdp_overlay_pp_params overlay_pp_cfg; 794 struct mdp_scale_data scale; 795 uint8_t color_space; 796 uint32_t frame_rate; 797 }; 798 799 struct msmfb_overlay_3d { 800 uint32_t is_3d; 801 uint32_t width; 802 uint32_t height; 803 }; 804 805 806 struct msmfb_overlay_blt { 807 uint32_t enable; 808 uint32_t offset; 809 uint32_t width; 810 uint32_t height; 811 uint32_t bpp; 812 }; 813 814 struct mdp_histogram { 815 uint32_t frame_cnt; 816 uint32_t bin_cnt; 817 uint32_t *r; 818 uint32_t *g; 819 uint32_t *b; 820 }; 821 822 #define MISR_CRC_BATCH_SIZE 32 823 enum { 824 DISPLAY_MISR_EDP, 825 DISPLAY_MISR_DSI0, 826 DISPLAY_MISR_DSI1, 827 DISPLAY_MISR_HDMI, 828 DISPLAY_MISR_LCDC, 829 DISPLAY_MISR_MDP, 830 DISPLAY_MISR_ATV, 831 DISPLAY_MISR_DSI_CMD, 832 DISPLAY_MISR_MAX 833 }; 834 835 enum { 836 MISR_OP_NONE, 837 MISR_OP_SFM, 838 MISR_OP_MFM, 839 MISR_OP_BM, 840 MISR_OP_MAX 841 }; 842 843 struct mdp_misr { 844 uint32_t block_id; 845 uint32_t frame_count; 846 uint32_t crc_op_mode; 847 uint32_t crc_value[MISR_CRC_BATCH_SIZE]; 848 }; 849 850 /* 851 852 mdp_block_type defines the identifiers for pipes in MDP 4.3 and up 853 854 MDP_BLOCK_RESERVED is provided for backward compatibility and is 855 deprecated. It corresponds to DMA_P. So MDP_BLOCK_DMA_P should be used 856 instead. 857 858 MDP_LOGICAL_BLOCK_DISP_0 identifies the display pipe which fb0 uses, 859 same for others. 860 861 */ 862 863 enum { 864 MDP_BLOCK_RESERVED = 0, 865 MDP_BLOCK_OVERLAY_0, 866 MDP_BLOCK_OVERLAY_1, 867 MDP_BLOCK_VG_1, 868 MDP_BLOCK_VG_2, 869 MDP_BLOCK_RGB_1, 870 MDP_BLOCK_RGB_2, 871 MDP_BLOCK_DMA_P, 872 MDP_BLOCK_DMA_S, 873 MDP_BLOCK_DMA_E, 874 MDP_BLOCK_OVERLAY_2, 875 MDP_LOGICAL_BLOCK_DISP_0 = 0x10, 876 MDP_LOGICAL_BLOCK_DISP_1, 877 MDP_LOGICAL_BLOCK_DISP_2, 878 MDP_BLOCK_MAX, 879 }; 880 881 /* 882 * mdp_histogram_start_req is used to provide the parameters for 883 * histogram start request 884 */ 885 886 struct mdp_histogram_start_req { 887 uint32_t block; 888 uint8_t frame_cnt; 889 uint8_t bit_mask; 890 uint16_t num_bins; 891 }; 892 893 /* 894 * mdp_histogram_data is used to return the histogram data, once 895 * the histogram is done/stopped/cance 896 */ 897 898 struct mdp_histogram_data { 899 uint32_t block; 900 uint32_t bin_cnt; 901 uint32_t *c0; 902 uint32_t *c1; 903 uint32_t *c2; 904 uint32_t *extra_info; 905 }; 906 907 908 #define GC_LUT_ENTRIES_V1_7 512 909 910 struct mdp_ar_gc_lut_data { 911 uint32_t x_start; 912 uint32_t slope; 913 uint32_t offset; 914 }; 915 916 struct mdp_pgc_lut_data { 917 uint32_t version; 918 uint32_t block; 919 uint32_t flags; 920 uint8_t num_r_stages; 921 uint8_t num_g_stages; 922 uint8_t num_b_stages; 923 struct mdp_ar_gc_lut_data *r_data; 924 struct mdp_ar_gc_lut_data *g_data; 925 struct mdp_ar_gc_lut_data *b_data; 926 void *cfg_payload; 927 }; 928 929 #define PGC_LUT_ENTRIES 1024 930 struct mdp_pgc_lut_data_v1_7 { 931 uint32_t len; 932 uint32_t *c0_data; 933 uint32_t *c1_data; 934 uint32_t *c2_data; 935 }; 936 937 /* 938 * mdp_rgb_lut_data is used to provide parameters for configuring the 939 * generic RGB lut in case of gamma correction or other LUT updation usecases 940 */ 941 struct mdp_rgb_lut_data { 942 uint32_t flags; 943 uint32_t lut_type; 944 struct fb_cmap cmap; 945 }; 946 947 enum { 948 mdp_rgb_lut_gc, 949 mdp_rgb_lut_hist, 950 }; 951 952 struct mdp_lut_cfg_data { 953 uint32_t lut_type; 954 union { 955 struct mdp_igc_lut_data igc_lut_data; 956 struct mdp_pgc_lut_data pgc_lut_data; 957 struct mdp_hist_lut_data hist_lut_data; 958 struct mdp_rgb_lut_data rgb_lut_data; 959 } data; 960 }; 961 962 struct mdp_bl_scale_data { 963 uint32_t min_lvl; 964 uint32_t scale; 965 }; 966 967 struct mdp_pa_cfg_data { 968 uint32_t block; 969 struct mdp_pa_cfg pa_data; 970 }; 971 972 struct mdp_dither_data_v1_7 { 973 uint32_t g_y_depth; 974 uint32_t r_cr_depth; 975 uint32_t b_cb_depth; 976 }; 977 978 struct mdp_dither_cfg_data { 979 uint32_t version; 980 uint32_t block; 981 uint32_t flags; 982 uint32_t mode; 983 uint32_t g_y_depth; 984 uint32_t r_cr_depth; 985 uint32_t b_cb_depth; 986 void *cfg_payload; 987 }; 988 989 #define MDP_GAMUT_TABLE_NUM 8 990 #define MDP_GAMUT_TABLE_NUM_V1_7 4 991 #define MDP_GAMUT_SCALE_OFF_TABLE_NUM 3 992 #define MDP_GAMUT_TABLE_V1_7_SZ 1229 993 #define MDP_GAMUT_SCALE_OFF_SZ 16 994 #define MDP_GAMUT_TABLE_V1_7_COARSE_SZ 32 995 996 struct mdp_gamut_cfg_data { 997 uint32_t block; 998 uint32_t flags; 999 uint32_t version; 1000 /* v1 version specific params */ 1001 uint32_t gamut_first; 1002 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; 1003 uint16_t *r_tbl[MDP_GAMUT_TABLE_NUM]; 1004 uint16_t *g_tbl[MDP_GAMUT_TABLE_NUM]; 1005 uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM]; 1006 /* params for newer versions of gamut */ 1007 void *cfg_payload; 1008 }; 1009 1010 enum { 1011 mdp_gamut_fine_mode = 0x1, 1012 mdp_gamut_coarse_mode, 1013 }; 1014 1015 struct mdp_gamut_data_v1_7 { 1016 uint32_t mode; 1017 uint32_t map_en; 1018 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM_V1_7]; 1019 uint32_t *c0_data[MDP_GAMUT_TABLE_NUM_V1_7]; 1020 uint32_t *c1_c2_data[MDP_GAMUT_TABLE_NUM_V1_7]; 1021 uint32_t tbl_scale_off_sz[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 1022 uint32_t *scale_off_data[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 1023 }; 1024 1025 struct mdp_calib_config_data { 1026 uint32_t ops; 1027 uint32_t addr; 1028 uint32_t data; 1029 }; 1030 1031 struct mdp_calib_config_buffer { 1032 uint32_t ops; 1033 uint32_t size; 1034 uint32_t *buffer; 1035 }; 1036 1037 struct mdp_calib_dcm_state { 1038 uint32_t ops; 1039 uint32_t dcm_state; 1040 }; 1041 1042 enum { 1043 DCM_UNINIT, 1044 DCM_UNBLANK, 1045 DCM_ENTER, 1046 DCM_EXIT, 1047 DCM_BLANK, 1048 DTM_ENTER, 1049 DTM_EXIT, 1050 }; 1051 1052 #define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000 1053 #define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000 1054 #define MDSS_PP_SPLIT_MASK 0x30000000 1055 1056 #define MDSS_MAX_BL_BRIGHTNESS 255 1057 #define AD_BL_LIN_LEN 256 1058 #define AD_BL_ATT_LUT_LEN 33 1059 1060 #define MDSS_AD_MODE_AUTO_BL 0x0 1061 #define MDSS_AD_MODE_AUTO_STR 0x1 1062 #define MDSS_AD_MODE_TARG_STR 0x3 1063 #define MDSS_AD_MODE_MAN_STR 0x7 1064 #define MDSS_AD_MODE_CALIB 0xF 1065 1066 #define MDP_PP_AD_INIT 0x10 1067 #define MDP_PP_AD_CFG 0x20 1068 1069 struct mdss_ad_init { 1070 uint32_t asym_lut[33]; 1071 uint32_t color_corr_lut[33]; 1072 uint8_t i_control[2]; 1073 uint16_t black_lvl; 1074 uint16_t white_lvl; 1075 uint8_t var; 1076 uint8_t limit_ampl; 1077 uint8_t i_dither; 1078 uint8_t slope_max; 1079 uint8_t slope_min; 1080 uint8_t dither_ctl; 1081 uint8_t format; 1082 uint8_t auto_size; 1083 uint16_t frame_w; 1084 uint16_t frame_h; 1085 uint8_t logo_v; 1086 uint8_t logo_h; 1087 uint32_t alpha; 1088 uint32_t alpha_base; 1089 uint32_t al_thresh; 1090 uint32_t bl_lin_len; 1091 uint32_t bl_att_len; 1092 uint32_t *bl_lin; 1093 uint32_t *bl_lin_inv; 1094 uint32_t *bl_att_lut; 1095 }; 1096 1097 #define MDSS_AD_BL_CTRL_MODE_EN 1 1098 #define MDSS_AD_BL_CTRL_MODE_DIS 0 1099 struct mdss_ad_cfg { 1100 uint32_t mode; 1101 uint32_t al_calib_lut[33]; 1102 uint16_t backlight_min; 1103 uint16_t backlight_max; 1104 uint16_t backlight_scale; 1105 uint16_t amb_light_min; 1106 uint16_t filter[2]; 1107 uint16_t calib[4]; 1108 uint8_t strength_limit; 1109 uint8_t t_filter_recursion; 1110 uint16_t stab_itr; 1111 uint32_t bl_ctrl_mode; 1112 }; 1113 1114 /* ops uses standard MDP_PP_* flags */ 1115 struct mdss_ad_init_cfg { 1116 uint32_t ops; 1117 union { 1118 struct mdss_ad_init init; 1119 struct mdss_ad_cfg cfg; 1120 } params; 1121 }; 1122 1123 /* mode uses MDSS_AD_MODE_* flags */ 1124 struct mdss_ad_input { 1125 uint32_t mode; 1126 union { 1127 uint32_t amb_light; 1128 uint32_t strength; 1129 uint32_t calib_bl; 1130 } in; 1131 uint32_t output; 1132 }; 1133 1134 #define MDSS_CALIB_MODE_BL 0x1 1135 struct mdss_calib_cfg { 1136 uint32_t ops; 1137 uint32_t calib_mask; 1138 }; 1139 1140 enum { 1141 mdp_op_pcc_cfg, 1142 mdp_op_csc_cfg, 1143 mdp_op_lut_cfg, 1144 mdp_op_qseed_cfg, 1145 mdp_bl_scale_cfg, 1146 mdp_op_pa_cfg, 1147 mdp_op_pa_v2_cfg, 1148 mdp_op_dither_cfg, 1149 mdp_op_gamut_cfg, 1150 mdp_op_calib_cfg, 1151 mdp_op_ad_cfg, 1152 mdp_op_ad_input, 1153 mdp_op_calib_mode, 1154 mdp_op_calib_buffer, 1155 mdp_op_calib_dcm_state, 1156 mdp_op_max, 1157 }; 1158 1159 enum { 1160 WB_FORMAT_NV12, 1161 WB_FORMAT_RGB_565, 1162 WB_FORMAT_RGB_888, 1163 WB_FORMAT_xRGB_8888, 1164 WB_FORMAT_ARGB_8888, 1165 WB_FORMAT_BGRA_8888, 1166 WB_FORMAT_BGRX_8888, 1167 WB_FORMAT_ARGB_8888_INPUT_ALPHA /* Need to support */ 1168 }; 1169 1170 struct msmfb_mdp_pp { 1171 uint32_t op; 1172 union { 1173 struct mdp_pcc_cfg_data pcc_cfg_data; 1174 struct mdp_csc_cfg_data csc_cfg_data; 1175 struct mdp_lut_cfg_data lut_cfg_data; 1176 struct mdp_qseed_cfg_data qseed_cfg_data; 1177 struct mdp_bl_scale_data bl_scale_data; 1178 struct mdp_pa_cfg_data pa_cfg_data; 1179 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 1180 struct mdp_dither_cfg_data dither_cfg_data; 1181 struct mdp_gamut_cfg_data gamut_cfg_data; 1182 struct mdp_calib_config_data calib_cfg; 1183 struct mdss_ad_init_cfg ad_init_cfg; 1184 struct mdss_calib_cfg mdss_calib_cfg; 1185 struct mdss_ad_input ad_input; 1186 struct mdp_calib_config_buffer calib_buffer; 1187 struct mdp_calib_dcm_state calib_dcm; 1188 } data; 1189 }; 1190 1191 #define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1 1192 enum { 1193 metadata_op_none, 1194 metadata_op_base_blend, 1195 metadata_op_frame_rate, 1196 metadata_op_vic, 1197 metadata_op_wb_format, 1198 metadata_op_wb_secure, 1199 metadata_op_get_caps, 1200 metadata_op_crc, 1201 metadata_op_get_ion_fd, 1202 metadata_op_max 1203 }; 1204 1205 struct mdp_blend_cfg { 1206 uint32_t is_premultiplied; 1207 }; 1208 1209 struct mdp_mixer_cfg { 1210 uint32_t writeback_format; 1211 uint32_t alpha; 1212 }; 1213 1214 struct mdss_hw_caps { 1215 uint32_t mdp_rev; 1216 uint8_t rgb_pipes; 1217 uint8_t vig_pipes; 1218 uint8_t dma_pipes; 1219 uint8_t max_smp_cnt; 1220 uint8_t smp_per_pipe; 1221 uint32_t features; 1222 }; 1223 1224 struct msmfb_metadata { 1225 uint32_t op; 1226 uint32_t flags; 1227 union { 1228 struct mdp_misr misr_request; 1229 struct mdp_blend_cfg blend_cfg; 1230 struct mdp_mixer_cfg mixer_cfg; 1231 uint32_t panel_frame_rate; 1232 uint32_t video_info_code; 1233 struct mdss_hw_caps caps; 1234 uint8_t secure_en; 1235 int fbmem_ionfd; 1236 } data; 1237 }; 1238 1239 #define MDP_MAX_FENCE_FD 32 1240 #define MDP_BUF_SYNC_FLAG_WAIT 1 1241 #define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10 1242 1243 struct mdp_buf_sync { 1244 uint32_t flags; 1245 uint32_t acq_fen_fd_cnt; 1246 uint32_t session_id; 1247 int *acq_fen_fd; 1248 int *rel_fen_fd; 1249 int *retire_fen_fd; 1250 }; 1251 1252 struct mdp_async_blit_req_list { 1253 struct mdp_buf_sync sync; 1254 uint32_t count; 1255 struct mdp_blit_req req[]; 1256 }; 1257 1258 #define MDP_DISPLAY_COMMIT_OVERLAY 1 1259 1260 struct mdp_display_commit { 1261 uint32_t flags; 1262 uint32_t wait_for_finish; 1263 struct fb_var_screeninfo var; 1264 /* 1265 * user needs to follow guidelines as per below rules 1266 * 1. source split is enabled: l_roi = roi and r_roi = 0 1267 * 2. source split is disabled: 1268 * 2.1 split display: l_roi = l_roi and r_roi = r_roi 1269 * 2.2 non split display: l_roi = roi and r_roi = 0 1270 */ 1271 struct mdp_rect l_roi; 1272 struct mdp_rect r_roi; 1273 }; 1274 1275 /** 1276 * struct mdp_overlay_list - argument for ioctl MSMFB_OVERLAY_PREPARE 1277 * @num_overlays: Number of overlay layers as part of the frame. 1278 * @overlay_list: Pointer to a list of overlay structures identifying 1279 * the layers as part of the frame 1280 * @flags: Flags can be used to extend behavior. 1281 * @processed_overlays: Output parameter indicating how many pipes were 1282 * successful. If there are no errors this number should 1283 * match num_overlays. Otherwise it will indicate the last 1284 * successful index for overlay that couldn't be set. 1285 */ 1286 struct mdp_overlay_list { 1287 uint32_t num_overlays; 1288 struct mdp_overlay **overlay_list; 1289 uint32_t flags; 1290 uint32_t processed_overlays; 1291 }; 1292 1293 struct mdp_page_protection { 1294 uint32_t page_protection; 1295 }; 1296 1297 1298 struct mdp_mixer_info { 1299 int pndx; 1300 int pnum; 1301 int ptype; 1302 int mixer_num; 1303 int z_order; 1304 }; 1305 1306 #define MAX_PIPE_PER_MIXER 7 1307 1308 struct msmfb_mixer_info_req { 1309 int mixer_num; 1310 int cnt; 1311 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER]; 1312 }; 1313 1314 enum { 1315 DISPLAY_SUBSYSTEM_ID, 1316 ROTATOR_SUBSYSTEM_ID, 1317 }; 1318 1319 enum { 1320 MDP_IOMMU_DOMAIN_CP, 1321 MDP_IOMMU_DOMAIN_NS, 1322 }; 1323 1324 enum { 1325 MDP_WRITEBACK_MIRROR_OFF, 1326 MDP_WRITEBACK_MIRROR_ON, 1327 MDP_WRITEBACK_MIRROR_PAUSE, 1328 MDP_WRITEBACK_MIRROR_RESUME, 1329 }; 1330 1331 enum mdp_color_space { 1332 MDP_CSC_ITU_R_601, 1333 MDP_CSC_ITU_R_601_FR, 1334 MDP_CSC_ITU_R_709, 1335 }; 1336 1337 enum { 1338 mdp_igc_v1_7 = 1, 1339 mdp_igc_vmax, 1340 mdp_hist_lut_v1_7, 1341 mdp_hist_lut_vmax, 1342 mdp_pgc_v1_7, 1343 mdp_pgc_vmax, 1344 mdp_dither_v1_7, 1345 mdp_dither_vmax, 1346 mdp_gamut_v1_7, 1347 mdp_gamut_vmax, 1348 mdp_pa_v1_7, 1349 mdp_pa_vmax, 1350 mdp_pcc_v1_7, 1351 mdp_pcc_vmax, 1352 mdp_pp_legacy, 1353 }; 1354 1355 /* PP Features */ 1356 enum { 1357 IGC = 1, 1358 PCC, 1359 GC, 1360 PA, 1361 GAMUT, 1362 DITHER, 1363 QSEED, 1364 HIST_LUT, 1365 HIST, 1366 PP_FEATURE_MAX, 1367 }; 1368 1369 struct mdp_pp_feature_version { 1370 uint32_t pp_feature; 1371 uint32_t version_info; 1372 }; 1373 #endif /*_UAPI_MSM_MDP_H_*/ 1374