1 #ifndef _UAPI_QCEDEV__H 2 #define _UAPI_QCEDEV__H 3 4 #include <linux/types.h> 5 #include <linux/ioctl.h> 6 #include "fips_status.h" 7 8 #define QCEDEV_MAX_SHA_BLOCK_SIZE 64 9 #define QCEDEV_MAX_BEARER 31 10 #define QCEDEV_MAX_KEY_SIZE 64 11 #define QCEDEV_MAX_IV_SIZE 32 12 13 #define QCEDEV_MAX_BUFFERS 16 14 #define QCEDEV_MAX_SHA_DIGEST 32 15 16 #define QCEDEV_USE_PMEM 1 17 #define QCEDEV_NO_PMEM 0 18 19 #define QCEDEV_AES_KEY_128 16 20 #define QCEDEV_AES_KEY_192 24 21 #define QCEDEV_AES_KEY_256 32 22 /** 23 *qcedev_oper_enum: Operation types 24 * @QCEDEV_OPER_ENC: Encrypt 25 * @QCEDEV_OPER_DEC: Decrypt 26 * @QCEDEV_OPER_ENC_NO_KEY: Encrypt. Do not need key to be specified by 27 * user. Key already set by an external processor. 28 * @QCEDEV_OPER_DEC_NO_KEY: Decrypt. Do not need the key to be specified by 29 * user. Key already set by an external processor. 30 */ 31 enum qcedev_oper_enum { 32 QCEDEV_OPER_DEC = 0, 33 QCEDEV_OPER_ENC = 1, 34 QCEDEV_OPER_DEC_NO_KEY = 2, 35 QCEDEV_OPER_ENC_NO_KEY = 3, 36 QCEDEV_OPER_LAST 37 }; 38 39 /** 40 *qcedev_oper_enum: Cipher algorithm types 41 * @QCEDEV_ALG_DES: DES 42 * @QCEDEV_ALG_3DES: 3DES 43 * @QCEDEV_ALG_AES: AES 44 */ 45 enum qcedev_cipher_alg_enum { 46 QCEDEV_ALG_DES = 0, 47 QCEDEV_ALG_3DES = 1, 48 QCEDEV_ALG_AES = 2, 49 QCEDEV_ALG_LAST 50 }; 51 52 /** 53 *qcedev_cipher_mode_enum : AES mode 54 * @QCEDEV_AES_MODE_CBC: CBC 55 * @QCEDEV_AES_MODE_ECB: ECB 56 * @QCEDEV_AES_MODE_CTR: CTR 57 * @QCEDEV_AES_MODE_XTS: XTS 58 * @QCEDEV_AES_MODE_CCM: CCM 59 * @QCEDEV_DES_MODE_CBC: CBC 60 * @QCEDEV_DES_MODE_ECB: ECB 61 */ 62 enum qcedev_cipher_mode_enum { 63 QCEDEV_AES_MODE_CBC = 0, 64 QCEDEV_AES_MODE_ECB = 1, 65 QCEDEV_AES_MODE_CTR = 2, 66 QCEDEV_AES_MODE_XTS = 3, 67 QCEDEV_AES_MODE_CCM = 4, 68 QCEDEV_DES_MODE_CBC = 5, 69 QCEDEV_DES_MODE_ECB = 6, 70 QCEDEV_AES_DES_MODE_LAST 71 }; 72 73 /** 74 *enum qcedev_sha_alg_enum : Secure Hashing Algorithm 75 * @QCEDEV_ALG_SHA1: Digest returned: 20 bytes (160 bits) 76 * @QCEDEV_ALG_SHA256: Digest returned: 32 bytes (256 bit) 77 * @QCEDEV_ALG_SHA1_HMAC: HMAC returned 20 bytes (160 bits) 78 * @QCEDEV_ALG_SHA256_HMAC: HMAC returned 32 bytes (256 bit) 79 * @QCEDEV_ALG_AES_CMAC: Configurable MAC size 80 */ 81 enum qcedev_sha_alg_enum { 82 QCEDEV_ALG_SHA1 = 0, 83 QCEDEV_ALG_SHA256 = 1, 84 QCEDEV_ALG_SHA1_HMAC = 2, 85 QCEDEV_ALG_SHA256_HMAC = 3, 86 QCEDEV_ALG_AES_CMAC = 4, 87 QCEDEV_ALG_SHA_ALG_LAST 88 }; 89 90 /** 91 * struct buf_info - Buffer information 92 * @offset: Offset from the base address of the buffer 93 * (Used when buffer is allocated using PMEM) 94 * @vaddr: Virtual buffer address pointer 95 * @len: Size of the buffer 96 */ 97 struct buf_info { 98 union { 99 uint32_t offset; 100 uint8_t *vaddr; 101 }; 102 uint32_t len; 103 }; 104 105 /** 106 * struct qcedev_vbuf_info - Source and destination Buffer information 107 * @src: Array of buf_info for input/source 108 * @dst: Array of buf_info for output/destination 109 */ 110 struct qcedev_vbuf_info { 111 struct buf_info src[QCEDEV_MAX_BUFFERS]; 112 struct buf_info dst[QCEDEV_MAX_BUFFERS]; 113 }; 114 115 /** 116 * struct qcedev_pmem_info - Stores PMEM buffer information 117 * @fd_src: Handle to /dev/adsp_pmem used to allocate 118 * memory for input/src buffer 119 * @src: Array of buf_info for input/source 120 * @fd_dst: Handle to /dev/adsp_pmem used to allocate 121 * memory for output/dst buffer 122 * @dst: Array of buf_info for output/destination 123 * @pmem_src_offset: The offset from input/src buffer 124 * (allocated by PMEM) 125 */ 126 struct qcedev_pmem_info { 127 int fd_src; 128 struct buf_info src[QCEDEV_MAX_BUFFERS]; 129 int fd_dst; 130 struct buf_info dst[QCEDEV_MAX_BUFFERS]; 131 }; 132 133 /** 134 * struct qcedev_cipher_op_req - Holds the ciphering request information 135 * @use_pmem (IN): Flag to indicate if buffer source is PMEM 136 * QCEDEV_USE_PMEM/QCEDEV_NO_PMEM 137 * @pmem (IN): Stores PMEM buffer information. 138 * Refer struct qcedev_pmem_info 139 * @vbuf (IN/OUT): Stores Source and destination Buffer information 140 * Refer to struct qcedev_vbuf_info 141 * @data_len (IN): Total Length of input/src and output/dst in bytes 142 * @in_place_op (IN): Indicates whether the operation is inplace where 143 * source == destination 144 * When using PMEM allocated memory, must set this to 1 145 * @enckey (IN): 128 bits of confidentiality key 146 * enckey[0] bit 127-120, enckey[1] bit 119-112,.. 147 * enckey[15] bit 7-0 148 * @encklen (IN): Length of the encryption key(set to 128 bits/16 149 * bytes in the driver) 150 * @iv (IN/OUT): Initialisation vector data 151 * This is updated by the driver, incremented by 152 * number of blocks encrypted/decrypted. 153 * @ivlen (IN): Length of the IV 154 * @byteoffset (IN): Offset in the Cipher BLOCK (applicable and to be set 155 * for AES-128 CTR mode only) 156 * @alg (IN): Type of ciphering algorithm: AES/DES/3DES 157 * @mode (IN): Mode use when using AES algorithm: ECB/CBC/CTR 158 * Apllicabel when using AES algorithm only 159 * @op (IN): Type of operation: QCEDEV_OPER_DEC/QCEDEV_OPER_ENC or 160 * QCEDEV_OPER_ENC_NO_KEY/QCEDEV_OPER_DEC_NO_KEY 161 * 162 *If use_pmem is set to 0, the driver assumes that memory was not allocated 163 * via PMEM, and kernel will need to allocate memory and copy data from user 164 * space buffer (data_src/dta_dst) and process accordingly and copy data back 165 * to the user space buffer 166 * 167 * If use_pmem is set to 1, the driver assumes that memory was allocated via 168 * PMEM. 169 * The kernel driver will use the fd_src to determine the kernel virtual address 170 * base that maps to the user space virtual address base for the buffer 171 * allocated in user space. 172 * The final input/src and output/dst buffer pointer will be determined 173 * by adding the offsets to the kernel virtual addr. 174 * 175 * If use of hardware key is supported in the target, user can configure the 176 * key paramters (encklen, enckey) to use the hardware key. 177 * In order to use the hardware key, set encklen to 0 and set the enckey 178 * data array to 0. 179 */ 180 struct qcedev_cipher_op_req { 181 uint8_t use_pmem; 182 union { 183 struct qcedev_pmem_info pmem; 184 struct qcedev_vbuf_info vbuf; 185 }; 186 uint32_t entries; 187 uint32_t data_len; 188 uint8_t in_place_op; 189 uint8_t enckey[QCEDEV_MAX_KEY_SIZE]; 190 uint32_t encklen; 191 uint8_t iv[QCEDEV_MAX_IV_SIZE]; 192 uint32_t ivlen; 193 uint32_t byteoffset; 194 enum qcedev_cipher_alg_enum alg; 195 enum qcedev_cipher_mode_enum mode; 196 enum qcedev_oper_enum op; 197 }; 198 199 /** 200 * struct qcedev_sha_op_req - Holds the hashing request information 201 * @data (IN): Array of pointers to the data to be hashed 202 * @entries (IN): Number of buf_info entries in the data array 203 * @data_len (IN): Length of data to be hashed 204 * @digest (IN/OUT): Returns the hashed data information 205 * @diglen (OUT): Size of the hashed/digest data 206 * @authkey (IN): Pointer to authentication key for HMAC 207 * @authklen (IN): Size of the authentication key 208 * @alg (IN): Secure Hash algorithm 209 */ 210 struct qcedev_sha_op_req { 211 struct buf_info data[QCEDEV_MAX_BUFFERS]; 212 uint32_t entries; 213 uint32_t data_len; 214 uint8_t digest[QCEDEV_MAX_SHA_DIGEST]; 215 uint32_t diglen; 216 uint8_t *authkey; 217 uint32_t authklen; 218 enum qcedev_sha_alg_enum alg; 219 }; 220 221 /** 222 * struct qfips_verify_t - Holds data for FIPS Integrity test 223 * @kernel_size (IN): Size of kernel Image 224 * @kernel (IN): pointer to buffer containing the kernel Image 225 */ 226 struct qfips_verify_t { 227 unsigned kernel_size; 228 void *kernel; 229 }; 230 231 struct file; 232 extern long qcedev_ioctl(struct file *file, 233 unsigned cmd, unsigned long arg); 234 235 #define QCEDEV_IOC_MAGIC 0x87 236 237 #define QCEDEV_IOCTL_ENC_REQ \ 238 _IOWR(QCEDEV_IOC_MAGIC, 1, struct qcedev_cipher_op_req) 239 #define QCEDEV_IOCTL_DEC_REQ \ 240 _IOWR(QCEDEV_IOC_MAGIC, 2, struct qcedev_cipher_op_req) 241 #define QCEDEV_IOCTL_SHA_INIT_REQ \ 242 _IOWR(QCEDEV_IOC_MAGIC, 3, struct qcedev_sha_op_req) 243 #define QCEDEV_IOCTL_SHA_UPDATE_REQ \ 244 _IOWR(QCEDEV_IOC_MAGIC, 4, struct qcedev_sha_op_req) 245 #define QCEDEV_IOCTL_SHA_FINAL_REQ \ 246 _IOWR(QCEDEV_IOC_MAGIC, 5, struct qcedev_sha_op_req) 247 #define QCEDEV_IOCTL_GET_SHA_REQ \ 248 _IOWR(QCEDEV_IOC_MAGIC, 6, struct qcedev_sha_op_req) 249 #define QCEDEV_IOCTL_LOCK_CE \ 250 _IO(QCEDEV_IOC_MAGIC, 7) 251 #define QCEDEV_IOCTL_UNLOCK_CE \ 252 _IO(QCEDEV_IOC_MAGIC, 8) 253 #define QCEDEV_IOCTL_GET_CMAC_REQ \ 254 _IOWR(QCEDEV_IOC_MAGIC, 9, struct qcedev_sha_op_req) 255 #define QCEDEV_IOCTL_UPDATE_FIPS_STATUS \ 256 _IOWR(QCEDEV_IOC_MAGIC, 10, enum fips_status) 257 #define QCEDEV_IOCTL_QUERY_FIPS_STATUS \ 258 _IOR(QCEDEV_IOC_MAGIC, 11, enum fips_status) 259 #endif /* _UAPI_QCEDEV__H */ 260