Lines Matching refs:mn10300_opcodes
1144 * mn10300-opc.c (mn10300_opcodes): Add "break" instruction.
1227 * mn10300-opc.c (mn10300_opcodes): Fix mask field for
1267 * mn10300-opc.c (mn10300_opcodes): Remove redundant "lcc"
1296 * mn10300-opc.c (mn10300_opcodes): Fix masks on several insns.
1300 (mn10300_opcodes): Use REGS for register list in "movm" instructions.
1308 * mn10300-opc.c (mn10300_opcodes): Demand parens around
1313 * mn10300-opc.c (mn10300_opcodes): Use DN01 for putx and
1322 (mn10300_opcodes): Use new operands as needed.
1326 (mn10300_opcodes): Use new IMM32_LOWSHIFT8 as needed.
1331 (mn10300_opcodes): Fix single bit error in mov imm32,dn insn.
1354 (mn10300_opcodes): Use DN01 and AN01 for mov/cmp imm8,DN/AN
1405 * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode
1414 * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode field
1419 * mn10300-opc.c (mn10300_opcodes): Fix destination register
1428 * mn10300-opc.c (mn10300_opcodes): Add "extended" instructions,
1436 (mn10300_opcodes): Surround all memory addresses with "PAREN"
1439 * mn10300-opc.c (mn10300_opcodes): Fix typos in yesterday's
1447 (mn10300_opcodes): Break opcode format out into its own field.
1459 * mn10300-opc.c (mn10300_opcodes): Add opcode & masks for
1462 * mn10300-opc.c (mn10300_opcodes): Start fleshing out the