| /external/llvm/lib/Target/AArch64/ |
| D | AArch64PBQPRegAlloc.cpp | 159 bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, in addIntraChainConstraint()
243 void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, in addInterChainConstraint()
363 unsigned Rd = MI.getOperand(0).getReg(); in apply() local
373 unsigned Rd = MI.getOperand(0).getReg(); in apply() local
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1789 unsigned Rd = fieldFromInstruction32(Insn, 8, 4); in DecodeT2MOVTWInstruction() local
1813 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); in DecodeArmMOVTWInstruction() local
1839 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); in DecodeSMLAInstruction() local
1959 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); in DecodeVLDInstruction() local
2208 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); in DecodeVSTInstruction() local
2458 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); in DecodeVLD1DupInstruction() local
2497 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); in DecodeVLD2DupInstruction() local
2533 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); in DecodeVLD3DupInstruction() local
2568 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); in DecodeVLD4DupInstruction() local
2621 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); in DecodeNEONModImmInstruction() local
[all …]
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| /external/capstone/arch/AArch64/ |
| D | AArch64Disassembler.c | 738 unsigned Rd = fieldFromInstruction(Insn, 0, 5); in DecodeFMOVLaneInstruction() local
843 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeThreeAddrSRegInstruction() local
907 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeMoveImmInstruction() local
1398 unsigned Rd, Rn, Rm; in DecodeAddSubERegInstruction() local
1458 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeLogicalImmInstruction() local
1491 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmInstruction() local
1531 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmTiedInstruction() local
1549 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAdrInstruction() local
1567 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeBaseAddSubImm() local
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| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 652 unsigned Rd = fieldFromInstruction(Insn, 0, 5); in DecodeFMOVLaneInstruction() local
743 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeThreeAddrSRegInstruction() local
805 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeMoveImmInstruction() local
1296 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAddSubERegInstruction() local
1353 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeLogicalImmInstruction() local
1384 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmInstruction() local
1423 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmTiedInstruction() local
1440 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAdrInstruction() local
1459 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeBaseAddSubImm() local
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| /external/capstone/arch/ARM/ |
| D | ARMDisassembler.c | 1891 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); in DecodeQADDInstruction() local
2096 unsigned Rd = fieldFromInstruction_4(Insn, 8, 4); in DecodeT2MOVTWInstruction() local
2120 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); in DecodeArmMOVTWInstruction() local
2147 unsigned Rd = fieldFromInstruction_4(Insn, 16, 4); in DecodeSMLAInstruction() local
2289 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); in DecodeVLDInstruction() local
2623 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); in DecodeVSTInstruction() local
2895 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); in DecodeVLD1DupInstruction() local
2943 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); in DecodeVLD2DupInstruction() local
2992 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); in DecodeVLD3DupInstruction() local
3028 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); in DecodeVLD4DupInstruction() local
[all …]
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| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1844 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeQADDInstruction() local
2070 unsigned Rd = fieldFromInstruction(Insn, 8, 4); in DecodeT2MOVTWInstruction() local
2094 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeArmMOVTWInstruction() local
2121 unsigned Rd = fieldFromInstruction(Insn, 16, 4); in DecodeSMLAInstruction() local
2334 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLDInstruction() local
2659 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVSTInstruction() local
2930 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD1DupInstruction() local
2977 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD2DupInstruction() local
3025 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD3DupInstruction() local
3060 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD4DupInstruction() local
[all …]
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerMIPS32.cpp | 271 const IValueT Rd = encodeGPRegister(OpRd, "Rd", InsnName); in emitRdRtSa() local
284 const IValueT Rd = encodeGPRegister(OpRd, "Rd", InsnName); in emitRdRsRt() local
527 const IValueT Rd = encodeGPRegister(OpRd, "Rd", "clz"); in clz() local
657 const IValueT Rd = in jalr() local
772 IValueT Rd = encodeGPRegister(OpRd, "Rd", "mfhi"); in mfhi() local
779 IValueT Rd = encodeGPRegister(OpRd, "Rd", "mflo"); in mflo() local
819 const IValueT Rd = encodeGPRegister(OpRd, "Rd", "pseudo-move"); in move() local
836 const IValueT Rd = encodeGPRegister(OpRd, "Rd", "movf"); in movf() local
871 const IValueT Rd = encodeGPRegister(OpRd, "Rd", "movt"); in movt() local
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| D | IceAssemblerARM32.cpp | 796 IValueT Rd, IValueT Imm12, in emitType01()
818 IValueT Rd = encodeGPRegister(OpRd, "Rd", InstName); in emitType01() local
824 IValueT Rd, IValueT Rn, const Operand *OpSrc1, in emitType01()
928 constexpr IValueT Rd = RegARM32::Encoded_Reg_r0; in emitCompareOp() local
1060 void AssemblerARM32::emitDivOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, in emitDivOp()
1127 void AssemblerARM32::emitMulOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, in emitMulOp()
1157 IValueT Rd = encodeGPRegister(OpRd, "Rd", InstName); in emitSignExtend() local
1463 IValueT Rd = encodeGPRegister(OpRd, RdName, ClzName); in clz() local
1623 IValueT Rd = encodeGPRegister(OpRd, "Rd", InstName); in emitMemExOp() local
1691 IValueT Rd = encodeGPRegister(OpRd, "Rd", InstName); in emitShift() local
[all …]
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| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1903 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
1942 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
1952 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
2150 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
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| /external/mesa3d/src/mesa/swrast/ |
| D | s_blend.c | 486 const GLfloat Rd = dest[i][RCOMP]; in blend_general_float() local
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| /external/v8/src/arm64/ |
| D | assembler-arm64.h | 1701 static Instr Rd(CPURegister rd) { in Rd() function
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| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 2584 static Instr Rd(CPURegister rd) { in Rd() function
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 2203 unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg(); in expandAlloca() local
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| D | HexagonInstrInfo.cpp | 1238 unsigned Rd = Op0.getReg(); in expandPostRAPseudo() local
|