1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9
10 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "llvm/MC/MCContext.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCFixedLenDisassembler.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/LEB128.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Support/raw_ostream.h"
25 #include <vector>
26
27 using namespace llvm;
28
29 #define DEBUG_TYPE "arm-disassembler"
30
31 typedef MCDisassembler::DecodeStatus DecodeStatus;
32
33 namespace {
34 // Handles the condition code status of instructions in IT blocks
35 class ITStatus
36 {
37 public:
38 // Returns the condition code for instruction in IT block
getITCC()39 unsigned getITCC() {
40 unsigned CC = ARMCC::AL;
41 if (instrInITBlock())
42 CC = ITStates.back();
43 return CC;
44 }
45
46 // Advances the IT block state to the next T or E
advanceITState()47 void advanceITState() {
48 ITStates.pop_back();
49 }
50
51 // Returns true if the current instruction is in an IT block
instrInITBlock()52 bool instrInITBlock() {
53 return !ITStates.empty();
54 }
55
56 // Returns true if current instruction is the last instruction in an IT block
instrLastInITBlock()57 bool instrLastInITBlock() {
58 return ITStates.size() == 1;
59 }
60
61 // Called when decoding an IT instruction. Sets the IT state for the following
62 // instructions that for the IT block. Firstcond and Mask correspond to the
63 // fields in the IT instruction encoding.
setITState(char Firstcond,char Mask)64 void setITState(char Firstcond, char Mask) {
65 // (3 - the number of trailing zeros) is the number of then / else.
66 unsigned CondBit0 = Firstcond & 1;
67 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
68 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
69 assert(NumTZ <= 3 && "Invalid IT mask!");
70 // push condition codes onto the stack the correct order for the pops
71 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
72 bool T = ((Mask >> Pos) & 1) == CondBit0;
73 if (T)
74 ITStates.push_back(CCBits);
75 else
76 ITStates.push_back(CCBits ^ 1);
77 }
78 ITStates.push_back(CCBits);
79 }
80
81 private:
82 std::vector<unsigned char> ITStates;
83 };
84 }
85
86 namespace {
87 /// ARM disassembler for all ARM platforms.
88 class ARMDisassembler : public MCDisassembler {
89 public:
ARMDisassembler(const MCSubtargetInfo & STI,MCContext & Ctx)90 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
91 MCDisassembler(STI, Ctx) {
92 }
93
~ARMDisassembler()94 ~ARMDisassembler() override {}
95
96 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
97 ArrayRef<uint8_t> Bytes, uint64_t Address,
98 raw_ostream &VStream,
99 raw_ostream &CStream) const override;
100 };
101
102 /// Thumb disassembler for all Thumb platforms.
103 class ThumbDisassembler : public MCDisassembler {
104 public:
ThumbDisassembler(const MCSubtargetInfo & STI,MCContext & Ctx)105 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
106 MCDisassembler(STI, Ctx) {
107 }
108
~ThumbDisassembler()109 ~ThumbDisassembler() override {}
110
111 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
112 ArrayRef<uint8_t> Bytes, uint64_t Address,
113 raw_ostream &VStream,
114 raw_ostream &CStream) const override;
115
116 private:
117 mutable ITStatus ITBlock;
118 DecodeStatus AddThumbPredicate(MCInst&) const;
119 void UpdateThumbVFPPredicate(MCInst&) const;
120 };
121 }
122
Check(DecodeStatus & Out,DecodeStatus In)123 static bool Check(DecodeStatus &Out, DecodeStatus In) {
124 switch (In) {
125 case MCDisassembler::Success:
126 // Out stays the same.
127 return true;
128 case MCDisassembler::SoftFail:
129 Out = In;
130 return true;
131 case MCDisassembler::Fail:
132 Out = In;
133 return false;
134 }
135 llvm_unreachable("Invalid DecodeStatus!");
136 }
137
138
139 // Forward declare these because the autogenerated code will reference them.
140 // Definitions are further down.
141 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
142 uint64_t Address, const void *Decoder);
143 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
144 unsigned RegNo, uint64_t Address,
145 const void *Decoder);
146 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
147 unsigned RegNo, uint64_t Address,
148 const void *Decoder);
149 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
150 uint64_t Address, const void *Decoder);
151 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
152 uint64_t Address, const void *Decoder);
153 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
154 uint64_t Address, const void *Decoder);
155 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
156 uint64_t Address, const void *Decoder);
157 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
158 uint64_t Address, const void *Decoder);
159 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
160 uint64_t Address, const void *Decoder);
161 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
162 uint64_t Address, const void *Decoder);
163 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
164 unsigned RegNo,
165 uint64_t Address,
166 const void *Decoder);
167 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
168 uint64_t Address, const void *Decoder);
169 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
170 uint64_t Address, const void *Decoder);
171 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
172 unsigned RegNo, uint64_t Address,
173 const void *Decoder);
174
175 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
176 uint64_t Address, const void *Decoder);
177 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
178 uint64_t Address, const void *Decoder);
179 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
180 uint64_t Address, const void *Decoder);
181 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
182 uint64_t Address, const void *Decoder);
183 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
184 uint64_t Address, const void *Decoder);
185
186 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
187 uint64_t Address, const void *Decoder);
188 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
189 uint64_t Address, const void *Decoder);
190 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
191 unsigned Insn,
192 uint64_t Address,
193 const void *Decoder);
194 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
195 uint64_t Address, const void *Decoder);
196 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
197 uint64_t Address, const void *Decoder);
198 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
199 uint64_t Address, const void *Decoder);
200 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
201 uint64_t Address, const void *Decoder);
202
203 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
204 unsigned Insn,
205 uint64_t Adddress,
206 const void *Decoder);
207 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
208 uint64_t Address, const void *Decoder);
209 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
210 uint64_t Address, const void *Decoder);
211 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
212 uint64_t Address, const void *Decoder);
213 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
214 uint64_t Address, const void *Decoder);
215 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
216 uint64_t Address, const void *Decoder);
217 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
218 uint64_t Address, const void *Decoder);
219 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
220 uint64_t Address, const void *Decoder);
221 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
222 uint64_t Address, const void *Decoder);
223 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
224 uint64_t Address, const void *Decoder);
225 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
226 uint64_t Address, const void *Decoder);
227 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
228 uint64_t Address, const void *Decoder);
229 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
230 uint64_t Address, const void *Decoder);
231 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
232 uint64_t Address, const void *Decoder);
233 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
234 uint64_t Address, const void *Decoder);
235 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
236 uint64_t Address, const void *Decoder);
237 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
238 uint64_t Address, const void *Decoder);
239 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
240 uint64_t Address, const void *Decoder);
241 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
242 uint64_t Address, const void *Decoder);
243 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
244 uint64_t Address, const void *Decoder);
245 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
246 uint64_t Address, const void *Decoder);
247 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
248 uint64_t Address, const void *Decoder);
249 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
250 uint64_t Address, const void *Decoder);
251 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
252 uint64_t Address, const void *Decoder);
253 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
254 uint64_t Address, const void *Decoder);
255 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
256 uint64_t Address, const void *Decoder);
257 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
258 uint64_t Address, const void *Decoder);
259 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
260 uint64_t Address, const void *Decoder);
261 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
262 uint64_t Address, const void *Decoder);
263 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
264 uint64_t Address, const void *Decoder);
265 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
266 uint64_t Address, const void *Decoder);
267 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
268 uint64_t Address, const void *Decoder);
269 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
270 uint64_t Address, const void *Decoder);
271 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
272 uint64_t Address, const void *Decoder);
273 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
274 uint64_t Address, const void *Decoder);
275 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
276 uint64_t Address, const void *Decoder);
277 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
278 uint64_t Address, const void *Decoder);
279 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
280 uint64_t Address, const void *Decoder);
281 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
282 uint64_t Address, const void *Decoder);
283 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
284 uint64_t Address, const void *Decoder);
285 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
286 uint64_t Address, const void *Decoder);
287 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
288 uint64_t Address, const void *Decoder);
289 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
290 uint64_t Address, const void *Decoder);
291 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
292 uint64_t Address, const void *Decoder);
293 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
294 uint64_t Address, const void *Decoder);
295 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
296 uint64_t Address, const void *Decoder);
297 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
298 uint64_t Address, const void *Decoder);
299 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
300 uint64_t Address, const void *Decoder);
301 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
302 uint64_t Address, const void *Decoder);
303 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
304 uint64_t Address, const void *Decoder);
305 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
306 uint64_t Address, const void *Decoder);
307 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
308 uint64_t Address, const void *Decoder);
309 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
310 uint64_t Address, const void *Decoder);
311 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
312 uint64_t Address, const void *Decoder);
313 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
314 uint64_t Address, const void *Decoder);
315 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
316 uint64_t Address, const void *Decoder);
317 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
318 uint64_t Address, const void *Decoder);
319 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
320 uint64_t Address, const void *Decoder);
321
322
323 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
324 uint64_t Address, const void *Decoder);
325 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
326 uint64_t Address, const void *Decoder);
327 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
328 uint64_t Address, const void *Decoder);
329 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
330 uint64_t Address, const void *Decoder);
331 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
332 uint64_t Address, const void *Decoder);
333 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
334 uint64_t Address, const void *Decoder);
335 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
336 uint64_t Address, const void *Decoder);
337 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
338 uint64_t Address, const void *Decoder);
339 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
340 uint64_t Address, const void *Decoder);
341 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
342 uint64_t Address, const void *Decoder);
343 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
344 uint64_t Address, const void* Decoder);
345 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
346 uint64_t Address, const void* Decoder);
347 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
348 uint64_t Address, const void* Decoder);
349 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
350 uint64_t Address, const void* Decoder);
351 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
352 uint64_t Address, const void *Decoder);
353 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
354 uint64_t Address, const void *Decoder);
355 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
356 uint64_t Address, const void *Decoder);
357 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
358 uint64_t Address, const void *Decoder);
359 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
360 uint64_t Address, const void *Decoder);
361 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
362 uint64_t Address, const void *Decoder);
363 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
364 uint64_t Address, const void *Decoder);
365 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
366 uint64_t Address, const void *Decoder);
367 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
368 uint64_t Address, const void *Decoder);
369 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
370 uint64_t Address, const void *Decoder);
371 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
372 uint64_t Address, const void *Decoder);
373 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
374 uint64_t Address, const void *Decoder);
375 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
376 uint64_t Address, const void *Decoder);
377 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
378 uint64_t Address, const void *Decoder);
379 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
380 uint64_t Address, const void *Decoder);
381 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
382 uint64_t Address, const void *Decoder);
383 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
384 uint64_t Address, const void *Decoder);
385 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
386 uint64_t Address, const void *Decoder);
387 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
388 uint64_t Address, const void *Decoder);
389 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
390 uint64_t Address, const void *Decoder);
391 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
392 uint64_t Address, const void *Decoder);
393 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
394 uint64_t Address, const void *Decoder);
395
396 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
397 uint64_t Address, const void *Decoder);
398 static DecodeStatus DecoderForMRRC2AndMCRR2(llvm::MCInst &Inst, unsigned Val,
399 uint64_t Address, const void *Decoder);
400 #include "ARMGenDisassemblerTables.inc"
401
createARMDisassembler(const Target & T,const MCSubtargetInfo & STI,MCContext & Ctx)402 static MCDisassembler *createARMDisassembler(const Target &T,
403 const MCSubtargetInfo &STI,
404 MCContext &Ctx) {
405 return new ARMDisassembler(STI, Ctx);
406 }
407
createThumbDisassembler(const Target & T,const MCSubtargetInfo & STI,MCContext & Ctx)408 static MCDisassembler *createThumbDisassembler(const Target &T,
409 const MCSubtargetInfo &STI,
410 MCContext &Ctx) {
411 return new ThumbDisassembler(STI, Ctx);
412 }
413
414 // Post-decoding checks
checkDecodedInstruction(MCInst & MI,uint64_t & Size,uint64_t Address,raw_ostream & OS,raw_ostream & CS,uint32_t Insn,DecodeStatus Result)415 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
416 uint64_t Address, raw_ostream &OS,
417 raw_ostream &CS,
418 uint32_t Insn,
419 DecodeStatus Result)
420 {
421 switch (MI.getOpcode()) {
422 case ARM::HVC: {
423 // HVC is undefined if condition = 0xf otherwise upredictable
424 // if condition != 0xe
425 uint32_t Cond = (Insn >> 28) & 0xF;
426 if (Cond == 0xF)
427 return MCDisassembler::Fail;
428 if (Cond != 0xE)
429 return MCDisassembler::SoftFail;
430 return Result;
431 }
432 default: return Result;
433 }
434 }
435
getInstruction(MCInst & MI,uint64_t & Size,ArrayRef<uint8_t> Bytes,uint64_t Address,raw_ostream & OS,raw_ostream & CS) const436 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
437 ArrayRef<uint8_t> Bytes,
438 uint64_t Address, raw_ostream &OS,
439 raw_ostream &CS) const {
440 CommentStream = &CS;
441
442 assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
443 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
444 "mode!");
445
446 // We want to read exactly 4 bytes of data.
447 if (Bytes.size() < 4) {
448 Size = 0;
449 return MCDisassembler::Fail;
450 }
451
452 // Encoded as a small-endian 32-bit word in the stream.
453 uint32_t Insn =
454 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
455
456 // Calling the auto-generated decoder function.
457 DecodeStatus Result =
458 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
459 if (Result != MCDisassembler::Fail) {
460 Size = 4;
461 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
462 }
463
464 // VFP and NEON instructions, similarly, are shared between ARM
465 // and Thumb modes.
466 Result = decodeInstruction(DecoderTableVFP32, MI, Insn, Address, this, STI);
467 if (Result != MCDisassembler::Fail) {
468 Size = 4;
469 return Result;
470 }
471
472 Result = decodeInstruction(DecoderTableVFPV832, MI, Insn, Address, this, STI);
473 if (Result != MCDisassembler::Fail) {
474 Size = 4;
475 return Result;
476 }
477
478 Result =
479 decodeInstruction(DecoderTableNEONData32, MI, Insn, Address, this, STI);
480 if (Result != MCDisassembler::Fail) {
481 Size = 4;
482 // Add a fake predicate operand, because we share these instruction
483 // definitions with Thumb2 where these instructions are predicable.
484 if (!DecodePredicateOperand(MI, 0xE, Address, this))
485 return MCDisassembler::Fail;
486 return Result;
487 }
488
489 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, Insn, Address,
490 this, STI);
491 if (Result != MCDisassembler::Fail) {
492 Size = 4;
493 // Add a fake predicate operand, because we share these instruction
494 // definitions with Thumb2 where these instructions are predicable.
495 if (!DecodePredicateOperand(MI, 0xE, Address, this))
496 return MCDisassembler::Fail;
497 return Result;
498 }
499
500 Result =
501 decodeInstruction(DecoderTableNEONDup32, MI, Insn, Address, this, STI);
502 if (Result != MCDisassembler::Fail) {
503 Size = 4;
504 // Add a fake predicate operand, because we share these instruction
505 // definitions with Thumb2 where these instructions are predicable.
506 if (!DecodePredicateOperand(MI, 0xE, Address, this))
507 return MCDisassembler::Fail;
508 return Result;
509 }
510
511 Result =
512 decodeInstruction(DecoderTablev8NEON32, MI, Insn, Address, this, STI);
513 if (Result != MCDisassembler::Fail) {
514 Size = 4;
515 return Result;
516 }
517
518 Result =
519 decodeInstruction(DecoderTablev8Crypto32, MI, Insn, Address, this, STI);
520 if (Result != MCDisassembler::Fail) {
521 Size = 4;
522 return Result;
523 }
524
525 Size = 0;
526 return MCDisassembler::Fail;
527 }
528
529 namespace llvm {
530 extern const MCInstrDesc ARMInsts[];
531 }
532
533 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
534 /// immediate Value in the MCInst. The immediate Value has had any PC
535 /// adjustment made by the caller. If the instruction is a branch instruction
536 /// then isBranch is true, else false. If the getOpInfo() function was set as
537 /// part of the setupForSymbolicDisassembly() call then that function is called
538 /// to get any symbolic information at the Address for this instruction. If
539 /// that returns non-zero then the symbolic information it returns is used to
540 /// create an MCExpr and that is added as an operand to the MCInst. If
541 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
542 /// Value is done and if a symbol is found an MCExpr is created with that, else
543 /// an MCExpr with Value is created. This function returns true if it adds an
544 /// operand to the MCInst and false otherwise.
tryAddingSymbolicOperand(uint64_t Address,int32_t Value,bool isBranch,uint64_t InstSize,MCInst & MI,const void * Decoder)545 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
546 bool isBranch, uint64_t InstSize,
547 MCInst &MI, const void *Decoder) {
548 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
549 // FIXME: Does it make sense for value to be negative?
550 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
551 /* Offset */ 0, InstSize);
552 }
553
554 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
555 /// referenced by a load instruction with the base register that is the Pc.
556 /// These can often be values in a literal pool near the Address of the
557 /// instruction. The Address of the instruction and its immediate Value are
558 /// used as a possible literal pool entry. The SymbolLookUp call back will
559 /// return the name of a symbol referenced by the literal pool's entry if
560 /// the referenced address is that of a symbol. Or it will return a pointer to
561 /// a literal 'C' string if the referenced address of the literal pool's entry
562 /// is an address into a section with 'C' string literals.
tryAddingPcLoadReferenceComment(uint64_t Address,int Value,const void * Decoder)563 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
564 const void *Decoder) {
565 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
566 Dis->tryAddingPcLoadReferenceComment(Value, Address);
567 }
568
569 // Thumb1 instructions don't have explicit S bits. Rather, they
570 // implicitly set CPSR. Since it's not represented in the encoding, the
571 // auto-generated decoder won't inject the CPSR operand. We need to fix
572 // that as a post-pass.
AddThumb1SBit(MCInst & MI,bool InITBlock)573 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
574 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
575 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
576 MCInst::iterator I = MI.begin();
577 for (unsigned i = 0; i < NumOps; ++i, ++I) {
578 if (I == MI.end()) break;
579 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
580 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
581 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
582 return;
583 }
584 }
585
586 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
587 }
588
589 // Most Thumb instructions don't have explicit predicates in the
590 // encoding, but rather get their predicates from IT context. We need
591 // to fix up the predicate operands using this context information as a
592 // post-pass.
593 MCDisassembler::DecodeStatus
AddThumbPredicate(MCInst & MI) const594 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
595 MCDisassembler::DecodeStatus S = Success;
596
597 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
598
599 // A few instructions actually have predicates encoded in them. Don't
600 // try to overwrite it if we're seeing one of those.
601 switch (MI.getOpcode()) {
602 case ARM::tBcc:
603 case ARM::t2Bcc:
604 case ARM::tCBZ:
605 case ARM::tCBNZ:
606 case ARM::tCPS:
607 case ARM::t2CPS3p:
608 case ARM::t2CPS2p:
609 case ARM::t2CPS1p:
610 case ARM::tMOVSr:
611 case ARM::tSETEND:
612 // Some instructions (mostly conditional branches) are not
613 // allowed in IT blocks.
614 if (ITBlock.instrInITBlock())
615 S = SoftFail;
616 else
617 return Success;
618 break;
619 case ARM::t2HINT:
620 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
621 S = SoftFail;
622 break;
623 case ARM::tB:
624 case ARM::t2B:
625 case ARM::t2TBB:
626 case ARM::t2TBH:
627 // Some instructions (mostly unconditional branches) can
628 // only appears at the end of, or outside of, an IT.
629 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
630 S = SoftFail;
631 break;
632 default:
633 break;
634 }
635
636 // If we're in an IT block, base the predicate on that. Otherwise,
637 // assume a predicate of AL.
638 unsigned CC;
639 CC = ITBlock.getITCC();
640 if (CC == 0xF)
641 CC = ARMCC::AL;
642 if (ITBlock.instrInITBlock())
643 ITBlock.advanceITState();
644
645 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
646 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
647 MCInst::iterator I = MI.begin();
648 for (unsigned i = 0; i < NumOps; ++i, ++I) {
649 if (I == MI.end()) break;
650 if (OpInfo[i].isPredicate()) {
651 I = MI.insert(I, MCOperand::createImm(CC));
652 ++I;
653 if (CC == ARMCC::AL)
654 MI.insert(I, MCOperand::createReg(0));
655 else
656 MI.insert(I, MCOperand::createReg(ARM::CPSR));
657 return S;
658 }
659 }
660
661 I = MI.insert(I, MCOperand::createImm(CC));
662 ++I;
663 if (CC == ARMCC::AL)
664 MI.insert(I, MCOperand::createReg(0));
665 else
666 MI.insert(I, MCOperand::createReg(ARM::CPSR));
667
668 return S;
669 }
670
671 // Thumb VFP instructions are a special case. Because we share their
672 // encodings between ARM and Thumb modes, and they are predicable in ARM
673 // mode, the auto-generated decoder will give them an (incorrect)
674 // predicate operand. We need to rewrite these operands based on the IT
675 // context as a post-pass.
UpdateThumbVFPPredicate(MCInst & MI) const676 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
677 unsigned CC;
678 CC = ITBlock.getITCC();
679 if (ITBlock.instrInITBlock())
680 ITBlock.advanceITState();
681
682 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
683 MCInst::iterator I = MI.begin();
684 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
685 for (unsigned i = 0; i < NumOps; ++i, ++I) {
686 if (OpInfo[i].isPredicate() ) {
687 I->setImm(CC);
688 ++I;
689 if (CC == ARMCC::AL)
690 I->setReg(0);
691 else
692 I->setReg(ARM::CPSR);
693 return;
694 }
695 }
696 }
697
getInstruction(MCInst & MI,uint64_t & Size,ArrayRef<uint8_t> Bytes,uint64_t Address,raw_ostream & OS,raw_ostream & CS) const698 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
699 ArrayRef<uint8_t> Bytes,
700 uint64_t Address,
701 raw_ostream &OS,
702 raw_ostream &CS) const {
703 CommentStream = &CS;
704
705 assert(STI.getFeatureBits()[ARM::ModeThumb] &&
706 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
707
708 // We want to read exactly 2 bytes of data.
709 if (Bytes.size() < 2) {
710 Size = 0;
711 return MCDisassembler::Fail;
712 }
713
714 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
715 DecodeStatus Result =
716 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
717 if (Result != MCDisassembler::Fail) {
718 Size = 2;
719 Check(Result, AddThumbPredicate(MI));
720 return Result;
721 }
722
723 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
724 STI);
725 if (Result) {
726 Size = 2;
727 bool InITBlock = ITBlock.instrInITBlock();
728 Check(Result, AddThumbPredicate(MI));
729 AddThumb1SBit(MI, InITBlock);
730 return Result;
731 }
732
733 Result =
734 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
735 if (Result != MCDisassembler::Fail) {
736 Size = 2;
737
738 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
739 // the Thumb predicate.
740 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
741 Result = MCDisassembler::SoftFail;
742
743 Check(Result, AddThumbPredicate(MI));
744
745 // If we find an IT instruction, we need to parse its condition
746 // code and mask operands so that we can apply them correctly
747 // to the subsequent instructions.
748 if (MI.getOpcode() == ARM::t2IT) {
749
750 unsigned Firstcond = MI.getOperand(0).getImm();
751 unsigned Mask = MI.getOperand(1).getImm();
752 ITBlock.setITState(Firstcond, Mask);
753 }
754
755 return Result;
756 }
757
758 // We want to read exactly 4 bytes of data.
759 if (Bytes.size() < 4) {
760 Size = 0;
761 return MCDisassembler::Fail;
762 }
763
764 uint32_t Insn32 =
765 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
766 Result =
767 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
768 if (Result != MCDisassembler::Fail) {
769 Size = 4;
770 bool InITBlock = ITBlock.instrInITBlock();
771 Check(Result, AddThumbPredicate(MI));
772 AddThumb1SBit(MI, InITBlock);
773 return Result;
774 }
775
776 Result =
777 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
778 if (Result != MCDisassembler::Fail) {
779 Size = 4;
780 Check(Result, AddThumbPredicate(MI));
781 return Result;
782 }
783
784 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
785 Result =
786 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
787 if (Result != MCDisassembler::Fail) {
788 Size = 4;
789 UpdateThumbVFPPredicate(MI);
790 return Result;
791 }
792 }
793
794 Result =
795 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
796 if (Result != MCDisassembler::Fail) {
797 Size = 4;
798 return Result;
799 }
800
801 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
802 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
803 STI);
804 if (Result != MCDisassembler::Fail) {
805 Size = 4;
806 Check(Result, AddThumbPredicate(MI));
807 return Result;
808 }
809 }
810
811 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
812 uint32_t NEONLdStInsn = Insn32;
813 NEONLdStInsn &= 0xF0FFFFFF;
814 NEONLdStInsn |= 0x04000000;
815 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
816 Address, this, STI);
817 if (Result != MCDisassembler::Fail) {
818 Size = 4;
819 Check(Result, AddThumbPredicate(MI));
820 return Result;
821 }
822 }
823
824 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
825 uint32_t NEONDataInsn = Insn32;
826 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
827 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
828 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
829 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
830 Address, this, STI);
831 if (Result != MCDisassembler::Fail) {
832 Size = 4;
833 Check(Result, AddThumbPredicate(MI));
834 return Result;
835 }
836
837 uint32_t NEONCryptoInsn = Insn32;
838 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
839 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
840 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
841 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
842 Address, this, STI);
843 if (Result != MCDisassembler::Fail) {
844 Size = 4;
845 return Result;
846 }
847
848 uint32_t NEONv8Insn = Insn32;
849 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
850 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
851 this, STI);
852 if (Result != MCDisassembler::Fail) {
853 Size = 4;
854 return Result;
855 }
856 }
857
858 Size = 0;
859 return MCDisassembler::Fail;
860 }
861
862
LLVMInitializeARMDisassembler()863 extern "C" void LLVMInitializeARMDisassembler() {
864 TargetRegistry::RegisterMCDisassembler(TheARMLETarget,
865 createARMDisassembler);
866 TargetRegistry::RegisterMCDisassembler(TheARMBETarget,
867 createARMDisassembler);
868 TargetRegistry::RegisterMCDisassembler(TheThumbLETarget,
869 createThumbDisassembler);
870 TargetRegistry::RegisterMCDisassembler(TheThumbBETarget,
871 createThumbDisassembler);
872 }
873
874 static const uint16_t GPRDecoderTable[] = {
875 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
876 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
877 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
878 ARM::R12, ARM::SP, ARM::LR, ARM::PC
879 };
880
DecodeGPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)881 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
882 uint64_t Address, const void *Decoder) {
883 if (RegNo > 15)
884 return MCDisassembler::Fail;
885
886 unsigned Register = GPRDecoderTable[RegNo];
887 Inst.addOperand(MCOperand::createReg(Register));
888 return MCDisassembler::Success;
889 }
890
891 static DecodeStatus
DecodeGPRnopcRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)892 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
893 uint64_t Address, const void *Decoder) {
894 DecodeStatus S = MCDisassembler::Success;
895
896 if (RegNo == 15)
897 S = MCDisassembler::SoftFail;
898
899 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
900
901 return S;
902 }
903
904 static DecodeStatus
DecodeGPRwithAPSRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)905 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
906 uint64_t Address, const void *Decoder) {
907 DecodeStatus S = MCDisassembler::Success;
908
909 if (RegNo == 15)
910 {
911 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
912 return MCDisassembler::Success;
913 }
914
915 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
916 return S;
917 }
918
DecodetGPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)919 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
920 uint64_t Address, const void *Decoder) {
921 if (RegNo > 7)
922 return MCDisassembler::Fail;
923 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
924 }
925
926 static const uint16_t GPRPairDecoderTable[] = {
927 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
928 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
929 };
930
DecodeGPRPairRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)931 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
932 uint64_t Address, const void *Decoder) {
933 DecodeStatus S = MCDisassembler::Success;
934
935 if (RegNo > 13)
936 return MCDisassembler::Fail;
937
938 if ((RegNo & 1) || RegNo == 0xe)
939 S = MCDisassembler::SoftFail;
940
941 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
942 Inst.addOperand(MCOperand::createReg(RegisterPair));
943 return S;
944 }
945
DecodetcGPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)946 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
947 uint64_t Address, const void *Decoder) {
948 unsigned Register = 0;
949 switch (RegNo) {
950 case 0:
951 Register = ARM::R0;
952 break;
953 case 1:
954 Register = ARM::R1;
955 break;
956 case 2:
957 Register = ARM::R2;
958 break;
959 case 3:
960 Register = ARM::R3;
961 break;
962 case 9:
963 Register = ARM::R9;
964 break;
965 case 12:
966 Register = ARM::R12;
967 break;
968 default:
969 return MCDisassembler::Fail;
970 }
971
972 Inst.addOperand(MCOperand::createReg(Register));
973 return MCDisassembler::Success;
974 }
975
DecoderGPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)976 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
977 uint64_t Address, const void *Decoder) {
978 DecodeStatus S = MCDisassembler::Success;
979
980 const FeatureBitset &featureBits =
981 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
982
983 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
984 S = MCDisassembler::SoftFail;
985
986 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
987 return S;
988 }
989
990 static const uint16_t SPRDecoderTable[] = {
991 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
992 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
993 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
994 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
995 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
996 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
997 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
998 ARM::S28, ARM::S29, ARM::S30, ARM::S31
999 };
1000
DecodeSPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1001 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
1002 uint64_t Address, const void *Decoder) {
1003 if (RegNo > 31)
1004 return MCDisassembler::Fail;
1005
1006 unsigned Register = SPRDecoderTable[RegNo];
1007 Inst.addOperand(MCOperand::createReg(Register));
1008 return MCDisassembler::Success;
1009 }
1010
1011 static const uint16_t DPRDecoderTable[] = {
1012 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1013 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1014 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1015 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1016 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1017 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1018 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1019 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1020 };
1021
DecodeDPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1022 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1023 uint64_t Address, const void *Decoder) {
1024 const FeatureBitset &featureBits =
1025 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1026
1027 bool hasD16 = featureBits[ARM::FeatureD16];
1028
1029 if (RegNo > 31 || (hasD16 && RegNo > 15))
1030 return MCDisassembler::Fail;
1031
1032 unsigned Register = DPRDecoderTable[RegNo];
1033 Inst.addOperand(MCOperand::createReg(Register));
1034 return MCDisassembler::Success;
1035 }
1036
DecodeDPR_8RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1037 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1038 uint64_t Address, const void *Decoder) {
1039 if (RegNo > 7)
1040 return MCDisassembler::Fail;
1041 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1042 }
1043
1044 static DecodeStatus
DecodeDPR_VFP2RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1045 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1046 uint64_t Address, const void *Decoder) {
1047 if (RegNo > 15)
1048 return MCDisassembler::Fail;
1049 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1050 }
1051
1052 static const uint16_t QPRDecoderTable[] = {
1053 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1054 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1055 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1056 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1057 };
1058
1059
DecodeQPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1060 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1061 uint64_t Address, const void *Decoder) {
1062 if (RegNo > 31 || (RegNo & 1) != 0)
1063 return MCDisassembler::Fail;
1064 RegNo >>= 1;
1065
1066 unsigned Register = QPRDecoderTable[RegNo];
1067 Inst.addOperand(MCOperand::createReg(Register));
1068 return MCDisassembler::Success;
1069 }
1070
1071 static const uint16_t DPairDecoderTable[] = {
1072 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1073 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1074 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1075 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1076 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1077 ARM::Q15
1078 };
1079
DecodeDPairRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1080 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1081 uint64_t Address, const void *Decoder) {
1082 if (RegNo > 30)
1083 return MCDisassembler::Fail;
1084
1085 unsigned Register = DPairDecoderTable[RegNo];
1086 Inst.addOperand(MCOperand::createReg(Register));
1087 return MCDisassembler::Success;
1088 }
1089
1090 static const uint16_t DPairSpacedDecoderTable[] = {
1091 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1092 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1093 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1094 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1095 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1096 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1097 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1098 ARM::D28_D30, ARM::D29_D31
1099 };
1100
DecodeDPairSpacedRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1101 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1102 unsigned RegNo,
1103 uint64_t Address,
1104 const void *Decoder) {
1105 if (RegNo > 29)
1106 return MCDisassembler::Fail;
1107
1108 unsigned Register = DPairSpacedDecoderTable[RegNo];
1109 Inst.addOperand(MCOperand::createReg(Register));
1110 return MCDisassembler::Success;
1111 }
1112
DecodePredicateOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1113 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1114 uint64_t Address, const void *Decoder) {
1115 if (Val == 0xF) return MCDisassembler::Fail;
1116 // AL predicate is not allowed on Thumb1 branches.
1117 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1118 return MCDisassembler::Fail;
1119 Inst.addOperand(MCOperand::createImm(Val));
1120 if (Val == ARMCC::AL) {
1121 Inst.addOperand(MCOperand::createReg(0));
1122 } else
1123 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1124 return MCDisassembler::Success;
1125 }
1126
DecodeCCOutOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1127 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1128 uint64_t Address, const void *Decoder) {
1129 if (Val)
1130 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1131 else
1132 Inst.addOperand(MCOperand::createReg(0));
1133 return MCDisassembler::Success;
1134 }
1135
DecodeSORegImmOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1136 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1137 uint64_t Address, const void *Decoder) {
1138 DecodeStatus S = MCDisassembler::Success;
1139
1140 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1141 unsigned type = fieldFromInstruction(Val, 5, 2);
1142 unsigned imm = fieldFromInstruction(Val, 7, 5);
1143
1144 // Register-immediate
1145 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
1146 return MCDisassembler::Fail;
1147
1148 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1149 switch (type) {
1150 case 0:
1151 Shift = ARM_AM::lsl;
1152 break;
1153 case 1:
1154 Shift = ARM_AM::lsr;
1155 break;
1156 case 2:
1157 Shift = ARM_AM::asr;
1158 break;
1159 case 3:
1160 Shift = ARM_AM::ror;
1161 break;
1162 }
1163
1164 if (Shift == ARM_AM::ror && imm == 0)
1165 Shift = ARM_AM::rrx;
1166
1167 unsigned Op = Shift | (imm << 3);
1168 Inst.addOperand(MCOperand::createImm(Op));
1169
1170 return S;
1171 }
1172
DecodeSORegRegOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1173 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1174 uint64_t Address, const void *Decoder) {
1175 DecodeStatus S = MCDisassembler::Success;
1176
1177 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1178 unsigned type = fieldFromInstruction(Val, 5, 2);
1179 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1180
1181 // Register-register
1182 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1183 return MCDisassembler::Fail;
1184 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1185 return MCDisassembler::Fail;
1186
1187 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1188 switch (type) {
1189 case 0:
1190 Shift = ARM_AM::lsl;
1191 break;
1192 case 1:
1193 Shift = ARM_AM::lsr;
1194 break;
1195 case 2:
1196 Shift = ARM_AM::asr;
1197 break;
1198 case 3:
1199 Shift = ARM_AM::ror;
1200 break;
1201 }
1202
1203 Inst.addOperand(MCOperand::createImm(Shift));
1204
1205 return S;
1206 }
1207
DecodeRegListOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1208 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1209 uint64_t Address, const void *Decoder) {
1210 DecodeStatus S = MCDisassembler::Success;
1211
1212 bool NeedDisjointWriteback = false;
1213 unsigned WritebackReg = 0;
1214 switch (Inst.getOpcode()) {
1215 default:
1216 break;
1217 case ARM::LDMIA_UPD:
1218 case ARM::LDMDB_UPD:
1219 case ARM::LDMIB_UPD:
1220 case ARM::LDMDA_UPD:
1221 case ARM::t2LDMIA_UPD:
1222 case ARM::t2LDMDB_UPD:
1223 case ARM::t2STMIA_UPD:
1224 case ARM::t2STMDB_UPD:
1225 NeedDisjointWriteback = true;
1226 WritebackReg = Inst.getOperand(0).getReg();
1227 break;
1228 }
1229
1230 // Empty register lists are not allowed.
1231 if (Val == 0) return MCDisassembler::Fail;
1232 for (unsigned i = 0; i < 16; ++i) {
1233 if (Val & (1 << i)) {
1234 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1235 return MCDisassembler::Fail;
1236 // Writeback not allowed if Rn is in the target list.
1237 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1238 Check(S, MCDisassembler::SoftFail);
1239 }
1240 }
1241
1242 return S;
1243 }
1244
DecodeSPRRegListOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1245 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1246 uint64_t Address, const void *Decoder) {
1247 DecodeStatus S = MCDisassembler::Success;
1248
1249 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1250 unsigned regs = fieldFromInstruction(Val, 0, 8);
1251
1252 // In case of unpredictable encoding, tweak the operands.
1253 if (regs == 0 || (Vd + regs) > 32) {
1254 regs = Vd + regs > 32 ? 32 - Vd : regs;
1255 regs = std::max( 1u, regs);
1256 S = MCDisassembler::SoftFail;
1257 }
1258
1259 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1260 return MCDisassembler::Fail;
1261 for (unsigned i = 0; i < (regs - 1); ++i) {
1262 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1263 return MCDisassembler::Fail;
1264 }
1265
1266 return S;
1267 }
1268
DecodeDPRRegListOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1269 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1270 uint64_t Address, const void *Decoder) {
1271 DecodeStatus S = MCDisassembler::Success;
1272
1273 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1274 unsigned regs = fieldFromInstruction(Val, 1, 7);
1275
1276 // In case of unpredictable encoding, tweak the operands.
1277 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1278 regs = Vd + regs > 32 ? 32 - Vd : regs;
1279 regs = std::max( 1u, regs);
1280 regs = std::min(16u, regs);
1281 S = MCDisassembler::SoftFail;
1282 }
1283
1284 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1285 return MCDisassembler::Fail;
1286 for (unsigned i = 0; i < (regs - 1); ++i) {
1287 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1288 return MCDisassembler::Fail;
1289 }
1290
1291 return S;
1292 }
1293
DecodeBitfieldMaskOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1294 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1295 uint64_t Address, const void *Decoder) {
1296 // This operand encodes a mask of contiguous zeros between a specified MSB
1297 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1298 // the mask of all bits LSB-and-lower, and then xor them to create
1299 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1300 // create the final mask.
1301 unsigned msb = fieldFromInstruction(Val, 5, 5);
1302 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1303
1304 DecodeStatus S = MCDisassembler::Success;
1305 if (lsb > msb) {
1306 Check(S, MCDisassembler::SoftFail);
1307 // The check above will cause the warning for the "potentially undefined
1308 // instruction encoding" but we can't build a bad MCOperand value here
1309 // with a lsb > msb or else printing the MCInst will cause a crash.
1310 lsb = msb;
1311 }
1312
1313 uint32_t msb_mask = 0xFFFFFFFF;
1314 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1315 uint32_t lsb_mask = (1U << lsb) - 1;
1316
1317 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
1318 return S;
1319 }
1320
DecodeCopMemInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1321 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1322 uint64_t Address, const void *Decoder) {
1323 DecodeStatus S = MCDisassembler::Success;
1324
1325 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1326 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1327 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1328 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1329 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1330 unsigned U = fieldFromInstruction(Insn, 23, 1);
1331
1332 switch (Inst.getOpcode()) {
1333 case ARM::LDC_OFFSET:
1334 case ARM::LDC_PRE:
1335 case ARM::LDC_POST:
1336 case ARM::LDC_OPTION:
1337 case ARM::LDCL_OFFSET:
1338 case ARM::LDCL_PRE:
1339 case ARM::LDCL_POST:
1340 case ARM::LDCL_OPTION:
1341 case ARM::STC_OFFSET:
1342 case ARM::STC_PRE:
1343 case ARM::STC_POST:
1344 case ARM::STC_OPTION:
1345 case ARM::STCL_OFFSET:
1346 case ARM::STCL_PRE:
1347 case ARM::STCL_POST:
1348 case ARM::STCL_OPTION:
1349 case ARM::t2LDC_OFFSET:
1350 case ARM::t2LDC_PRE:
1351 case ARM::t2LDC_POST:
1352 case ARM::t2LDC_OPTION:
1353 case ARM::t2LDCL_OFFSET:
1354 case ARM::t2LDCL_PRE:
1355 case ARM::t2LDCL_POST:
1356 case ARM::t2LDCL_OPTION:
1357 case ARM::t2STC_OFFSET:
1358 case ARM::t2STC_PRE:
1359 case ARM::t2STC_POST:
1360 case ARM::t2STC_OPTION:
1361 case ARM::t2STCL_OFFSET:
1362 case ARM::t2STCL_PRE:
1363 case ARM::t2STCL_POST:
1364 case ARM::t2STCL_OPTION:
1365 if (coproc == 0xA || coproc == 0xB)
1366 return MCDisassembler::Fail;
1367 break;
1368 default:
1369 break;
1370 }
1371
1372 const FeatureBitset &featureBits =
1373 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1374 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1375 return MCDisassembler::Fail;
1376
1377 Inst.addOperand(MCOperand::createImm(coproc));
1378 Inst.addOperand(MCOperand::createImm(CRd));
1379 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1380 return MCDisassembler::Fail;
1381
1382 switch (Inst.getOpcode()) {
1383 case ARM::t2LDC2_OFFSET:
1384 case ARM::t2LDC2L_OFFSET:
1385 case ARM::t2LDC2_PRE:
1386 case ARM::t2LDC2L_PRE:
1387 case ARM::t2STC2_OFFSET:
1388 case ARM::t2STC2L_OFFSET:
1389 case ARM::t2STC2_PRE:
1390 case ARM::t2STC2L_PRE:
1391 case ARM::LDC2_OFFSET:
1392 case ARM::LDC2L_OFFSET:
1393 case ARM::LDC2_PRE:
1394 case ARM::LDC2L_PRE:
1395 case ARM::STC2_OFFSET:
1396 case ARM::STC2L_OFFSET:
1397 case ARM::STC2_PRE:
1398 case ARM::STC2L_PRE:
1399 case ARM::t2LDC_OFFSET:
1400 case ARM::t2LDCL_OFFSET:
1401 case ARM::t2LDC_PRE:
1402 case ARM::t2LDCL_PRE:
1403 case ARM::t2STC_OFFSET:
1404 case ARM::t2STCL_OFFSET:
1405 case ARM::t2STC_PRE:
1406 case ARM::t2STCL_PRE:
1407 case ARM::LDC_OFFSET:
1408 case ARM::LDCL_OFFSET:
1409 case ARM::LDC_PRE:
1410 case ARM::LDCL_PRE:
1411 case ARM::STC_OFFSET:
1412 case ARM::STCL_OFFSET:
1413 case ARM::STC_PRE:
1414 case ARM::STCL_PRE:
1415 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1416 Inst.addOperand(MCOperand::createImm(imm));
1417 break;
1418 case ARM::t2LDC2_POST:
1419 case ARM::t2LDC2L_POST:
1420 case ARM::t2STC2_POST:
1421 case ARM::t2STC2L_POST:
1422 case ARM::LDC2_POST:
1423 case ARM::LDC2L_POST:
1424 case ARM::STC2_POST:
1425 case ARM::STC2L_POST:
1426 case ARM::t2LDC_POST:
1427 case ARM::t2LDCL_POST:
1428 case ARM::t2STC_POST:
1429 case ARM::t2STCL_POST:
1430 case ARM::LDC_POST:
1431 case ARM::LDCL_POST:
1432 case ARM::STC_POST:
1433 case ARM::STCL_POST:
1434 imm |= U << 8;
1435 // fall through.
1436 default:
1437 // The 'option' variant doesn't encode 'U' in the immediate since
1438 // the immediate is unsigned [0,255].
1439 Inst.addOperand(MCOperand::createImm(imm));
1440 break;
1441 }
1442
1443 switch (Inst.getOpcode()) {
1444 case ARM::LDC_OFFSET:
1445 case ARM::LDC_PRE:
1446 case ARM::LDC_POST:
1447 case ARM::LDC_OPTION:
1448 case ARM::LDCL_OFFSET:
1449 case ARM::LDCL_PRE:
1450 case ARM::LDCL_POST:
1451 case ARM::LDCL_OPTION:
1452 case ARM::STC_OFFSET:
1453 case ARM::STC_PRE:
1454 case ARM::STC_POST:
1455 case ARM::STC_OPTION:
1456 case ARM::STCL_OFFSET:
1457 case ARM::STCL_PRE:
1458 case ARM::STCL_POST:
1459 case ARM::STCL_OPTION:
1460 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1461 return MCDisassembler::Fail;
1462 break;
1463 default:
1464 break;
1465 }
1466
1467 return S;
1468 }
1469
1470 static DecodeStatus
DecodeAddrMode2IdxInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1471 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1472 uint64_t Address, const void *Decoder) {
1473 DecodeStatus S = MCDisassembler::Success;
1474
1475 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1476 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1477 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1478 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1479 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1480 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1481 unsigned P = fieldFromInstruction(Insn, 24, 1);
1482 unsigned W = fieldFromInstruction(Insn, 21, 1);
1483
1484 // On stores, the writeback operand precedes Rt.
1485 switch (Inst.getOpcode()) {
1486 case ARM::STR_POST_IMM:
1487 case ARM::STR_POST_REG:
1488 case ARM::STRB_POST_IMM:
1489 case ARM::STRB_POST_REG:
1490 case ARM::STRT_POST_REG:
1491 case ARM::STRT_POST_IMM:
1492 case ARM::STRBT_POST_REG:
1493 case ARM::STRBT_POST_IMM:
1494 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1495 return MCDisassembler::Fail;
1496 break;
1497 default:
1498 break;
1499 }
1500
1501 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1502 return MCDisassembler::Fail;
1503
1504 // On loads, the writeback operand comes after Rt.
1505 switch (Inst.getOpcode()) {
1506 case ARM::LDR_POST_IMM:
1507 case ARM::LDR_POST_REG:
1508 case ARM::LDRB_POST_IMM:
1509 case ARM::LDRB_POST_REG:
1510 case ARM::LDRBT_POST_REG:
1511 case ARM::LDRBT_POST_IMM:
1512 case ARM::LDRT_POST_REG:
1513 case ARM::LDRT_POST_IMM:
1514 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1515 return MCDisassembler::Fail;
1516 break;
1517 default:
1518 break;
1519 }
1520
1521 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1522 return MCDisassembler::Fail;
1523
1524 ARM_AM::AddrOpc Op = ARM_AM::add;
1525 if (!fieldFromInstruction(Insn, 23, 1))
1526 Op = ARM_AM::sub;
1527
1528 bool writeback = (P == 0) || (W == 1);
1529 unsigned idx_mode = 0;
1530 if (P && writeback)
1531 idx_mode = ARMII::IndexModePre;
1532 else if (!P && writeback)
1533 idx_mode = ARMII::IndexModePost;
1534
1535 if (writeback && (Rn == 15 || Rn == Rt))
1536 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1537
1538 if (reg) {
1539 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1540 return MCDisassembler::Fail;
1541 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1542 switch( fieldFromInstruction(Insn, 5, 2)) {
1543 case 0:
1544 Opc = ARM_AM::lsl;
1545 break;
1546 case 1:
1547 Opc = ARM_AM::lsr;
1548 break;
1549 case 2:
1550 Opc = ARM_AM::asr;
1551 break;
1552 case 3:
1553 Opc = ARM_AM::ror;
1554 break;
1555 default:
1556 return MCDisassembler::Fail;
1557 }
1558 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1559 if (Opc == ARM_AM::ror && amt == 0)
1560 Opc = ARM_AM::rrx;
1561 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1562
1563 Inst.addOperand(MCOperand::createImm(imm));
1564 } else {
1565 Inst.addOperand(MCOperand::createReg(0));
1566 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1567 Inst.addOperand(MCOperand::createImm(tmp));
1568 }
1569
1570 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1571 return MCDisassembler::Fail;
1572
1573 return S;
1574 }
1575
DecodeSORegMemOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1576 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1577 uint64_t Address, const void *Decoder) {
1578 DecodeStatus S = MCDisassembler::Success;
1579
1580 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1581 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1582 unsigned type = fieldFromInstruction(Val, 5, 2);
1583 unsigned imm = fieldFromInstruction(Val, 7, 5);
1584 unsigned U = fieldFromInstruction(Val, 12, 1);
1585
1586 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1587 switch (type) {
1588 case 0:
1589 ShOp = ARM_AM::lsl;
1590 break;
1591 case 1:
1592 ShOp = ARM_AM::lsr;
1593 break;
1594 case 2:
1595 ShOp = ARM_AM::asr;
1596 break;
1597 case 3:
1598 ShOp = ARM_AM::ror;
1599 break;
1600 }
1601
1602 if (ShOp == ARM_AM::ror && imm == 0)
1603 ShOp = ARM_AM::rrx;
1604
1605 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1606 return MCDisassembler::Fail;
1607 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1608 return MCDisassembler::Fail;
1609 unsigned shift;
1610 if (U)
1611 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1612 else
1613 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1614 Inst.addOperand(MCOperand::createImm(shift));
1615
1616 return S;
1617 }
1618
1619 static DecodeStatus
DecodeAddrMode3Instruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1620 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1621 uint64_t Address, const void *Decoder) {
1622 DecodeStatus S = MCDisassembler::Success;
1623
1624 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1625 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1626 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1627 unsigned type = fieldFromInstruction(Insn, 22, 1);
1628 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1629 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1630 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1631 unsigned W = fieldFromInstruction(Insn, 21, 1);
1632 unsigned P = fieldFromInstruction(Insn, 24, 1);
1633 unsigned Rt2 = Rt + 1;
1634
1635 bool writeback = (W == 1) | (P == 0);
1636
1637 // For {LD,ST}RD, Rt must be even, else undefined.
1638 switch (Inst.getOpcode()) {
1639 case ARM::STRD:
1640 case ARM::STRD_PRE:
1641 case ARM::STRD_POST:
1642 case ARM::LDRD:
1643 case ARM::LDRD_PRE:
1644 case ARM::LDRD_POST:
1645 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1646 break;
1647 default:
1648 break;
1649 }
1650 switch (Inst.getOpcode()) {
1651 case ARM::STRD:
1652 case ARM::STRD_PRE:
1653 case ARM::STRD_POST:
1654 if (P == 0 && W == 1)
1655 S = MCDisassembler::SoftFail;
1656
1657 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1658 S = MCDisassembler::SoftFail;
1659 if (type && Rm == 15)
1660 S = MCDisassembler::SoftFail;
1661 if (Rt2 == 15)
1662 S = MCDisassembler::SoftFail;
1663 if (!type && fieldFromInstruction(Insn, 8, 4))
1664 S = MCDisassembler::SoftFail;
1665 break;
1666 case ARM::STRH:
1667 case ARM::STRH_PRE:
1668 case ARM::STRH_POST:
1669 if (Rt == 15)
1670 S = MCDisassembler::SoftFail;
1671 if (writeback && (Rn == 15 || Rn == Rt))
1672 S = MCDisassembler::SoftFail;
1673 if (!type && Rm == 15)
1674 S = MCDisassembler::SoftFail;
1675 break;
1676 case ARM::LDRD:
1677 case ARM::LDRD_PRE:
1678 case ARM::LDRD_POST:
1679 if (type && Rn == 15){
1680 if (Rt2 == 15)
1681 S = MCDisassembler::SoftFail;
1682 break;
1683 }
1684 if (P == 0 && W == 1)
1685 S = MCDisassembler::SoftFail;
1686 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1687 S = MCDisassembler::SoftFail;
1688 if (!type && writeback && Rn == 15)
1689 S = MCDisassembler::SoftFail;
1690 if (writeback && (Rn == Rt || Rn == Rt2))
1691 S = MCDisassembler::SoftFail;
1692 break;
1693 case ARM::LDRH:
1694 case ARM::LDRH_PRE:
1695 case ARM::LDRH_POST:
1696 if (type && Rn == 15){
1697 if (Rt == 15)
1698 S = MCDisassembler::SoftFail;
1699 break;
1700 }
1701 if (Rt == 15)
1702 S = MCDisassembler::SoftFail;
1703 if (!type && Rm == 15)
1704 S = MCDisassembler::SoftFail;
1705 if (!type && writeback && (Rn == 15 || Rn == Rt))
1706 S = MCDisassembler::SoftFail;
1707 break;
1708 case ARM::LDRSH:
1709 case ARM::LDRSH_PRE:
1710 case ARM::LDRSH_POST:
1711 case ARM::LDRSB:
1712 case ARM::LDRSB_PRE:
1713 case ARM::LDRSB_POST:
1714 if (type && Rn == 15){
1715 if (Rt == 15)
1716 S = MCDisassembler::SoftFail;
1717 break;
1718 }
1719 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1720 S = MCDisassembler::SoftFail;
1721 if (!type && (Rt == 15 || Rm == 15))
1722 S = MCDisassembler::SoftFail;
1723 if (!type && writeback && (Rn == 15 || Rn == Rt))
1724 S = MCDisassembler::SoftFail;
1725 break;
1726 default:
1727 break;
1728 }
1729
1730 if (writeback) { // Writeback
1731 if (P)
1732 U |= ARMII::IndexModePre << 9;
1733 else
1734 U |= ARMII::IndexModePost << 9;
1735
1736 // On stores, the writeback operand precedes Rt.
1737 switch (Inst.getOpcode()) {
1738 case ARM::STRD:
1739 case ARM::STRD_PRE:
1740 case ARM::STRD_POST:
1741 case ARM::STRH:
1742 case ARM::STRH_PRE:
1743 case ARM::STRH_POST:
1744 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1745 return MCDisassembler::Fail;
1746 break;
1747 default:
1748 break;
1749 }
1750 }
1751
1752 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1753 return MCDisassembler::Fail;
1754 switch (Inst.getOpcode()) {
1755 case ARM::STRD:
1756 case ARM::STRD_PRE:
1757 case ARM::STRD_POST:
1758 case ARM::LDRD:
1759 case ARM::LDRD_PRE:
1760 case ARM::LDRD_POST:
1761 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1762 return MCDisassembler::Fail;
1763 break;
1764 default:
1765 break;
1766 }
1767
1768 if (writeback) {
1769 // On loads, the writeback operand comes after Rt.
1770 switch (Inst.getOpcode()) {
1771 case ARM::LDRD:
1772 case ARM::LDRD_PRE:
1773 case ARM::LDRD_POST:
1774 case ARM::LDRH:
1775 case ARM::LDRH_PRE:
1776 case ARM::LDRH_POST:
1777 case ARM::LDRSH:
1778 case ARM::LDRSH_PRE:
1779 case ARM::LDRSH_POST:
1780 case ARM::LDRSB:
1781 case ARM::LDRSB_PRE:
1782 case ARM::LDRSB_POST:
1783 case ARM::LDRHTr:
1784 case ARM::LDRSBTr:
1785 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1786 return MCDisassembler::Fail;
1787 break;
1788 default:
1789 break;
1790 }
1791 }
1792
1793 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1794 return MCDisassembler::Fail;
1795
1796 if (type) {
1797 Inst.addOperand(MCOperand::createReg(0));
1798 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
1799 } else {
1800 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1801 return MCDisassembler::Fail;
1802 Inst.addOperand(MCOperand::createImm(U));
1803 }
1804
1805 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1806 return MCDisassembler::Fail;
1807
1808 return S;
1809 }
1810
DecodeRFEInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1811 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1812 uint64_t Address, const void *Decoder) {
1813 DecodeStatus S = MCDisassembler::Success;
1814
1815 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1816 unsigned mode = fieldFromInstruction(Insn, 23, 2);
1817
1818 switch (mode) {
1819 case 0:
1820 mode = ARM_AM::da;
1821 break;
1822 case 1:
1823 mode = ARM_AM::ia;
1824 break;
1825 case 2:
1826 mode = ARM_AM::db;
1827 break;
1828 case 3:
1829 mode = ARM_AM::ib;
1830 break;
1831 }
1832
1833 Inst.addOperand(MCOperand::createImm(mode));
1834 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1835 return MCDisassembler::Fail;
1836
1837 return S;
1838 }
1839
DecodeQADDInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1840 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
1841 uint64_t Address, const void *Decoder) {
1842 DecodeStatus S = MCDisassembler::Success;
1843
1844 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1845 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1846 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1847 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1848
1849 if (pred == 0xF)
1850 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1851
1852 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1853 return MCDisassembler::Fail;
1854 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1855 return MCDisassembler::Fail;
1856 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1857 return MCDisassembler::Fail;
1858 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1859 return MCDisassembler::Fail;
1860 return S;
1861 }
1862
DecodeMemMultipleWritebackInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1863 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
1864 unsigned Insn,
1865 uint64_t Address, const void *Decoder) {
1866 DecodeStatus S = MCDisassembler::Success;
1867
1868 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1869 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1870 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1871
1872 if (pred == 0xF) {
1873 // Ambiguous with RFE and SRS
1874 switch (Inst.getOpcode()) {
1875 case ARM::LDMDA:
1876 Inst.setOpcode(ARM::RFEDA);
1877 break;
1878 case ARM::LDMDA_UPD:
1879 Inst.setOpcode(ARM::RFEDA_UPD);
1880 break;
1881 case ARM::LDMDB:
1882 Inst.setOpcode(ARM::RFEDB);
1883 break;
1884 case ARM::LDMDB_UPD:
1885 Inst.setOpcode(ARM::RFEDB_UPD);
1886 break;
1887 case ARM::LDMIA:
1888 Inst.setOpcode(ARM::RFEIA);
1889 break;
1890 case ARM::LDMIA_UPD:
1891 Inst.setOpcode(ARM::RFEIA_UPD);
1892 break;
1893 case ARM::LDMIB:
1894 Inst.setOpcode(ARM::RFEIB);
1895 break;
1896 case ARM::LDMIB_UPD:
1897 Inst.setOpcode(ARM::RFEIB_UPD);
1898 break;
1899 case ARM::STMDA:
1900 Inst.setOpcode(ARM::SRSDA);
1901 break;
1902 case ARM::STMDA_UPD:
1903 Inst.setOpcode(ARM::SRSDA_UPD);
1904 break;
1905 case ARM::STMDB:
1906 Inst.setOpcode(ARM::SRSDB);
1907 break;
1908 case ARM::STMDB_UPD:
1909 Inst.setOpcode(ARM::SRSDB_UPD);
1910 break;
1911 case ARM::STMIA:
1912 Inst.setOpcode(ARM::SRSIA);
1913 break;
1914 case ARM::STMIA_UPD:
1915 Inst.setOpcode(ARM::SRSIA_UPD);
1916 break;
1917 case ARM::STMIB:
1918 Inst.setOpcode(ARM::SRSIB);
1919 break;
1920 case ARM::STMIB_UPD:
1921 Inst.setOpcode(ARM::SRSIB_UPD);
1922 break;
1923 default:
1924 return MCDisassembler::Fail;
1925 }
1926
1927 // For stores (which become SRS's, the only operand is the mode.
1928 if (fieldFromInstruction(Insn, 20, 1) == 0) {
1929 // Check SRS encoding constraints
1930 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1931 fieldFromInstruction(Insn, 20, 1) == 0))
1932 return MCDisassembler::Fail;
1933
1934 Inst.addOperand(
1935 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
1936 return S;
1937 }
1938
1939 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1940 }
1941
1942 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1943 return MCDisassembler::Fail;
1944 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1945 return MCDisassembler::Fail; // Tied
1946 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1947 return MCDisassembler::Fail;
1948 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1949 return MCDisassembler::Fail;
1950
1951 return S;
1952 }
1953
1954 // Check for UNPREDICTABLE predicated ESB instruction
DecodeHINTInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1955 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
1956 uint64_t Address, const void *Decoder) {
1957 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1958 unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
1959 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
1960 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
1961
1962 DecodeStatus S = MCDisassembler::Success;
1963
1964 Inst.addOperand(MCOperand::createImm(imm8));
1965
1966 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1967 return MCDisassembler::Fail;
1968
1969 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
1970 // so all predicates should be allowed.
1971 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
1972 S = MCDisassembler::SoftFail;
1973
1974 return S;
1975 }
1976
DecodeCPSInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1977 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1978 uint64_t Address, const void *Decoder) {
1979 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1980 unsigned M = fieldFromInstruction(Insn, 17, 1);
1981 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1982 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1983
1984 DecodeStatus S = MCDisassembler::Success;
1985
1986 // This decoder is called from multiple location that do not check
1987 // the full encoding is valid before they do.
1988 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1989 fieldFromInstruction(Insn, 16, 1) != 0 ||
1990 fieldFromInstruction(Insn, 20, 8) != 0x10)
1991 return MCDisassembler::Fail;
1992
1993 // imod == '01' --> UNPREDICTABLE
1994 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1995 // return failure here. The '01' imod value is unprintable, so there's
1996 // nothing useful we could do even if we returned UNPREDICTABLE.
1997
1998 if (imod == 1) return MCDisassembler::Fail;
1999
2000 if (imod && M) {
2001 Inst.setOpcode(ARM::CPS3p);
2002 Inst.addOperand(MCOperand::createImm(imod));
2003 Inst.addOperand(MCOperand::createImm(iflags));
2004 Inst.addOperand(MCOperand::createImm(mode));
2005 } else if (imod && !M) {
2006 Inst.setOpcode(ARM::CPS2p);
2007 Inst.addOperand(MCOperand::createImm(imod));
2008 Inst.addOperand(MCOperand::createImm(iflags));
2009 if (mode) S = MCDisassembler::SoftFail;
2010 } else if (!imod && M) {
2011 Inst.setOpcode(ARM::CPS1p);
2012 Inst.addOperand(MCOperand::createImm(mode));
2013 if (iflags) S = MCDisassembler::SoftFail;
2014 } else {
2015 // imod == '00' && M == '0' --> UNPREDICTABLE
2016 Inst.setOpcode(ARM::CPS1p);
2017 Inst.addOperand(MCOperand::createImm(mode));
2018 S = MCDisassembler::SoftFail;
2019 }
2020
2021 return S;
2022 }
2023
DecodeT2CPSInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2024 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
2025 uint64_t Address, const void *Decoder) {
2026 unsigned imod = fieldFromInstruction(Insn, 9, 2);
2027 unsigned M = fieldFromInstruction(Insn, 8, 1);
2028 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2029 unsigned mode = fieldFromInstruction(Insn, 0, 5);
2030
2031 DecodeStatus S = MCDisassembler::Success;
2032
2033 // imod == '01' --> UNPREDICTABLE
2034 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2035 // return failure here. The '01' imod value is unprintable, so there's
2036 // nothing useful we could do even if we returned UNPREDICTABLE.
2037
2038 if (imod == 1) return MCDisassembler::Fail;
2039
2040 if (imod && M) {
2041 Inst.setOpcode(ARM::t2CPS3p);
2042 Inst.addOperand(MCOperand::createImm(imod));
2043 Inst.addOperand(MCOperand::createImm(iflags));
2044 Inst.addOperand(MCOperand::createImm(mode));
2045 } else if (imod && !M) {
2046 Inst.setOpcode(ARM::t2CPS2p);
2047 Inst.addOperand(MCOperand::createImm(imod));
2048 Inst.addOperand(MCOperand::createImm(iflags));
2049 if (mode) S = MCDisassembler::SoftFail;
2050 } else if (!imod && M) {
2051 Inst.setOpcode(ARM::t2CPS1p);
2052 Inst.addOperand(MCOperand::createImm(mode));
2053 if (iflags) S = MCDisassembler::SoftFail;
2054 } else {
2055 // imod == '00' && M == '0' --> this is a HINT instruction
2056 int imm = fieldFromInstruction(Insn, 0, 8);
2057 // HINT are defined only for immediate in [0..4]
2058 if(imm > 4) return MCDisassembler::Fail;
2059 Inst.setOpcode(ARM::t2HINT);
2060 Inst.addOperand(MCOperand::createImm(imm));
2061 }
2062
2063 return S;
2064 }
2065
DecodeT2MOVTWInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2066 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2067 uint64_t Address, const void *Decoder) {
2068 DecodeStatus S = MCDisassembler::Success;
2069
2070 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2071 unsigned imm = 0;
2072
2073 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2074 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2075 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2076 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2077
2078 if (Inst.getOpcode() == ARM::t2MOVTi16)
2079 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2080 return MCDisassembler::Fail;
2081 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2082 return MCDisassembler::Fail;
2083
2084 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2085 Inst.addOperand(MCOperand::createImm(imm));
2086
2087 return S;
2088 }
2089
DecodeArmMOVTWInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2090 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2091 uint64_t Address, const void *Decoder) {
2092 DecodeStatus S = MCDisassembler::Success;
2093
2094 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2095 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2096 unsigned imm = 0;
2097
2098 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2099 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2100
2101 if (Inst.getOpcode() == ARM::MOVTi16)
2102 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2103 return MCDisassembler::Fail;
2104
2105 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2106 return MCDisassembler::Fail;
2107
2108 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2109 Inst.addOperand(MCOperand::createImm(imm));
2110
2111 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2112 return MCDisassembler::Fail;
2113
2114 return S;
2115 }
2116
DecodeSMLAInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2117 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2118 uint64_t Address, const void *Decoder) {
2119 DecodeStatus S = MCDisassembler::Success;
2120
2121 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2122 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2123 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2124 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2125 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2126
2127 if (pred == 0xF)
2128 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2129
2130 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2131 return MCDisassembler::Fail;
2132 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2133 return MCDisassembler::Fail;
2134 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2135 return MCDisassembler::Fail;
2136 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2137 return MCDisassembler::Fail;
2138
2139 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2140 return MCDisassembler::Fail;
2141
2142 return S;
2143 }
2144
DecodeTSTInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2145 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
2146 uint64_t Address, const void *Decoder) {
2147 DecodeStatus S = MCDisassembler::Success;
2148
2149 unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2150 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2151 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2152
2153 if (Pred == 0xF)
2154 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
2155
2156 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2157 return MCDisassembler::Fail;
2158 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2159 return MCDisassembler::Fail;
2160 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
2161 return MCDisassembler::Fail;
2162
2163 return S;
2164 }
2165
DecodeSETPANInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2166 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
2167 uint64_t Address, const void *Decoder) {
2168 DecodeStatus S = MCDisassembler::Success;
2169
2170 unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2171
2172 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2173 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2174
2175 if (!FeatureBits[ARM::HasV8_1aOps] ||
2176 !FeatureBits[ARM::HasV8Ops])
2177 return MCDisassembler::Fail;
2178
2179 // Decoder can be called from DecodeTST, which does not check the full
2180 // encoding is valid.
2181 if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2182 fieldFromInstruction(Insn, 4,4) != 0)
2183 return MCDisassembler::Fail;
2184 if (fieldFromInstruction(Insn, 10,10) != 0 ||
2185 fieldFromInstruction(Insn, 0,4) != 0)
2186 S = MCDisassembler::SoftFail;
2187
2188 Inst.setOpcode(ARM::SETPAN);
2189 Inst.addOperand(MCOperand::createImm(Imm));
2190
2191 return S;
2192 }
2193
DecodeAddrModeImm12Operand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)2194 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2195 uint64_t Address, const void *Decoder) {
2196 DecodeStatus S = MCDisassembler::Success;
2197
2198 unsigned add = fieldFromInstruction(Val, 12, 1);
2199 unsigned imm = fieldFromInstruction(Val, 0, 12);
2200 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2201
2202 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2203 return MCDisassembler::Fail;
2204
2205 if (!add) imm *= -1;
2206 if (imm == 0 && !add) imm = INT32_MIN;
2207 Inst.addOperand(MCOperand::createImm(imm));
2208 if (Rn == 15)
2209 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2210
2211 return S;
2212 }
2213
DecodeAddrMode5Operand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)2214 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2215 uint64_t Address, const void *Decoder) {
2216 DecodeStatus S = MCDisassembler::Success;
2217
2218 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2219 // U == 1 to add imm, 0 to subtract it.
2220 unsigned U = fieldFromInstruction(Val, 8, 1);
2221 unsigned imm = fieldFromInstruction(Val, 0, 8);
2222
2223 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2224 return MCDisassembler::Fail;
2225
2226 if (U)
2227 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2228 else
2229 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2230
2231 return S;
2232 }
2233
DecodeAddrMode5FP16Operand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)2234 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
2235 uint64_t Address, const void *Decoder) {
2236 DecodeStatus S = MCDisassembler::Success;
2237
2238 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2239 // U == 1 to add imm, 0 to subtract it.
2240 unsigned U = fieldFromInstruction(Val, 8, 1);
2241 unsigned imm = fieldFromInstruction(Val, 0, 8);
2242
2243 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2244 return MCDisassembler::Fail;
2245
2246 if (U)
2247 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm)));
2248 else
2249 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm)));
2250
2251 return S;
2252 }
2253
DecodeAddrMode7Operand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)2254 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2255 uint64_t Address, const void *Decoder) {
2256 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2257 }
2258
2259 static DecodeStatus
DecodeT2BInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2260 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2261 uint64_t Address, const void *Decoder) {
2262 DecodeStatus Status = MCDisassembler::Success;
2263
2264 // Note the J1 and J2 values are from the encoded instruction. So here
2265 // change them to I1 and I2 values via as documented:
2266 // I1 = NOT(J1 EOR S);
2267 // I2 = NOT(J2 EOR S);
2268 // and build the imm32 with one trailing zero as documented:
2269 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2270 unsigned S = fieldFromInstruction(Insn, 26, 1);
2271 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2272 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2273 unsigned I1 = !(J1 ^ S);
2274 unsigned I2 = !(J2 ^ S);
2275 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2276 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2277 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2278 int imm32 = SignExtend32<25>(tmp << 1);
2279 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2280 true, 4, Inst, Decoder))
2281 Inst.addOperand(MCOperand::createImm(imm32));
2282
2283 return Status;
2284 }
2285
2286 static DecodeStatus
DecodeBranchImmInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2287 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2288 uint64_t Address, const void *Decoder) {
2289 DecodeStatus S = MCDisassembler::Success;
2290
2291 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2292 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2293
2294 if (pred == 0xF) {
2295 Inst.setOpcode(ARM::BLXi);
2296 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2297 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2298 true, 4, Inst, Decoder))
2299 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2300 return S;
2301 }
2302
2303 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2304 true, 4, Inst, Decoder))
2305 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2306 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2307 return MCDisassembler::Fail;
2308
2309 return S;
2310 }
2311
2312
DecodeAddrMode6Operand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)2313 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2314 uint64_t Address, const void *Decoder) {
2315 DecodeStatus S = MCDisassembler::Success;
2316
2317 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2318 unsigned align = fieldFromInstruction(Val, 4, 2);
2319
2320 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2321 return MCDisassembler::Fail;
2322 if (!align)
2323 Inst.addOperand(MCOperand::createImm(0));
2324 else
2325 Inst.addOperand(MCOperand::createImm(4 << align));
2326
2327 return S;
2328 }
2329
DecodeVLDInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2330 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2331 uint64_t Address, const void *Decoder) {
2332 DecodeStatus S = MCDisassembler::Success;
2333
2334 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2335 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2336 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2337 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2338 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2339 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2340
2341 // First output register
2342 switch (Inst.getOpcode()) {
2343 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2344 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2345 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2346 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2347 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2348 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2349 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2350 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2351 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2352 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2353 return MCDisassembler::Fail;
2354 break;
2355 case ARM::VLD2b16:
2356 case ARM::VLD2b32:
2357 case ARM::VLD2b8:
2358 case ARM::VLD2b16wb_fixed:
2359 case ARM::VLD2b16wb_register:
2360 case ARM::VLD2b32wb_fixed:
2361 case ARM::VLD2b32wb_register:
2362 case ARM::VLD2b8wb_fixed:
2363 case ARM::VLD2b8wb_register:
2364 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2365 return MCDisassembler::Fail;
2366 break;
2367 default:
2368 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2369 return MCDisassembler::Fail;
2370 }
2371
2372 // Second output register
2373 switch (Inst.getOpcode()) {
2374 case ARM::VLD3d8:
2375 case ARM::VLD3d16:
2376 case ARM::VLD3d32:
2377 case ARM::VLD3d8_UPD:
2378 case ARM::VLD3d16_UPD:
2379 case ARM::VLD3d32_UPD:
2380 case ARM::VLD4d8:
2381 case ARM::VLD4d16:
2382 case ARM::VLD4d32:
2383 case ARM::VLD4d8_UPD:
2384 case ARM::VLD4d16_UPD:
2385 case ARM::VLD4d32_UPD:
2386 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2387 return MCDisassembler::Fail;
2388 break;
2389 case ARM::VLD3q8:
2390 case ARM::VLD3q16:
2391 case ARM::VLD3q32:
2392 case ARM::VLD3q8_UPD:
2393 case ARM::VLD3q16_UPD:
2394 case ARM::VLD3q32_UPD:
2395 case ARM::VLD4q8:
2396 case ARM::VLD4q16:
2397 case ARM::VLD4q32:
2398 case ARM::VLD4q8_UPD:
2399 case ARM::VLD4q16_UPD:
2400 case ARM::VLD4q32_UPD:
2401 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2402 return MCDisassembler::Fail;
2403 default:
2404 break;
2405 }
2406
2407 // Third output register
2408 switch(Inst.getOpcode()) {
2409 case ARM::VLD3d8:
2410 case ARM::VLD3d16:
2411 case ARM::VLD3d32:
2412 case ARM::VLD3d8_UPD:
2413 case ARM::VLD3d16_UPD:
2414 case ARM::VLD3d32_UPD:
2415 case ARM::VLD4d8:
2416 case ARM::VLD4d16:
2417 case ARM::VLD4d32:
2418 case ARM::VLD4d8_UPD:
2419 case ARM::VLD4d16_UPD:
2420 case ARM::VLD4d32_UPD:
2421 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2422 return MCDisassembler::Fail;
2423 break;
2424 case ARM::VLD3q8:
2425 case ARM::VLD3q16:
2426 case ARM::VLD3q32:
2427 case ARM::VLD3q8_UPD:
2428 case ARM::VLD3q16_UPD:
2429 case ARM::VLD3q32_UPD:
2430 case ARM::VLD4q8:
2431 case ARM::VLD4q16:
2432 case ARM::VLD4q32:
2433 case ARM::VLD4q8_UPD:
2434 case ARM::VLD4q16_UPD:
2435 case ARM::VLD4q32_UPD:
2436 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2437 return MCDisassembler::Fail;
2438 break;
2439 default:
2440 break;
2441 }
2442
2443 // Fourth output register
2444 switch (Inst.getOpcode()) {
2445 case ARM::VLD4d8:
2446 case ARM::VLD4d16:
2447 case ARM::VLD4d32:
2448 case ARM::VLD4d8_UPD:
2449 case ARM::VLD4d16_UPD:
2450 case ARM::VLD4d32_UPD:
2451 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2452 return MCDisassembler::Fail;
2453 break;
2454 case ARM::VLD4q8:
2455 case ARM::VLD4q16:
2456 case ARM::VLD4q32:
2457 case ARM::VLD4q8_UPD:
2458 case ARM::VLD4q16_UPD:
2459 case ARM::VLD4q32_UPD:
2460 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2461 return MCDisassembler::Fail;
2462 break;
2463 default:
2464 break;
2465 }
2466
2467 // Writeback operand
2468 switch (Inst.getOpcode()) {
2469 case ARM::VLD1d8wb_fixed:
2470 case ARM::VLD1d16wb_fixed:
2471 case ARM::VLD1d32wb_fixed:
2472 case ARM::VLD1d64wb_fixed:
2473 case ARM::VLD1d8wb_register:
2474 case ARM::VLD1d16wb_register:
2475 case ARM::VLD1d32wb_register:
2476 case ARM::VLD1d64wb_register:
2477 case ARM::VLD1q8wb_fixed:
2478 case ARM::VLD1q16wb_fixed:
2479 case ARM::VLD1q32wb_fixed:
2480 case ARM::VLD1q64wb_fixed:
2481 case ARM::VLD1q8wb_register:
2482 case ARM::VLD1q16wb_register:
2483 case ARM::VLD1q32wb_register:
2484 case ARM::VLD1q64wb_register:
2485 case ARM::VLD1d8Twb_fixed:
2486 case ARM::VLD1d8Twb_register:
2487 case ARM::VLD1d16Twb_fixed:
2488 case ARM::VLD1d16Twb_register:
2489 case ARM::VLD1d32Twb_fixed:
2490 case ARM::VLD1d32Twb_register:
2491 case ARM::VLD1d64Twb_fixed:
2492 case ARM::VLD1d64Twb_register:
2493 case ARM::VLD1d8Qwb_fixed:
2494 case ARM::VLD1d8Qwb_register:
2495 case ARM::VLD1d16Qwb_fixed:
2496 case ARM::VLD1d16Qwb_register:
2497 case ARM::VLD1d32Qwb_fixed:
2498 case ARM::VLD1d32Qwb_register:
2499 case ARM::VLD1d64Qwb_fixed:
2500 case ARM::VLD1d64Qwb_register:
2501 case ARM::VLD2d8wb_fixed:
2502 case ARM::VLD2d16wb_fixed:
2503 case ARM::VLD2d32wb_fixed:
2504 case ARM::VLD2q8wb_fixed:
2505 case ARM::VLD2q16wb_fixed:
2506 case ARM::VLD2q32wb_fixed:
2507 case ARM::VLD2d8wb_register:
2508 case ARM::VLD2d16wb_register:
2509 case ARM::VLD2d32wb_register:
2510 case ARM::VLD2q8wb_register:
2511 case ARM::VLD2q16wb_register:
2512 case ARM::VLD2q32wb_register:
2513 case ARM::VLD2b8wb_fixed:
2514 case ARM::VLD2b16wb_fixed:
2515 case ARM::VLD2b32wb_fixed:
2516 case ARM::VLD2b8wb_register:
2517 case ARM::VLD2b16wb_register:
2518 case ARM::VLD2b32wb_register:
2519 Inst.addOperand(MCOperand::createImm(0));
2520 break;
2521 case ARM::VLD3d8_UPD:
2522 case ARM::VLD3d16_UPD:
2523 case ARM::VLD3d32_UPD:
2524 case ARM::VLD3q8_UPD:
2525 case ARM::VLD3q16_UPD:
2526 case ARM::VLD3q32_UPD:
2527 case ARM::VLD4d8_UPD:
2528 case ARM::VLD4d16_UPD:
2529 case ARM::VLD4d32_UPD:
2530 case ARM::VLD4q8_UPD:
2531 case ARM::VLD4q16_UPD:
2532 case ARM::VLD4q32_UPD:
2533 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2534 return MCDisassembler::Fail;
2535 break;
2536 default:
2537 break;
2538 }
2539
2540 // AddrMode6 Base (register+alignment)
2541 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2542 return MCDisassembler::Fail;
2543
2544 // AddrMode6 Offset (register)
2545 switch (Inst.getOpcode()) {
2546 default:
2547 // The below have been updated to have explicit am6offset split
2548 // between fixed and register offset. For those instructions not
2549 // yet updated, we need to add an additional reg0 operand for the
2550 // fixed variant.
2551 //
2552 // The fixed offset encodes as Rm == 0xd, so we check for that.
2553 if (Rm == 0xd) {
2554 Inst.addOperand(MCOperand::createReg(0));
2555 break;
2556 }
2557 // Fall through to handle the register offset variant.
2558 case ARM::VLD1d8wb_fixed:
2559 case ARM::VLD1d16wb_fixed:
2560 case ARM::VLD1d32wb_fixed:
2561 case ARM::VLD1d64wb_fixed:
2562 case ARM::VLD1d8Twb_fixed:
2563 case ARM::VLD1d16Twb_fixed:
2564 case ARM::VLD1d32Twb_fixed:
2565 case ARM::VLD1d64Twb_fixed:
2566 case ARM::VLD1d8Qwb_fixed:
2567 case ARM::VLD1d16Qwb_fixed:
2568 case ARM::VLD1d32Qwb_fixed:
2569 case ARM::VLD1d64Qwb_fixed:
2570 case ARM::VLD1d8wb_register:
2571 case ARM::VLD1d16wb_register:
2572 case ARM::VLD1d32wb_register:
2573 case ARM::VLD1d64wb_register:
2574 case ARM::VLD1q8wb_fixed:
2575 case ARM::VLD1q16wb_fixed:
2576 case ARM::VLD1q32wb_fixed:
2577 case ARM::VLD1q64wb_fixed:
2578 case ARM::VLD1q8wb_register:
2579 case ARM::VLD1q16wb_register:
2580 case ARM::VLD1q32wb_register:
2581 case ARM::VLD1q64wb_register:
2582 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2583 // variant encodes Rm == 0xf. Anything else is a register offset post-
2584 // increment and we need to add the register operand to the instruction.
2585 if (Rm != 0xD && Rm != 0xF &&
2586 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2587 return MCDisassembler::Fail;
2588 break;
2589 case ARM::VLD2d8wb_fixed:
2590 case ARM::VLD2d16wb_fixed:
2591 case ARM::VLD2d32wb_fixed:
2592 case ARM::VLD2b8wb_fixed:
2593 case ARM::VLD2b16wb_fixed:
2594 case ARM::VLD2b32wb_fixed:
2595 case ARM::VLD2q8wb_fixed:
2596 case ARM::VLD2q16wb_fixed:
2597 case ARM::VLD2q32wb_fixed:
2598 break;
2599 }
2600
2601 return S;
2602 }
2603
DecodeVLDST1Instruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2604 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2605 uint64_t Address, const void *Decoder) {
2606 unsigned type = fieldFromInstruction(Insn, 8, 4);
2607 unsigned align = fieldFromInstruction(Insn, 4, 2);
2608 if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2609 if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2610 if (type == 10 && align == 3) return MCDisassembler::Fail;
2611
2612 unsigned load = fieldFromInstruction(Insn, 21, 1);
2613 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2614 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2615 }
2616
DecodeVLDST2Instruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2617 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2618 uint64_t Address, const void *Decoder) {
2619 unsigned size = fieldFromInstruction(Insn, 6, 2);
2620 if (size == 3) return MCDisassembler::Fail;
2621
2622 unsigned type = fieldFromInstruction(Insn, 8, 4);
2623 unsigned align = fieldFromInstruction(Insn, 4, 2);
2624 if (type == 8 && align == 3) return MCDisassembler::Fail;
2625 if (type == 9 && align == 3) return MCDisassembler::Fail;
2626
2627 unsigned load = fieldFromInstruction(Insn, 21, 1);
2628 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2629 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2630 }
2631
DecodeVLDST3Instruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2632 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2633 uint64_t Address, const void *Decoder) {
2634 unsigned size = fieldFromInstruction(Insn, 6, 2);
2635 if (size == 3) return MCDisassembler::Fail;
2636
2637 unsigned align = fieldFromInstruction(Insn, 4, 2);
2638 if (align & 2) return MCDisassembler::Fail;
2639
2640 unsigned load = fieldFromInstruction(Insn, 21, 1);
2641 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2642 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2643 }
2644
DecodeVLDST4Instruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2645 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2646 uint64_t Address, const void *Decoder) {
2647 unsigned size = fieldFromInstruction(Insn, 6, 2);
2648 if (size == 3) return MCDisassembler::Fail;
2649
2650 unsigned load = fieldFromInstruction(Insn, 21, 1);
2651 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2652 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2653 }
2654
DecodeVSTInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2655 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2656 uint64_t Address, const void *Decoder) {
2657 DecodeStatus S = MCDisassembler::Success;
2658
2659 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2660 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2661 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2662 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2663 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2664 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2665
2666 // Writeback Operand
2667 switch (Inst.getOpcode()) {
2668 case ARM::VST1d8wb_fixed:
2669 case ARM::VST1d16wb_fixed:
2670 case ARM::VST1d32wb_fixed:
2671 case ARM::VST1d64wb_fixed:
2672 case ARM::VST1d8wb_register:
2673 case ARM::VST1d16wb_register:
2674 case ARM::VST1d32wb_register:
2675 case ARM::VST1d64wb_register:
2676 case ARM::VST1q8wb_fixed:
2677 case ARM::VST1q16wb_fixed:
2678 case ARM::VST1q32wb_fixed:
2679 case ARM::VST1q64wb_fixed:
2680 case ARM::VST1q8wb_register:
2681 case ARM::VST1q16wb_register:
2682 case ARM::VST1q32wb_register:
2683 case ARM::VST1q64wb_register:
2684 case ARM::VST1d8Twb_fixed:
2685 case ARM::VST1d16Twb_fixed:
2686 case ARM::VST1d32Twb_fixed:
2687 case ARM::VST1d64Twb_fixed:
2688 case ARM::VST1d8Twb_register:
2689 case ARM::VST1d16Twb_register:
2690 case ARM::VST1d32Twb_register:
2691 case ARM::VST1d64Twb_register:
2692 case ARM::VST1d8Qwb_fixed:
2693 case ARM::VST1d16Qwb_fixed:
2694 case ARM::VST1d32Qwb_fixed:
2695 case ARM::VST1d64Qwb_fixed:
2696 case ARM::VST1d8Qwb_register:
2697 case ARM::VST1d16Qwb_register:
2698 case ARM::VST1d32Qwb_register:
2699 case ARM::VST1d64Qwb_register:
2700 case ARM::VST2d8wb_fixed:
2701 case ARM::VST2d16wb_fixed:
2702 case ARM::VST2d32wb_fixed:
2703 case ARM::VST2d8wb_register:
2704 case ARM::VST2d16wb_register:
2705 case ARM::VST2d32wb_register:
2706 case ARM::VST2q8wb_fixed:
2707 case ARM::VST2q16wb_fixed:
2708 case ARM::VST2q32wb_fixed:
2709 case ARM::VST2q8wb_register:
2710 case ARM::VST2q16wb_register:
2711 case ARM::VST2q32wb_register:
2712 case ARM::VST2b8wb_fixed:
2713 case ARM::VST2b16wb_fixed:
2714 case ARM::VST2b32wb_fixed:
2715 case ARM::VST2b8wb_register:
2716 case ARM::VST2b16wb_register:
2717 case ARM::VST2b32wb_register:
2718 if (Rm == 0xF)
2719 return MCDisassembler::Fail;
2720 Inst.addOperand(MCOperand::createImm(0));
2721 break;
2722 case ARM::VST3d8_UPD:
2723 case ARM::VST3d16_UPD:
2724 case ARM::VST3d32_UPD:
2725 case ARM::VST3q8_UPD:
2726 case ARM::VST3q16_UPD:
2727 case ARM::VST3q32_UPD:
2728 case ARM::VST4d8_UPD:
2729 case ARM::VST4d16_UPD:
2730 case ARM::VST4d32_UPD:
2731 case ARM::VST4q8_UPD:
2732 case ARM::VST4q16_UPD:
2733 case ARM::VST4q32_UPD:
2734 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2735 return MCDisassembler::Fail;
2736 break;
2737 default:
2738 break;
2739 }
2740
2741 // AddrMode6 Base (register+alignment)
2742 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2743 return MCDisassembler::Fail;
2744
2745 // AddrMode6 Offset (register)
2746 switch (Inst.getOpcode()) {
2747 default:
2748 if (Rm == 0xD)
2749 Inst.addOperand(MCOperand::createReg(0));
2750 else if (Rm != 0xF) {
2751 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2752 return MCDisassembler::Fail;
2753 }
2754 break;
2755 case ARM::VST1d8wb_fixed:
2756 case ARM::VST1d16wb_fixed:
2757 case ARM::VST1d32wb_fixed:
2758 case ARM::VST1d64wb_fixed:
2759 case ARM::VST1q8wb_fixed:
2760 case ARM::VST1q16wb_fixed:
2761 case ARM::VST1q32wb_fixed:
2762 case ARM::VST1q64wb_fixed:
2763 case ARM::VST1d8Twb_fixed:
2764 case ARM::VST1d16Twb_fixed:
2765 case ARM::VST1d32Twb_fixed:
2766 case ARM::VST1d64Twb_fixed:
2767 case ARM::VST1d8Qwb_fixed:
2768 case ARM::VST1d16Qwb_fixed:
2769 case ARM::VST1d32Qwb_fixed:
2770 case ARM::VST1d64Qwb_fixed:
2771 case ARM::VST2d8wb_fixed:
2772 case ARM::VST2d16wb_fixed:
2773 case ARM::VST2d32wb_fixed:
2774 case ARM::VST2q8wb_fixed:
2775 case ARM::VST2q16wb_fixed:
2776 case ARM::VST2q32wb_fixed:
2777 case ARM::VST2b8wb_fixed:
2778 case ARM::VST2b16wb_fixed:
2779 case ARM::VST2b32wb_fixed:
2780 break;
2781 }
2782
2783
2784 // First input register
2785 switch (Inst.getOpcode()) {
2786 case ARM::VST1q16:
2787 case ARM::VST1q32:
2788 case ARM::VST1q64:
2789 case ARM::VST1q8:
2790 case ARM::VST1q16wb_fixed:
2791 case ARM::VST1q16wb_register:
2792 case ARM::VST1q32wb_fixed:
2793 case ARM::VST1q32wb_register:
2794 case ARM::VST1q64wb_fixed:
2795 case ARM::VST1q64wb_register:
2796 case ARM::VST1q8wb_fixed:
2797 case ARM::VST1q8wb_register:
2798 case ARM::VST2d16:
2799 case ARM::VST2d32:
2800 case ARM::VST2d8:
2801 case ARM::VST2d16wb_fixed:
2802 case ARM::VST2d16wb_register:
2803 case ARM::VST2d32wb_fixed:
2804 case ARM::VST2d32wb_register:
2805 case ARM::VST2d8wb_fixed:
2806 case ARM::VST2d8wb_register:
2807 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2808 return MCDisassembler::Fail;
2809 break;
2810 case ARM::VST2b16:
2811 case ARM::VST2b32:
2812 case ARM::VST2b8:
2813 case ARM::VST2b16wb_fixed:
2814 case ARM::VST2b16wb_register:
2815 case ARM::VST2b32wb_fixed:
2816 case ARM::VST2b32wb_register:
2817 case ARM::VST2b8wb_fixed:
2818 case ARM::VST2b8wb_register:
2819 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2820 return MCDisassembler::Fail;
2821 break;
2822 default:
2823 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2824 return MCDisassembler::Fail;
2825 }
2826
2827 // Second input register
2828 switch (Inst.getOpcode()) {
2829 case ARM::VST3d8:
2830 case ARM::VST3d16:
2831 case ARM::VST3d32:
2832 case ARM::VST3d8_UPD:
2833 case ARM::VST3d16_UPD:
2834 case ARM::VST3d32_UPD:
2835 case ARM::VST4d8:
2836 case ARM::VST4d16:
2837 case ARM::VST4d32:
2838 case ARM::VST4d8_UPD:
2839 case ARM::VST4d16_UPD:
2840 case ARM::VST4d32_UPD:
2841 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2842 return MCDisassembler::Fail;
2843 break;
2844 case ARM::VST3q8:
2845 case ARM::VST3q16:
2846 case ARM::VST3q32:
2847 case ARM::VST3q8_UPD:
2848 case ARM::VST3q16_UPD:
2849 case ARM::VST3q32_UPD:
2850 case ARM::VST4q8:
2851 case ARM::VST4q16:
2852 case ARM::VST4q32:
2853 case ARM::VST4q8_UPD:
2854 case ARM::VST4q16_UPD:
2855 case ARM::VST4q32_UPD:
2856 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2857 return MCDisassembler::Fail;
2858 break;
2859 default:
2860 break;
2861 }
2862
2863 // Third input register
2864 switch (Inst.getOpcode()) {
2865 case ARM::VST3d8:
2866 case ARM::VST3d16:
2867 case ARM::VST3d32:
2868 case ARM::VST3d8_UPD:
2869 case ARM::VST3d16_UPD:
2870 case ARM::VST3d32_UPD:
2871 case ARM::VST4d8:
2872 case ARM::VST4d16:
2873 case ARM::VST4d32:
2874 case ARM::VST4d8_UPD:
2875 case ARM::VST4d16_UPD:
2876 case ARM::VST4d32_UPD:
2877 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2878 return MCDisassembler::Fail;
2879 break;
2880 case ARM::VST3q8:
2881 case ARM::VST3q16:
2882 case ARM::VST3q32:
2883 case ARM::VST3q8_UPD:
2884 case ARM::VST3q16_UPD:
2885 case ARM::VST3q32_UPD:
2886 case ARM::VST4q8:
2887 case ARM::VST4q16:
2888 case ARM::VST4q32:
2889 case ARM::VST4q8_UPD:
2890 case ARM::VST4q16_UPD:
2891 case ARM::VST4q32_UPD:
2892 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2893 return MCDisassembler::Fail;
2894 break;
2895 default:
2896 break;
2897 }
2898
2899 // Fourth input register
2900 switch (Inst.getOpcode()) {
2901 case ARM::VST4d8:
2902 case ARM::VST4d16:
2903 case ARM::VST4d32:
2904 case ARM::VST4d8_UPD:
2905 case ARM::VST4d16_UPD:
2906 case ARM::VST4d32_UPD:
2907 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2908 return MCDisassembler::Fail;
2909 break;
2910 case ARM::VST4q8:
2911 case ARM::VST4q16:
2912 case ARM::VST4q32:
2913 case ARM::VST4q8_UPD:
2914 case ARM::VST4q16_UPD:
2915 case ARM::VST4q32_UPD:
2916 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2917 return MCDisassembler::Fail;
2918 break;
2919 default:
2920 break;
2921 }
2922
2923 return S;
2924 }
2925
DecodeVLD1DupInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2926 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2927 uint64_t Address, const void *Decoder) {
2928 DecodeStatus S = MCDisassembler::Success;
2929
2930 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2931 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2932 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2933 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2934 unsigned align = fieldFromInstruction(Insn, 4, 1);
2935 unsigned size = fieldFromInstruction(Insn, 6, 2);
2936
2937 if (size == 0 && align == 1)
2938 return MCDisassembler::Fail;
2939 align *= (1 << size);
2940
2941 switch (Inst.getOpcode()) {
2942 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2943 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2944 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2945 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2946 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2947 return MCDisassembler::Fail;
2948 break;
2949 default:
2950 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2951 return MCDisassembler::Fail;
2952 break;
2953 }
2954 if (Rm != 0xF) {
2955 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2956 return MCDisassembler::Fail;
2957 }
2958
2959 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2960 return MCDisassembler::Fail;
2961 Inst.addOperand(MCOperand::createImm(align));
2962
2963 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2964 // variant encodes Rm == 0xf. Anything else is a register offset post-
2965 // increment and we need to add the register operand to the instruction.
2966 if (Rm != 0xD && Rm != 0xF &&
2967 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2968 return MCDisassembler::Fail;
2969
2970 return S;
2971 }
2972
DecodeVLD2DupInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2973 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2974 uint64_t Address, const void *Decoder) {
2975 DecodeStatus S = MCDisassembler::Success;
2976
2977 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2978 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2979 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2980 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2981 unsigned align = fieldFromInstruction(Insn, 4, 1);
2982 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2983 align *= 2*size;
2984
2985 switch (Inst.getOpcode()) {
2986 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2987 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2988 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2989 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2990 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2991 return MCDisassembler::Fail;
2992 break;
2993 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2994 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2995 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2996 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2997 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2998 return MCDisassembler::Fail;
2999 break;
3000 default:
3001 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3002 return MCDisassembler::Fail;
3003 break;
3004 }
3005
3006 if (Rm != 0xF)
3007 Inst.addOperand(MCOperand::createImm(0));
3008
3009 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3010 return MCDisassembler::Fail;
3011 Inst.addOperand(MCOperand::createImm(align));
3012
3013 if (Rm != 0xD && Rm != 0xF) {
3014 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3015 return MCDisassembler::Fail;
3016 }
3017
3018 return S;
3019 }
3020
DecodeVLD3DupInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3021 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
3022 uint64_t Address, const void *Decoder) {
3023 DecodeStatus S = MCDisassembler::Success;
3024
3025 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3026 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3027 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3028 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3029 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3030
3031 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3032 return MCDisassembler::Fail;
3033 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3034 return MCDisassembler::Fail;
3035 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3036 return MCDisassembler::Fail;
3037 if (Rm != 0xF) {
3038 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3039 return MCDisassembler::Fail;
3040 }
3041
3042 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3043 return MCDisassembler::Fail;
3044 Inst.addOperand(MCOperand::createImm(0));
3045
3046 if (Rm == 0xD)
3047 Inst.addOperand(MCOperand::createReg(0));
3048 else if (Rm != 0xF) {
3049 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3050 return MCDisassembler::Fail;
3051 }
3052
3053 return S;
3054 }
3055
DecodeVLD4DupInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3056 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
3057 uint64_t Address, const void *Decoder) {
3058 DecodeStatus S = MCDisassembler::Success;
3059
3060 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3061 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3062 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3063 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3064 unsigned size = fieldFromInstruction(Insn, 6, 2);
3065 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3066 unsigned align = fieldFromInstruction(Insn, 4, 1);
3067
3068 if (size == 0x3) {
3069 if (align == 0)
3070 return MCDisassembler::Fail;
3071 align = 16;
3072 } else {
3073 if (size == 2) {
3074 align *= 8;
3075 } else {
3076 size = 1 << size;
3077 align *= 4*size;
3078 }
3079 }
3080
3081 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3082 return MCDisassembler::Fail;
3083 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3084 return MCDisassembler::Fail;
3085 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3086 return MCDisassembler::Fail;
3087 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
3088 return MCDisassembler::Fail;
3089 if (Rm != 0xF) {
3090 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3091 return MCDisassembler::Fail;
3092 }
3093
3094 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3095 return MCDisassembler::Fail;
3096 Inst.addOperand(MCOperand::createImm(align));
3097
3098 if (Rm == 0xD)
3099 Inst.addOperand(MCOperand::createReg(0));
3100 else if (Rm != 0xF) {
3101 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3102 return MCDisassembler::Fail;
3103 }
3104
3105 return S;
3106 }
3107
3108 static DecodeStatus
DecodeNEONModImmInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3109 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
3110 uint64_t Address, const void *Decoder) {
3111 DecodeStatus S = MCDisassembler::Success;
3112
3113 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3114 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3115 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3116 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3117 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3118 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3119 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3120 unsigned Q = fieldFromInstruction(Insn, 6, 1);
3121
3122 if (Q) {
3123 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3124 return MCDisassembler::Fail;
3125 } else {
3126 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3127 return MCDisassembler::Fail;
3128 }
3129
3130 Inst.addOperand(MCOperand::createImm(imm));
3131
3132 switch (Inst.getOpcode()) {
3133 case ARM::VORRiv4i16:
3134 case ARM::VORRiv2i32:
3135 case ARM::VBICiv4i16:
3136 case ARM::VBICiv2i32:
3137 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3138 return MCDisassembler::Fail;
3139 break;
3140 case ARM::VORRiv8i16:
3141 case ARM::VORRiv4i32:
3142 case ARM::VBICiv8i16:
3143 case ARM::VBICiv4i32:
3144 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3145 return MCDisassembler::Fail;
3146 break;
3147 default:
3148 break;
3149 }
3150
3151 return S;
3152 }
3153
DecodeVSHLMaxInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3154 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3155 uint64_t Address, const void *Decoder) {
3156 DecodeStatus S = MCDisassembler::Success;
3157
3158 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3159 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3160 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3161 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3162 unsigned size = fieldFromInstruction(Insn, 18, 2);
3163
3164 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3165 return MCDisassembler::Fail;
3166 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3167 return MCDisassembler::Fail;
3168 Inst.addOperand(MCOperand::createImm(8 << size));
3169
3170 return S;
3171 }
3172
DecodeShiftRight8Imm(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3173 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3174 uint64_t Address, const void *Decoder) {
3175 Inst.addOperand(MCOperand::createImm(8 - Val));
3176 return MCDisassembler::Success;
3177 }
3178
DecodeShiftRight16Imm(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3179 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3180 uint64_t Address, const void *Decoder) {
3181 Inst.addOperand(MCOperand::createImm(16 - Val));
3182 return MCDisassembler::Success;
3183 }
3184
DecodeShiftRight32Imm(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3185 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3186 uint64_t Address, const void *Decoder) {
3187 Inst.addOperand(MCOperand::createImm(32 - Val));
3188 return MCDisassembler::Success;
3189 }
3190
DecodeShiftRight64Imm(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3191 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3192 uint64_t Address, const void *Decoder) {
3193 Inst.addOperand(MCOperand::createImm(64 - Val));
3194 return MCDisassembler::Success;
3195 }
3196
DecodeTBLInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3197 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3198 uint64_t Address, const void *Decoder) {
3199 DecodeStatus S = MCDisassembler::Success;
3200
3201 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3202 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3203 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3204 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3205 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3206 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3207 unsigned op = fieldFromInstruction(Insn, 6, 1);
3208
3209 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3210 return MCDisassembler::Fail;
3211 if (op) {
3212 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3213 return MCDisassembler::Fail; // Writeback
3214 }
3215
3216 switch (Inst.getOpcode()) {
3217 case ARM::VTBL2:
3218 case ARM::VTBX2:
3219 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3220 return MCDisassembler::Fail;
3221 break;
3222 default:
3223 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3224 return MCDisassembler::Fail;
3225 }
3226
3227 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3228 return MCDisassembler::Fail;
3229
3230 return S;
3231 }
3232
DecodeThumbAddSpecialReg(MCInst & Inst,uint16_t Insn,uint64_t Address,const void * Decoder)3233 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3234 uint64_t Address, const void *Decoder) {
3235 DecodeStatus S = MCDisassembler::Success;
3236
3237 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3238 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3239
3240 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3241 return MCDisassembler::Fail;
3242
3243 switch(Inst.getOpcode()) {
3244 default:
3245 return MCDisassembler::Fail;
3246 case ARM::tADR:
3247 break; // tADR does not explicitly represent the PC as an operand.
3248 case ARM::tADDrSPi:
3249 Inst.addOperand(MCOperand::createReg(ARM::SP));
3250 break;
3251 }
3252
3253 Inst.addOperand(MCOperand::createImm(imm));
3254 return S;
3255 }
3256
DecodeThumbBROperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3257 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3258 uint64_t Address, const void *Decoder) {
3259 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3260 true, 2, Inst, Decoder))
3261 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
3262 return MCDisassembler::Success;
3263 }
3264
DecodeT2BROperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3265 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3266 uint64_t Address, const void *Decoder) {
3267 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3268 true, 4, Inst, Decoder))
3269 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
3270 return MCDisassembler::Success;
3271 }
3272
DecodeThumbCmpBROperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3273 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3274 uint64_t Address, const void *Decoder) {
3275 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3276 true, 2, Inst, Decoder))
3277 Inst.addOperand(MCOperand::createImm(Val << 1));
3278 return MCDisassembler::Success;
3279 }
3280
DecodeThumbAddrModeRR(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3281 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3282 uint64_t Address, const void *Decoder) {
3283 DecodeStatus S = MCDisassembler::Success;
3284
3285 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3286 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3287
3288 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3289 return MCDisassembler::Fail;
3290 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3291 return MCDisassembler::Fail;
3292
3293 return S;
3294 }
3295
DecodeThumbAddrModeIS(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3296 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3297 uint64_t Address, const void *Decoder) {
3298 DecodeStatus S = MCDisassembler::Success;
3299
3300 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3301 unsigned imm = fieldFromInstruction(Val, 3, 5);
3302
3303 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3304 return MCDisassembler::Fail;
3305 Inst.addOperand(MCOperand::createImm(imm));
3306
3307 return S;
3308 }
3309
DecodeThumbAddrModePC(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3310 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3311 uint64_t Address, const void *Decoder) {
3312 unsigned imm = Val << 2;
3313
3314 Inst.addOperand(MCOperand::createImm(imm));
3315 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3316
3317 return MCDisassembler::Success;
3318 }
3319
DecodeThumbAddrModeSP(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3320 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3321 uint64_t Address, const void *Decoder) {
3322 Inst.addOperand(MCOperand::createReg(ARM::SP));
3323 Inst.addOperand(MCOperand::createImm(Val));
3324
3325 return MCDisassembler::Success;
3326 }
3327
DecodeT2AddrModeSOReg(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3328 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3329 uint64_t Address, const void *Decoder) {
3330 DecodeStatus S = MCDisassembler::Success;
3331
3332 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3333 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3334 unsigned imm = fieldFromInstruction(Val, 0, 2);
3335
3336 // Thumb stores cannot use PC as dest register.
3337 switch (Inst.getOpcode()) {
3338 case ARM::t2STRHs:
3339 case ARM::t2STRBs:
3340 case ARM::t2STRs:
3341 if (Rn == 15)
3342 return MCDisassembler::Fail;
3343 default:
3344 break;
3345 }
3346
3347 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3348 return MCDisassembler::Fail;
3349 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3350 return MCDisassembler::Fail;
3351 Inst.addOperand(MCOperand::createImm(imm));
3352
3353 return S;
3354 }
3355
DecodeT2LoadShift(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3356 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3357 uint64_t Address, const void *Decoder) {
3358 DecodeStatus S = MCDisassembler::Success;
3359
3360 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3361 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3362
3363 const FeatureBitset &featureBits =
3364 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3365
3366 bool hasMP = featureBits[ARM::FeatureMP];
3367 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3368
3369 if (Rn == 15) {
3370 switch (Inst.getOpcode()) {
3371 case ARM::t2LDRBs:
3372 Inst.setOpcode(ARM::t2LDRBpci);
3373 break;
3374 case ARM::t2LDRHs:
3375 Inst.setOpcode(ARM::t2LDRHpci);
3376 break;
3377 case ARM::t2LDRSHs:
3378 Inst.setOpcode(ARM::t2LDRSHpci);
3379 break;
3380 case ARM::t2LDRSBs:
3381 Inst.setOpcode(ARM::t2LDRSBpci);
3382 break;
3383 case ARM::t2LDRs:
3384 Inst.setOpcode(ARM::t2LDRpci);
3385 break;
3386 case ARM::t2PLDs:
3387 Inst.setOpcode(ARM::t2PLDpci);
3388 break;
3389 case ARM::t2PLIs:
3390 Inst.setOpcode(ARM::t2PLIpci);
3391 break;
3392 default:
3393 return MCDisassembler::Fail;
3394 }
3395
3396 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3397 }
3398
3399 if (Rt == 15) {
3400 switch (Inst.getOpcode()) {
3401 case ARM::t2LDRSHs:
3402 return MCDisassembler::Fail;
3403 case ARM::t2LDRHs:
3404 Inst.setOpcode(ARM::t2PLDWs);
3405 break;
3406 case ARM::t2LDRSBs:
3407 Inst.setOpcode(ARM::t2PLIs);
3408 default:
3409 break;
3410 }
3411 }
3412
3413 switch (Inst.getOpcode()) {
3414 case ARM::t2PLDs:
3415 break;
3416 case ARM::t2PLIs:
3417 if (!hasV7Ops)
3418 return MCDisassembler::Fail;
3419 break;
3420 case ARM::t2PLDWs:
3421 if (!hasV7Ops || !hasMP)
3422 return MCDisassembler::Fail;
3423 break;
3424 default:
3425 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3426 return MCDisassembler::Fail;
3427 }
3428
3429 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3430 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3431 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3432 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3433 return MCDisassembler::Fail;
3434
3435 return S;
3436 }
3437
DecodeT2LoadImm8(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3438 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3439 uint64_t Address, const void* Decoder) {
3440 DecodeStatus S = MCDisassembler::Success;
3441
3442 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3443 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3444 unsigned U = fieldFromInstruction(Insn, 9, 1);
3445 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3446 imm |= (U << 8);
3447 imm |= (Rn << 9);
3448 unsigned add = fieldFromInstruction(Insn, 9, 1);
3449
3450 const FeatureBitset &featureBits =
3451 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3452
3453 bool hasMP = featureBits[ARM::FeatureMP];
3454 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3455
3456 if (Rn == 15) {
3457 switch (Inst.getOpcode()) {
3458 case ARM::t2LDRi8:
3459 Inst.setOpcode(ARM::t2LDRpci);
3460 break;
3461 case ARM::t2LDRBi8:
3462 Inst.setOpcode(ARM::t2LDRBpci);
3463 break;
3464 case ARM::t2LDRSBi8:
3465 Inst.setOpcode(ARM::t2LDRSBpci);
3466 break;
3467 case ARM::t2LDRHi8:
3468 Inst.setOpcode(ARM::t2LDRHpci);
3469 break;
3470 case ARM::t2LDRSHi8:
3471 Inst.setOpcode(ARM::t2LDRSHpci);
3472 break;
3473 case ARM::t2PLDi8:
3474 Inst.setOpcode(ARM::t2PLDpci);
3475 break;
3476 case ARM::t2PLIi8:
3477 Inst.setOpcode(ARM::t2PLIpci);
3478 break;
3479 default:
3480 return MCDisassembler::Fail;
3481 }
3482 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3483 }
3484
3485 if (Rt == 15) {
3486 switch (Inst.getOpcode()) {
3487 case ARM::t2LDRSHi8:
3488 return MCDisassembler::Fail;
3489 case ARM::t2LDRHi8:
3490 if (!add)
3491 Inst.setOpcode(ARM::t2PLDWi8);
3492 break;
3493 case ARM::t2LDRSBi8:
3494 Inst.setOpcode(ARM::t2PLIi8);
3495 break;
3496 default:
3497 break;
3498 }
3499 }
3500
3501 switch (Inst.getOpcode()) {
3502 case ARM::t2PLDi8:
3503 break;
3504 case ARM::t2PLIi8:
3505 if (!hasV7Ops)
3506 return MCDisassembler::Fail;
3507 break;
3508 case ARM::t2PLDWi8:
3509 if (!hasV7Ops || !hasMP)
3510 return MCDisassembler::Fail;
3511 break;
3512 default:
3513 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3514 return MCDisassembler::Fail;
3515 }
3516
3517 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3518 return MCDisassembler::Fail;
3519 return S;
3520 }
3521
DecodeT2LoadImm12(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3522 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3523 uint64_t Address, const void* Decoder) {
3524 DecodeStatus S = MCDisassembler::Success;
3525
3526 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3527 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3528 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3529 imm |= (Rn << 13);
3530
3531 const FeatureBitset &featureBits =
3532 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3533
3534 bool hasMP = featureBits[ARM::FeatureMP];
3535 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3536
3537 if (Rn == 15) {
3538 switch (Inst.getOpcode()) {
3539 case ARM::t2LDRi12:
3540 Inst.setOpcode(ARM::t2LDRpci);
3541 break;
3542 case ARM::t2LDRHi12:
3543 Inst.setOpcode(ARM::t2LDRHpci);
3544 break;
3545 case ARM::t2LDRSHi12:
3546 Inst.setOpcode(ARM::t2LDRSHpci);
3547 break;
3548 case ARM::t2LDRBi12:
3549 Inst.setOpcode(ARM::t2LDRBpci);
3550 break;
3551 case ARM::t2LDRSBi12:
3552 Inst.setOpcode(ARM::t2LDRSBpci);
3553 break;
3554 case ARM::t2PLDi12:
3555 Inst.setOpcode(ARM::t2PLDpci);
3556 break;
3557 case ARM::t2PLIi12:
3558 Inst.setOpcode(ARM::t2PLIpci);
3559 break;
3560 default:
3561 return MCDisassembler::Fail;
3562 }
3563 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3564 }
3565
3566 if (Rt == 15) {
3567 switch (Inst.getOpcode()) {
3568 case ARM::t2LDRSHi12:
3569 return MCDisassembler::Fail;
3570 case ARM::t2LDRHi12:
3571 Inst.setOpcode(ARM::t2PLDWi12);
3572 break;
3573 case ARM::t2LDRSBi12:
3574 Inst.setOpcode(ARM::t2PLIi12);
3575 break;
3576 default:
3577 break;
3578 }
3579 }
3580
3581 switch (Inst.getOpcode()) {
3582 case ARM::t2PLDi12:
3583 break;
3584 case ARM::t2PLIi12:
3585 if (!hasV7Ops)
3586 return MCDisassembler::Fail;
3587 break;
3588 case ARM::t2PLDWi12:
3589 if (!hasV7Ops || !hasMP)
3590 return MCDisassembler::Fail;
3591 break;
3592 default:
3593 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3594 return MCDisassembler::Fail;
3595 }
3596
3597 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3598 return MCDisassembler::Fail;
3599 return S;
3600 }
3601
DecodeT2LoadT(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3602 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
3603 uint64_t Address, const void* Decoder) {
3604 DecodeStatus S = MCDisassembler::Success;
3605
3606 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3607 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3608 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3609 imm |= (Rn << 9);
3610
3611 if (Rn == 15) {
3612 switch (Inst.getOpcode()) {
3613 case ARM::t2LDRT:
3614 Inst.setOpcode(ARM::t2LDRpci);
3615 break;
3616 case ARM::t2LDRBT:
3617 Inst.setOpcode(ARM::t2LDRBpci);
3618 break;
3619 case ARM::t2LDRHT:
3620 Inst.setOpcode(ARM::t2LDRHpci);
3621 break;
3622 case ARM::t2LDRSBT:
3623 Inst.setOpcode(ARM::t2LDRSBpci);
3624 break;
3625 case ARM::t2LDRSHT:
3626 Inst.setOpcode(ARM::t2LDRSHpci);
3627 break;
3628 default:
3629 return MCDisassembler::Fail;
3630 }
3631 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3632 }
3633
3634 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3635 return MCDisassembler::Fail;
3636 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3637 return MCDisassembler::Fail;
3638 return S;
3639 }
3640
DecodeT2LoadLabel(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3641 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
3642 uint64_t Address, const void* Decoder) {
3643 DecodeStatus S = MCDisassembler::Success;
3644
3645 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3646 unsigned U = fieldFromInstruction(Insn, 23, 1);
3647 int imm = fieldFromInstruction(Insn, 0, 12);
3648
3649 const FeatureBitset &featureBits =
3650 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3651
3652 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3653
3654 if (Rt == 15) {
3655 switch (Inst.getOpcode()) {
3656 case ARM::t2LDRBpci:
3657 case ARM::t2LDRHpci:
3658 Inst.setOpcode(ARM::t2PLDpci);
3659 break;
3660 case ARM::t2LDRSBpci:
3661 Inst.setOpcode(ARM::t2PLIpci);
3662 break;
3663 case ARM::t2LDRSHpci:
3664 return MCDisassembler::Fail;
3665 default:
3666 break;
3667 }
3668 }
3669
3670 switch(Inst.getOpcode()) {
3671 case ARM::t2PLDpci:
3672 break;
3673 case ARM::t2PLIpci:
3674 if (!hasV7Ops)
3675 return MCDisassembler::Fail;
3676 break;
3677 default:
3678 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3679 return MCDisassembler::Fail;
3680 }
3681
3682 if (!U) {
3683 // Special case for #-0.
3684 if (imm == 0)
3685 imm = INT32_MIN;
3686 else
3687 imm = -imm;
3688 }
3689 Inst.addOperand(MCOperand::createImm(imm));
3690
3691 return S;
3692 }
3693
DecodeT2Imm8S4(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3694 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3695 uint64_t Address, const void *Decoder) {
3696 if (Val == 0)
3697 Inst.addOperand(MCOperand::createImm(INT32_MIN));
3698 else {
3699 int imm = Val & 0xFF;
3700
3701 if (!(Val & 0x100)) imm *= -1;
3702 Inst.addOperand(MCOperand::createImm(imm * 4));
3703 }
3704
3705 return MCDisassembler::Success;
3706 }
3707
DecodeT2AddrModeImm8s4(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3708 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3709 uint64_t Address, const void *Decoder) {
3710 DecodeStatus S = MCDisassembler::Success;
3711
3712 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3713 unsigned imm = fieldFromInstruction(Val, 0, 9);
3714
3715 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3716 return MCDisassembler::Fail;
3717 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3718 return MCDisassembler::Fail;
3719
3720 return S;
3721 }
3722
DecodeT2AddrModeImm0_1020s4(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3723 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
3724 uint64_t Address, const void *Decoder) {
3725 DecodeStatus S = MCDisassembler::Success;
3726
3727 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3728 unsigned imm = fieldFromInstruction(Val, 0, 8);
3729
3730 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3731 return MCDisassembler::Fail;
3732
3733 Inst.addOperand(MCOperand::createImm(imm));
3734
3735 return S;
3736 }
3737
DecodeT2Imm8(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3738 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3739 uint64_t Address, const void *Decoder) {
3740 int imm = Val & 0xFF;
3741 if (Val == 0)
3742 imm = INT32_MIN;
3743 else if (!(Val & 0x100))
3744 imm *= -1;
3745 Inst.addOperand(MCOperand::createImm(imm));
3746
3747 return MCDisassembler::Success;
3748 }
3749
3750
DecodeT2AddrModeImm8(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3751 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3752 uint64_t Address, const void *Decoder) {
3753 DecodeStatus S = MCDisassembler::Success;
3754
3755 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3756 unsigned imm = fieldFromInstruction(Val, 0, 9);
3757
3758 // Thumb stores cannot use PC as dest register.
3759 switch (Inst.getOpcode()) {
3760 case ARM::t2STRT:
3761 case ARM::t2STRBT:
3762 case ARM::t2STRHT:
3763 case ARM::t2STRi8:
3764 case ARM::t2STRHi8:
3765 case ARM::t2STRBi8:
3766 if (Rn == 15)
3767 return MCDisassembler::Fail;
3768 break;
3769 default:
3770 break;
3771 }
3772
3773 // Some instructions always use an additive offset.
3774 switch (Inst.getOpcode()) {
3775 case ARM::t2LDRT:
3776 case ARM::t2LDRBT:
3777 case ARM::t2LDRHT:
3778 case ARM::t2LDRSBT:
3779 case ARM::t2LDRSHT:
3780 case ARM::t2STRT:
3781 case ARM::t2STRBT:
3782 case ARM::t2STRHT:
3783 imm |= 0x100;
3784 break;
3785 default:
3786 break;
3787 }
3788
3789 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3790 return MCDisassembler::Fail;
3791 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3792 return MCDisassembler::Fail;
3793
3794 return S;
3795 }
3796
DecodeT2LdStPre(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3797 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3798 uint64_t Address, const void *Decoder) {
3799 DecodeStatus S = MCDisassembler::Success;
3800
3801 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3802 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3803 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3804 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3805 addr |= Rn << 9;
3806 unsigned load = fieldFromInstruction(Insn, 20, 1);
3807
3808 if (Rn == 15) {
3809 switch (Inst.getOpcode()) {
3810 case ARM::t2LDR_PRE:
3811 case ARM::t2LDR_POST:
3812 Inst.setOpcode(ARM::t2LDRpci);
3813 break;
3814 case ARM::t2LDRB_PRE:
3815 case ARM::t2LDRB_POST:
3816 Inst.setOpcode(ARM::t2LDRBpci);
3817 break;
3818 case ARM::t2LDRH_PRE:
3819 case ARM::t2LDRH_POST:
3820 Inst.setOpcode(ARM::t2LDRHpci);
3821 break;
3822 case ARM::t2LDRSB_PRE:
3823 case ARM::t2LDRSB_POST:
3824 if (Rt == 15)
3825 Inst.setOpcode(ARM::t2PLIpci);
3826 else
3827 Inst.setOpcode(ARM::t2LDRSBpci);
3828 break;
3829 case ARM::t2LDRSH_PRE:
3830 case ARM::t2LDRSH_POST:
3831 Inst.setOpcode(ARM::t2LDRSHpci);
3832 break;
3833 default:
3834 return MCDisassembler::Fail;
3835 }
3836 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3837 }
3838
3839 if (!load) {
3840 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3841 return MCDisassembler::Fail;
3842 }
3843
3844 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3845 return MCDisassembler::Fail;
3846
3847 if (load) {
3848 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3849 return MCDisassembler::Fail;
3850 }
3851
3852 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3853 return MCDisassembler::Fail;
3854
3855 return S;
3856 }
3857
DecodeT2AddrModeImm12(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3858 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3859 uint64_t Address, const void *Decoder) {
3860 DecodeStatus S = MCDisassembler::Success;
3861
3862 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3863 unsigned imm = fieldFromInstruction(Val, 0, 12);
3864
3865 // Thumb stores cannot use PC as dest register.
3866 switch (Inst.getOpcode()) {
3867 case ARM::t2STRi12:
3868 case ARM::t2STRBi12:
3869 case ARM::t2STRHi12:
3870 if (Rn == 15)
3871 return MCDisassembler::Fail;
3872 default:
3873 break;
3874 }
3875
3876 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3877 return MCDisassembler::Fail;
3878 Inst.addOperand(MCOperand::createImm(imm));
3879
3880 return S;
3881 }
3882
3883
DecodeThumbAddSPImm(MCInst & Inst,uint16_t Insn,uint64_t Address,const void * Decoder)3884 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3885 uint64_t Address, const void *Decoder) {
3886 unsigned imm = fieldFromInstruction(Insn, 0, 7);
3887
3888 Inst.addOperand(MCOperand::createReg(ARM::SP));
3889 Inst.addOperand(MCOperand::createReg(ARM::SP));
3890 Inst.addOperand(MCOperand::createImm(imm));
3891
3892 return MCDisassembler::Success;
3893 }
3894
DecodeThumbAddSPReg(MCInst & Inst,uint16_t Insn,uint64_t Address,const void * Decoder)3895 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3896 uint64_t Address, const void *Decoder) {
3897 DecodeStatus S = MCDisassembler::Success;
3898
3899 if (Inst.getOpcode() == ARM::tADDrSP) {
3900 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3901 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3902
3903 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3904 return MCDisassembler::Fail;
3905 Inst.addOperand(MCOperand::createReg(ARM::SP));
3906 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3907 return MCDisassembler::Fail;
3908 } else if (Inst.getOpcode() == ARM::tADDspr) {
3909 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3910
3911 Inst.addOperand(MCOperand::createReg(ARM::SP));
3912 Inst.addOperand(MCOperand::createReg(ARM::SP));
3913 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3914 return MCDisassembler::Fail;
3915 }
3916
3917 return S;
3918 }
3919
DecodeThumbCPS(MCInst & Inst,uint16_t Insn,uint64_t Address,const void * Decoder)3920 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3921 uint64_t Address, const void *Decoder) {
3922 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3923 unsigned flags = fieldFromInstruction(Insn, 0, 3);
3924
3925 Inst.addOperand(MCOperand::createImm(imod));
3926 Inst.addOperand(MCOperand::createImm(flags));
3927
3928 return MCDisassembler::Success;
3929 }
3930
DecodePostIdxReg(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3931 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3932 uint64_t Address, const void *Decoder) {
3933 DecodeStatus S = MCDisassembler::Success;
3934 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3935 unsigned add = fieldFromInstruction(Insn, 4, 1);
3936
3937 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3938 return MCDisassembler::Fail;
3939 Inst.addOperand(MCOperand::createImm(add));
3940
3941 return S;
3942 }
3943
DecodeThumbBLXOffset(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3944 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3945 uint64_t Address, const void *Decoder) {
3946 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3947 // Note only one trailing zero not two. Also the J1 and J2 values are from
3948 // the encoded instruction. So here change to I1 and I2 values via:
3949 // I1 = NOT(J1 EOR S);
3950 // I2 = NOT(J2 EOR S);
3951 // and build the imm32 with two trailing zeros as documented:
3952 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3953 unsigned S = (Val >> 23) & 1;
3954 unsigned J1 = (Val >> 22) & 1;
3955 unsigned J2 = (Val >> 21) & 1;
3956 unsigned I1 = !(J1 ^ S);
3957 unsigned I2 = !(J2 ^ S);
3958 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3959 int imm32 = SignExtend32<25>(tmp << 1);
3960
3961 if (!tryAddingSymbolicOperand(Address,
3962 (Address & ~2u) + imm32 + 4,
3963 true, 4, Inst, Decoder))
3964 Inst.addOperand(MCOperand::createImm(imm32));
3965 return MCDisassembler::Success;
3966 }
3967
DecodeCoprocessor(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3968 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3969 uint64_t Address, const void *Decoder) {
3970 if (Val == 0xA || Val == 0xB)
3971 return MCDisassembler::Fail;
3972
3973 const FeatureBitset &featureBits =
3974 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3975
3976 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
3977 return MCDisassembler::Fail;
3978
3979 Inst.addOperand(MCOperand::createImm(Val));
3980 return MCDisassembler::Success;
3981 }
3982
3983 static DecodeStatus
DecodeThumbTableBranch(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3984 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3985 uint64_t Address, const void *Decoder) {
3986 DecodeStatus S = MCDisassembler::Success;
3987
3988 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3989 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3990
3991 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3992 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3993 return MCDisassembler::Fail;
3994 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3995 return MCDisassembler::Fail;
3996 return S;
3997 }
3998
3999 static DecodeStatus
DecodeThumb2BCCInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4000 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
4001 uint64_t Address, const void *Decoder) {
4002 DecodeStatus S = MCDisassembler::Success;
4003
4004 unsigned pred = fieldFromInstruction(Insn, 22, 4);
4005 if (pred == 0xE || pred == 0xF) {
4006 unsigned opc = fieldFromInstruction(Insn, 4, 28);
4007 switch (opc) {
4008 default:
4009 return MCDisassembler::Fail;
4010 case 0xf3bf8f4:
4011 Inst.setOpcode(ARM::t2DSB);
4012 break;
4013 case 0xf3bf8f5:
4014 Inst.setOpcode(ARM::t2DMB);
4015 break;
4016 case 0xf3bf8f6:
4017 Inst.setOpcode(ARM::t2ISB);
4018 break;
4019 }
4020
4021 unsigned imm = fieldFromInstruction(Insn, 0, 4);
4022 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
4023 }
4024
4025 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
4026 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
4027 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
4028 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
4029 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
4030
4031 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
4032 return MCDisassembler::Fail;
4033 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4034 return MCDisassembler::Fail;
4035
4036 return S;
4037 }
4038
4039 // Decode a shifted immediate operand. These basically consist
4040 // of an 8-bit value, and a 4-bit directive that specifies either
4041 // a splat operation or a rotation.
DecodeT2SOImm(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4042 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
4043 uint64_t Address, const void *Decoder) {
4044 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
4045 if (ctrl == 0) {
4046 unsigned byte = fieldFromInstruction(Val, 8, 2);
4047 unsigned imm = fieldFromInstruction(Val, 0, 8);
4048 switch (byte) {
4049 case 0:
4050 Inst.addOperand(MCOperand::createImm(imm));
4051 break;
4052 case 1:
4053 Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
4054 break;
4055 case 2:
4056 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
4057 break;
4058 case 3:
4059 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
4060 (imm << 8) | imm));
4061 break;
4062 }
4063 } else {
4064 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
4065 unsigned rot = fieldFromInstruction(Val, 7, 5);
4066 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
4067 Inst.addOperand(MCOperand::createImm(imm));
4068 }
4069
4070 return MCDisassembler::Success;
4071 }
4072
4073 static DecodeStatus
DecodeThumbBCCTargetOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4074 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
4075 uint64_t Address, const void *Decoder){
4076 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
4077 true, 2, Inst, Decoder))
4078 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
4079 return MCDisassembler::Success;
4080 }
4081
DecodeThumbBLTargetOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4082 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
4083 uint64_t Address, const void *Decoder){
4084 // Val is passed in as S:J1:J2:imm10:imm11
4085 // Note no trailing zero after imm11. Also the J1 and J2 values are from
4086 // the encoded instruction. So here change to I1 and I2 values via:
4087 // I1 = NOT(J1 EOR S);
4088 // I2 = NOT(J2 EOR S);
4089 // and build the imm32 with one trailing zero as documented:
4090 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
4091 unsigned S = (Val >> 23) & 1;
4092 unsigned J1 = (Val >> 22) & 1;
4093 unsigned J2 = (Val >> 21) & 1;
4094 unsigned I1 = !(J1 ^ S);
4095 unsigned I2 = !(J2 ^ S);
4096 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4097 int imm32 = SignExtend32<25>(tmp << 1);
4098
4099 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
4100 true, 4, Inst, Decoder))
4101 Inst.addOperand(MCOperand::createImm(imm32));
4102 return MCDisassembler::Success;
4103 }
4104
DecodeMemBarrierOption(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4105 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
4106 uint64_t Address, const void *Decoder) {
4107 if (Val & ~0xf)
4108 return MCDisassembler::Fail;
4109
4110 Inst.addOperand(MCOperand::createImm(Val));
4111 return MCDisassembler::Success;
4112 }
4113
DecodeInstSyncBarrierOption(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4114 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
4115 uint64_t Address, const void *Decoder) {
4116 if (Val & ~0xf)
4117 return MCDisassembler::Fail;
4118
4119 Inst.addOperand(MCOperand::createImm(Val));
4120 return MCDisassembler::Success;
4121 }
4122
DecodeMSRMask(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4123 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
4124 uint64_t Address, const void *Decoder) {
4125 DecodeStatus S = MCDisassembler::Success;
4126 const FeatureBitset &FeatureBits =
4127 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4128
4129 if (FeatureBits[ARM::FeatureMClass]) {
4130 unsigned ValLow = Val & 0xff;
4131
4132 // Validate the SYSm value first.
4133 switch (ValLow) {
4134 case 0: // apsr
4135 case 1: // iapsr
4136 case 2: // eapsr
4137 case 3: // xpsr
4138 case 5: // ipsr
4139 case 6: // epsr
4140 case 7: // iepsr
4141 case 8: // msp
4142 case 9: // psp
4143 case 16: // primask
4144 case 20: // control
4145 break;
4146 case 17: // basepri
4147 case 18: // basepri_max
4148 case 19: // faultmask
4149 if (!(FeatureBits[ARM::HasV7Ops]))
4150 // Values basepri, basepri_max and faultmask are only valid for v7m.
4151 return MCDisassembler::Fail;
4152 break;
4153 case 0x8a: // msplim_ns
4154 case 0x8b: // psplim_ns
4155 case 0x91: // basepri_ns
4156 case 0x92: // basepri_max_ns
4157 case 0x93: // faultmask_ns
4158 if (!(FeatureBits[ARM::HasV8MMainlineOps]))
4159 return MCDisassembler::Fail;
4160 // fall through
4161 case 10: // msplim
4162 case 11: // psplim
4163 case 0x88: // msp_ns
4164 case 0x89: // psp_ns
4165 case 0x90: // primask_ns
4166 case 0x94: // control_ns
4167 case 0x98: // sp_ns
4168 if (!(FeatureBits[ARM::Feature8MSecExt]))
4169 return MCDisassembler::Fail;
4170 break;
4171 default:
4172 return MCDisassembler::Fail;
4173 }
4174
4175 if (Inst.getOpcode() == ARM::t2MSR_M) {
4176 unsigned Mask = fieldFromInstruction(Val, 10, 2);
4177 if (!(FeatureBits[ARM::HasV7Ops])) {
4178 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4179 // unpredictable.
4180 if (Mask != 2)
4181 S = MCDisassembler::SoftFail;
4182 }
4183 else {
4184 // The ARMv7-M architecture stores an additional 2-bit mask value in
4185 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4186 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4187 // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4188 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4189 // only if the processor includes the DSP extension.
4190 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4191 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
4192 S = MCDisassembler::SoftFail;
4193 }
4194 }
4195 } else {
4196 // A/R class
4197 if (Val == 0)
4198 return MCDisassembler::Fail;
4199 }
4200 Inst.addOperand(MCOperand::createImm(Val));
4201 return S;
4202 }
4203
DecodeBankedReg(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4204 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
4205 uint64_t Address, const void *Decoder) {
4206
4207 unsigned R = fieldFromInstruction(Val, 5, 1);
4208 unsigned SysM = fieldFromInstruction(Val, 0, 5);
4209
4210 // The table of encodings for these banked registers comes from B9.2.3 of the
4211 // ARM ARM. There are patterns, but nothing regular enough to make this logic
4212 // neater. So by fiat, these values are UNPREDICTABLE:
4213 if (!R) {
4214 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
4215 SysM == 0x1a || SysM == 0x1b)
4216 return MCDisassembler::SoftFail;
4217 } else {
4218 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
4219 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
4220 return MCDisassembler::SoftFail;
4221 }
4222
4223 Inst.addOperand(MCOperand::createImm(Val));
4224 return MCDisassembler::Success;
4225 }
4226
DecodeDoubleRegLoad(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4227 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
4228 uint64_t Address, const void *Decoder) {
4229 DecodeStatus S = MCDisassembler::Success;
4230
4231 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4232 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4233 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4234
4235 if (Rn == 0xF)
4236 S = MCDisassembler::SoftFail;
4237
4238 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4239 return MCDisassembler::Fail;
4240 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4241 return MCDisassembler::Fail;
4242 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4243 return MCDisassembler::Fail;
4244
4245 return S;
4246 }
4247
DecodeDoubleRegStore(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4248 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4249 uint64_t Address, const void *Decoder){
4250 DecodeStatus S = MCDisassembler::Success;
4251
4252 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4253 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4254 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4255 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4256
4257 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4258 return MCDisassembler::Fail;
4259
4260 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4261 S = MCDisassembler::SoftFail;
4262
4263 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4264 return MCDisassembler::Fail;
4265 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4266 return MCDisassembler::Fail;
4267 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4268 return MCDisassembler::Fail;
4269
4270 return S;
4271 }
4272
DecodeLDRPreImm(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4273 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4274 uint64_t Address, const void *Decoder) {
4275 DecodeStatus S = MCDisassembler::Success;
4276
4277 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4278 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4279 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4280 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4281 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4282 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4283
4284 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4285
4286 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4287 return MCDisassembler::Fail;
4288 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4289 return MCDisassembler::Fail;
4290 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4291 return MCDisassembler::Fail;
4292 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4293 return MCDisassembler::Fail;
4294
4295 return S;
4296 }
4297
DecodeLDRPreReg(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4298 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4299 uint64_t Address, const void *Decoder) {
4300 DecodeStatus S = MCDisassembler::Success;
4301
4302 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4303 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4304 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4305 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4306 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4307 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4308 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4309
4310 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4311 if (Rm == 0xF) S = MCDisassembler::SoftFail;
4312
4313 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4314 return MCDisassembler::Fail;
4315 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4316 return MCDisassembler::Fail;
4317 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4318 return MCDisassembler::Fail;
4319 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4320 return MCDisassembler::Fail;
4321
4322 return S;
4323 }
4324
4325
DecodeSTRPreImm(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4326 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4327 uint64_t Address, const void *Decoder) {
4328 DecodeStatus S = MCDisassembler::Success;
4329
4330 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4331 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4332 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4333 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4334 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4335 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4336
4337 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4338
4339 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4340 return MCDisassembler::Fail;
4341 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4342 return MCDisassembler::Fail;
4343 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4344 return MCDisassembler::Fail;
4345 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4346 return MCDisassembler::Fail;
4347
4348 return S;
4349 }
4350
DecodeSTRPreReg(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4351 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4352 uint64_t Address, const void *Decoder) {
4353 DecodeStatus S = MCDisassembler::Success;
4354
4355 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4356 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4357 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4358 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4359 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4360 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4361
4362 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4363
4364 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4365 return MCDisassembler::Fail;
4366 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4367 return MCDisassembler::Fail;
4368 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4369 return MCDisassembler::Fail;
4370 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4371 return MCDisassembler::Fail;
4372
4373 return S;
4374 }
4375
DecodeVLD1LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4376 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
4377 uint64_t Address, const void *Decoder) {
4378 DecodeStatus S = MCDisassembler::Success;
4379
4380 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4381 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4382 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4383 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4384 unsigned size = fieldFromInstruction(Insn, 10, 2);
4385
4386 unsigned align = 0;
4387 unsigned index = 0;
4388 switch (size) {
4389 default:
4390 return MCDisassembler::Fail;
4391 case 0:
4392 if (fieldFromInstruction(Insn, 4, 1))
4393 return MCDisassembler::Fail; // UNDEFINED
4394 index = fieldFromInstruction(Insn, 5, 3);
4395 break;
4396 case 1:
4397 if (fieldFromInstruction(Insn, 5, 1))
4398 return MCDisassembler::Fail; // UNDEFINED
4399 index = fieldFromInstruction(Insn, 6, 2);
4400 if (fieldFromInstruction(Insn, 4, 1))
4401 align = 2;
4402 break;
4403 case 2:
4404 if (fieldFromInstruction(Insn, 6, 1))
4405 return MCDisassembler::Fail; // UNDEFINED
4406 index = fieldFromInstruction(Insn, 7, 1);
4407
4408 switch (fieldFromInstruction(Insn, 4, 2)) {
4409 case 0 :
4410 align = 0; break;
4411 case 3:
4412 align = 4; break;
4413 default:
4414 return MCDisassembler::Fail;
4415 }
4416 break;
4417 }
4418
4419 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4420 return MCDisassembler::Fail;
4421 if (Rm != 0xF) { // Writeback
4422 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4423 return MCDisassembler::Fail;
4424 }
4425 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4426 return MCDisassembler::Fail;
4427 Inst.addOperand(MCOperand::createImm(align));
4428 if (Rm != 0xF) {
4429 if (Rm != 0xD) {
4430 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4431 return MCDisassembler::Fail;
4432 } else
4433 Inst.addOperand(MCOperand::createReg(0));
4434 }
4435
4436 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4437 return MCDisassembler::Fail;
4438 Inst.addOperand(MCOperand::createImm(index));
4439
4440 return S;
4441 }
4442
DecodeVST1LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4443 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
4444 uint64_t Address, const void *Decoder) {
4445 DecodeStatus S = MCDisassembler::Success;
4446
4447 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4448 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4449 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4450 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4451 unsigned size = fieldFromInstruction(Insn, 10, 2);
4452
4453 unsigned align = 0;
4454 unsigned index = 0;
4455 switch (size) {
4456 default:
4457 return MCDisassembler::Fail;
4458 case 0:
4459 if (fieldFromInstruction(Insn, 4, 1))
4460 return MCDisassembler::Fail; // UNDEFINED
4461 index = fieldFromInstruction(Insn, 5, 3);
4462 break;
4463 case 1:
4464 if (fieldFromInstruction(Insn, 5, 1))
4465 return MCDisassembler::Fail; // UNDEFINED
4466 index = fieldFromInstruction(Insn, 6, 2);
4467 if (fieldFromInstruction(Insn, 4, 1))
4468 align = 2;
4469 break;
4470 case 2:
4471 if (fieldFromInstruction(Insn, 6, 1))
4472 return MCDisassembler::Fail; // UNDEFINED
4473 index = fieldFromInstruction(Insn, 7, 1);
4474
4475 switch (fieldFromInstruction(Insn, 4, 2)) {
4476 case 0:
4477 align = 0; break;
4478 case 3:
4479 align = 4; break;
4480 default:
4481 return MCDisassembler::Fail;
4482 }
4483 break;
4484 }
4485
4486 if (Rm != 0xF) { // Writeback
4487 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4488 return MCDisassembler::Fail;
4489 }
4490 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4491 return MCDisassembler::Fail;
4492 Inst.addOperand(MCOperand::createImm(align));
4493 if (Rm != 0xF) {
4494 if (Rm != 0xD) {
4495 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4496 return MCDisassembler::Fail;
4497 } else
4498 Inst.addOperand(MCOperand::createReg(0));
4499 }
4500
4501 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4502 return MCDisassembler::Fail;
4503 Inst.addOperand(MCOperand::createImm(index));
4504
4505 return S;
4506 }
4507
4508
DecodeVLD2LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4509 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
4510 uint64_t Address, const void *Decoder) {
4511 DecodeStatus S = MCDisassembler::Success;
4512
4513 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4514 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4515 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4516 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4517 unsigned size = fieldFromInstruction(Insn, 10, 2);
4518
4519 unsigned align = 0;
4520 unsigned index = 0;
4521 unsigned inc = 1;
4522 switch (size) {
4523 default:
4524 return MCDisassembler::Fail;
4525 case 0:
4526 index = fieldFromInstruction(Insn, 5, 3);
4527 if (fieldFromInstruction(Insn, 4, 1))
4528 align = 2;
4529 break;
4530 case 1:
4531 index = fieldFromInstruction(Insn, 6, 2);
4532 if (fieldFromInstruction(Insn, 4, 1))
4533 align = 4;
4534 if (fieldFromInstruction(Insn, 5, 1))
4535 inc = 2;
4536 break;
4537 case 2:
4538 if (fieldFromInstruction(Insn, 5, 1))
4539 return MCDisassembler::Fail; // UNDEFINED
4540 index = fieldFromInstruction(Insn, 7, 1);
4541 if (fieldFromInstruction(Insn, 4, 1) != 0)
4542 align = 8;
4543 if (fieldFromInstruction(Insn, 6, 1))
4544 inc = 2;
4545 break;
4546 }
4547
4548 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4549 return MCDisassembler::Fail;
4550 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4551 return MCDisassembler::Fail;
4552 if (Rm != 0xF) { // Writeback
4553 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4554 return MCDisassembler::Fail;
4555 }
4556 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4557 return MCDisassembler::Fail;
4558 Inst.addOperand(MCOperand::createImm(align));
4559 if (Rm != 0xF) {
4560 if (Rm != 0xD) {
4561 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4562 return MCDisassembler::Fail;
4563 } else
4564 Inst.addOperand(MCOperand::createReg(0));
4565 }
4566
4567 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4568 return MCDisassembler::Fail;
4569 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4570 return MCDisassembler::Fail;
4571 Inst.addOperand(MCOperand::createImm(index));
4572
4573 return S;
4574 }
4575
DecodeVST2LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4576 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
4577 uint64_t Address, const void *Decoder) {
4578 DecodeStatus S = MCDisassembler::Success;
4579
4580 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4581 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4582 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4583 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4584 unsigned size = fieldFromInstruction(Insn, 10, 2);
4585
4586 unsigned align = 0;
4587 unsigned index = 0;
4588 unsigned inc = 1;
4589 switch (size) {
4590 default:
4591 return MCDisassembler::Fail;
4592 case 0:
4593 index = fieldFromInstruction(Insn, 5, 3);
4594 if (fieldFromInstruction(Insn, 4, 1))
4595 align = 2;
4596 break;
4597 case 1:
4598 index = fieldFromInstruction(Insn, 6, 2);
4599 if (fieldFromInstruction(Insn, 4, 1))
4600 align = 4;
4601 if (fieldFromInstruction(Insn, 5, 1))
4602 inc = 2;
4603 break;
4604 case 2:
4605 if (fieldFromInstruction(Insn, 5, 1))
4606 return MCDisassembler::Fail; // UNDEFINED
4607 index = fieldFromInstruction(Insn, 7, 1);
4608 if (fieldFromInstruction(Insn, 4, 1) != 0)
4609 align = 8;
4610 if (fieldFromInstruction(Insn, 6, 1))
4611 inc = 2;
4612 break;
4613 }
4614
4615 if (Rm != 0xF) { // Writeback
4616 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4617 return MCDisassembler::Fail;
4618 }
4619 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4620 return MCDisassembler::Fail;
4621 Inst.addOperand(MCOperand::createImm(align));
4622 if (Rm != 0xF) {
4623 if (Rm != 0xD) {
4624 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4625 return MCDisassembler::Fail;
4626 } else
4627 Inst.addOperand(MCOperand::createReg(0));
4628 }
4629
4630 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4631 return MCDisassembler::Fail;
4632 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4633 return MCDisassembler::Fail;
4634 Inst.addOperand(MCOperand::createImm(index));
4635
4636 return S;
4637 }
4638
4639
DecodeVLD3LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4640 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
4641 uint64_t Address, const void *Decoder) {
4642 DecodeStatus S = MCDisassembler::Success;
4643
4644 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4645 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4646 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4647 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4648 unsigned size = fieldFromInstruction(Insn, 10, 2);
4649
4650 unsigned align = 0;
4651 unsigned index = 0;
4652 unsigned inc = 1;
4653 switch (size) {
4654 default:
4655 return MCDisassembler::Fail;
4656 case 0:
4657 if (fieldFromInstruction(Insn, 4, 1))
4658 return MCDisassembler::Fail; // UNDEFINED
4659 index = fieldFromInstruction(Insn, 5, 3);
4660 break;
4661 case 1:
4662 if (fieldFromInstruction(Insn, 4, 1))
4663 return MCDisassembler::Fail; // UNDEFINED
4664 index = fieldFromInstruction(Insn, 6, 2);
4665 if (fieldFromInstruction(Insn, 5, 1))
4666 inc = 2;
4667 break;
4668 case 2:
4669 if (fieldFromInstruction(Insn, 4, 2))
4670 return MCDisassembler::Fail; // UNDEFINED
4671 index = fieldFromInstruction(Insn, 7, 1);
4672 if (fieldFromInstruction(Insn, 6, 1))
4673 inc = 2;
4674 break;
4675 }
4676
4677 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4678 return MCDisassembler::Fail;
4679 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4680 return MCDisassembler::Fail;
4681 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4682 return MCDisassembler::Fail;
4683
4684 if (Rm != 0xF) { // Writeback
4685 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4686 return MCDisassembler::Fail;
4687 }
4688 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4689 return MCDisassembler::Fail;
4690 Inst.addOperand(MCOperand::createImm(align));
4691 if (Rm != 0xF) {
4692 if (Rm != 0xD) {
4693 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4694 return MCDisassembler::Fail;
4695 } else
4696 Inst.addOperand(MCOperand::createReg(0));
4697 }
4698
4699 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4700 return MCDisassembler::Fail;
4701 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4702 return MCDisassembler::Fail;
4703 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4704 return MCDisassembler::Fail;
4705 Inst.addOperand(MCOperand::createImm(index));
4706
4707 return S;
4708 }
4709
DecodeVST3LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4710 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
4711 uint64_t Address, const void *Decoder) {
4712 DecodeStatus S = MCDisassembler::Success;
4713
4714 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4715 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4716 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4717 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4718 unsigned size = fieldFromInstruction(Insn, 10, 2);
4719
4720 unsigned align = 0;
4721 unsigned index = 0;
4722 unsigned inc = 1;
4723 switch (size) {
4724 default:
4725 return MCDisassembler::Fail;
4726 case 0:
4727 if (fieldFromInstruction(Insn, 4, 1))
4728 return MCDisassembler::Fail; // UNDEFINED
4729 index = fieldFromInstruction(Insn, 5, 3);
4730 break;
4731 case 1:
4732 if (fieldFromInstruction(Insn, 4, 1))
4733 return MCDisassembler::Fail; // UNDEFINED
4734 index = fieldFromInstruction(Insn, 6, 2);
4735 if (fieldFromInstruction(Insn, 5, 1))
4736 inc = 2;
4737 break;
4738 case 2:
4739 if (fieldFromInstruction(Insn, 4, 2))
4740 return MCDisassembler::Fail; // UNDEFINED
4741 index = fieldFromInstruction(Insn, 7, 1);
4742 if (fieldFromInstruction(Insn, 6, 1))
4743 inc = 2;
4744 break;
4745 }
4746
4747 if (Rm != 0xF) { // Writeback
4748 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4749 return MCDisassembler::Fail;
4750 }
4751 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4752 return MCDisassembler::Fail;
4753 Inst.addOperand(MCOperand::createImm(align));
4754 if (Rm != 0xF) {
4755 if (Rm != 0xD) {
4756 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4757 return MCDisassembler::Fail;
4758 } else
4759 Inst.addOperand(MCOperand::createReg(0));
4760 }
4761
4762 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4763 return MCDisassembler::Fail;
4764 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4765 return MCDisassembler::Fail;
4766 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4767 return MCDisassembler::Fail;
4768 Inst.addOperand(MCOperand::createImm(index));
4769
4770 return S;
4771 }
4772
4773
DecodeVLD4LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4774 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4775 uint64_t Address, const void *Decoder) {
4776 DecodeStatus S = MCDisassembler::Success;
4777
4778 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4779 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4780 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4781 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4782 unsigned size = fieldFromInstruction(Insn, 10, 2);
4783
4784 unsigned align = 0;
4785 unsigned index = 0;
4786 unsigned inc = 1;
4787 switch (size) {
4788 default:
4789 return MCDisassembler::Fail;
4790 case 0:
4791 if (fieldFromInstruction(Insn, 4, 1))
4792 align = 4;
4793 index = fieldFromInstruction(Insn, 5, 3);
4794 break;
4795 case 1:
4796 if (fieldFromInstruction(Insn, 4, 1))
4797 align = 8;
4798 index = fieldFromInstruction(Insn, 6, 2);
4799 if (fieldFromInstruction(Insn, 5, 1))
4800 inc = 2;
4801 break;
4802 case 2:
4803 switch (fieldFromInstruction(Insn, 4, 2)) {
4804 case 0:
4805 align = 0; break;
4806 case 3:
4807 return MCDisassembler::Fail;
4808 default:
4809 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4810 }
4811
4812 index = fieldFromInstruction(Insn, 7, 1);
4813 if (fieldFromInstruction(Insn, 6, 1))
4814 inc = 2;
4815 break;
4816 }
4817
4818 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4819 return MCDisassembler::Fail;
4820 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4821 return MCDisassembler::Fail;
4822 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4823 return MCDisassembler::Fail;
4824 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4825 return MCDisassembler::Fail;
4826
4827 if (Rm != 0xF) { // Writeback
4828 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4829 return MCDisassembler::Fail;
4830 }
4831 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4832 return MCDisassembler::Fail;
4833 Inst.addOperand(MCOperand::createImm(align));
4834 if (Rm != 0xF) {
4835 if (Rm != 0xD) {
4836 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4837 return MCDisassembler::Fail;
4838 } else
4839 Inst.addOperand(MCOperand::createReg(0));
4840 }
4841
4842 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4843 return MCDisassembler::Fail;
4844 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4845 return MCDisassembler::Fail;
4846 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4847 return MCDisassembler::Fail;
4848 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4849 return MCDisassembler::Fail;
4850 Inst.addOperand(MCOperand::createImm(index));
4851
4852 return S;
4853 }
4854
DecodeVST4LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4855 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4856 uint64_t Address, const void *Decoder) {
4857 DecodeStatus S = MCDisassembler::Success;
4858
4859 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4860 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4861 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4862 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4863 unsigned size = fieldFromInstruction(Insn, 10, 2);
4864
4865 unsigned align = 0;
4866 unsigned index = 0;
4867 unsigned inc = 1;
4868 switch (size) {
4869 default:
4870 return MCDisassembler::Fail;
4871 case 0:
4872 if (fieldFromInstruction(Insn, 4, 1))
4873 align = 4;
4874 index = fieldFromInstruction(Insn, 5, 3);
4875 break;
4876 case 1:
4877 if (fieldFromInstruction(Insn, 4, 1))
4878 align = 8;
4879 index = fieldFromInstruction(Insn, 6, 2);
4880 if (fieldFromInstruction(Insn, 5, 1))
4881 inc = 2;
4882 break;
4883 case 2:
4884 switch (fieldFromInstruction(Insn, 4, 2)) {
4885 case 0:
4886 align = 0; break;
4887 case 3:
4888 return MCDisassembler::Fail;
4889 default:
4890 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4891 }
4892
4893 index = fieldFromInstruction(Insn, 7, 1);
4894 if (fieldFromInstruction(Insn, 6, 1))
4895 inc = 2;
4896 break;
4897 }
4898
4899 if (Rm != 0xF) { // Writeback
4900 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4901 return MCDisassembler::Fail;
4902 }
4903 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4904 return MCDisassembler::Fail;
4905 Inst.addOperand(MCOperand::createImm(align));
4906 if (Rm != 0xF) {
4907 if (Rm != 0xD) {
4908 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4909 return MCDisassembler::Fail;
4910 } else
4911 Inst.addOperand(MCOperand::createReg(0));
4912 }
4913
4914 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4915 return MCDisassembler::Fail;
4916 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4917 return MCDisassembler::Fail;
4918 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4919 return MCDisassembler::Fail;
4920 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4921 return MCDisassembler::Fail;
4922 Inst.addOperand(MCOperand::createImm(index));
4923
4924 return S;
4925 }
4926
DecodeVMOVSRR(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4927 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4928 uint64_t Address, const void *Decoder) {
4929 DecodeStatus S = MCDisassembler::Success;
4930 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4931 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4932 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4933 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4934 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4935
4936 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4937 S = MCDisassembler::SoftFail;
4938
4939 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4940 return MCDisassembler::Fail;
4941 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4942 return MCDisassembler::Fail;
4943 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4944 return MCDisassembler::Fail;
4945 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4946 return MCDisassembler::Fail;
4947 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4948 return MCDisassembler::Fail;
4949
4950 return S;
4951 }
4952
DecodeVMOVRRS(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4953 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4954 uint64_t Address, const void *Decoder) {
4955 DecodeStatus S = MCDisassembler::Success;
4956 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4957 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4958 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4959 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4960 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4961
4962 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4963 S = MCDisassembler::SoftFail;
4964
4965 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4966 return MCDisassembler::Fail;
4967 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4968 return MCDisassembler::Fail;
4969 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4970 return MCDisassembler::Fail;
4971 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4972 return MCDisassembler::Fail;
4973 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4974 return MCDisassembler::Fail;
4975
4976 return S;
4977 }
4978
DecodeIT(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4979 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4980 uint64_t Address, const void *Decoder) {
4981 DecodeStatus S = MCDisassembler::Success;
4982 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4983 unsigned mask = fieldFromInstruction(Insn, 0, 4);
4984
4985 if (pred == 0xF) {
4986 pred = 0xE;
4987 S = MCDisassembler::SoftFail;
4988 }
4989
4990 if (mask == 0x0)
4991 return MCDisassembler::Fail;
4992
4993 Inst.addOperand(MCOperand::createImm(pred));
4994 Inst.addOperand(MCOperand::createImm(mask));
4995 return S;
4996 }
4997
4998 static DecodeStatus
DecodeT2LDRDPreInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4999 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
5000 uint64_t Address, const void *Decoder) {
5001 DecodeStatus S = MCDisassembler::Success;
5002
5003 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5004 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
5005 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5006 unsigned addr = fieldFromInstruction(Insn, 0, 8);
5007 unsigned W = fieldFromInstruction(Insn, 21, 1);
5008 unsigned U = fieldFromInstruction(Insn, 23, 1);
5009 unsigned P = fieldFromInstruction(Insn, 24, 1);
5010 bool writeback = (W == 1) | (P == 0);
5011
5012 addr |= (U << 8) | (Rn << 9);
5013
5014 if (writeback && (Rn == Rt || Rn == Rt2))
5015 Check(S, MCDisassembler::SoftFail);
5016 if (Rt == Rt2)
5017 Check(S, MCDisassembler::SoftFail);
5018
5019 // Rt
5020 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5021 return MCDisassembler::Fail;
5022 // Rt2
5023 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5024 return MCDisassembler::Fail;
5025 // Writeback operand
5026 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5027 return MCDisassembler::Fail;
5028 // addr
5029 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5030 return MCDisassembler::Fail;
5031
5032 return S;
5033 }
5034
5035 static DecodeStatus
DecodeT2STRDPreInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)5036 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
5037 uint64_t Address, const void *Decoder) {
5038 DecodeStatus S = MCDisassembler::Success;
5039
5040 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5041 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
5042 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5043 unsigned addr = fieldFromInstruction(Insn, 0, 8);
5044 unsigned W = fieldFromInstruction(Insn, 21, 1);
5045 unsigned U = fieldFromInstruction(Insn, 23, 1);
5046 unsigned P = fieldFromInstruction(Insn, 24, 1);
5047 bool writeback = (W == 1) | (P == 0);
5048
5049 addr |= (U << 8) | (Rn << 9);
5050
5051 if (writeback && (Rn == Rt || Rn == Rt2))
5052 Check(S, MCDisassembler::SoftFail);
5053
5054 // Writeback operand
5055 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5056 return MCDisassembler::Fail;
5057 // Rt
5058 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5059 return MCDisassembler::Fail;
5060 // Rt2
5061 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5062 return MCDisassembler::Fail;
5063 // addr
5064 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5065 return MCDisassembler::Fail;
5066
5067 return S;
5068 }
5069
DecodeT2Adr(MCInst & Inst,uint32_t Insn,uint64_t Address,const void * Decoder)5070 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
5071 uint64_t Address, const void *Decoder) {
5072 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
5073 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
5074 if (sign1 != sign2) return MCDisassembler::Fail;
5075
5076 unsigned Val = fieldFromInstruction(Insn, 0, 8);
5077 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
5078 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
5079 Val |= sign1 << 12;
5080 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val)));
5081
5082 return MCDisassembler::Success;
5083 }
5084
DecodeT2ShifterImmOperand(MCInst & Inst,uint32_t Val,uint64_t Address,const void * Decoder)5085 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
5086 uint64_t Address,
5087 const void *Decoder) {
5088 DecodeStatus S = MCDisassembler::Success;
5089
5090 // Shift of "asr #32" is not allowed in Thumb2 mode.
5091 if (Val == 0x20) S = MCDisassembler::Fail;
5092 Inst.addOperand(MCOperand::createImm(Val));
5093 return S;
5094 }
5095
DecodeSwap(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)5096 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
5097 uint64_t Address, const void *Decoder) {
5098 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5099 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
5100 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5101 unsigned pred = fieldFromInstruction(Insn, 28, 4);
5102
5103 if (pred == 0xF)
5104 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
5105
5106 DecodeStatus S = MCDisassembler::Success;
5107
5108 if (Rt == Rn || Rn == Rt2)
5109 S = MCDisassembler::SoftFail;
5110
5111 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5112 return MCDisassembler::Fail;
5113 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5114 return MCDisassembler::Fail;
5115 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5116 return MCDisassembler::Fail;
5117 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5118 return MCDisassembler::Fail;
5119
5120 return S;
5121 }
5122
DecodeVCVTD(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)5123 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
5124 uint64_t Address, const void *Decoder) {
5125 const FeatureBitset &featureBits =
5126 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5127 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5128
5129 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5130 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5131 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5132 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5133 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5134 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5135 unsigned op = fieldFromInstruction(Insn, 5, 1);
5136
5137 DecodeStatus S = MCDisassembler::Success;
5138
5139 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5140 if (!(imm & 0x38)) {
5141 if (cmode == 0xF) {
5142 if (op == 1) return MCDisassembler::Fail;
5143 Inst.setOpcode(ARM::VMOVv2f32);
5144 }
5145 if (hasFullFP16) {
5146 if (cmode == 0xE) {
5147 if (op == 1) {
5148 Inst.setOpcode(ARM::VMOVv1i64);
5149 } else {
5150 Inst.setOpcode(ARM::VMOVv8i8);
5151 }
5152 }
5153 if (cmode == 0xD) {
5154 if (op == 1) {
5155 Inst.setOpcode(ARM::VMVNv2i32);
5156 } else {
5157 Inst.setOpcode(ARM::VMOVv2i32);
5158 }
5159 }
5160 if (cmode == 0xC) {
5161 if (op == 1) {
5162 Inst.setOpcode(ARM::VMVNv2i32);
5163 } else {
5164 Inst.setOpcode(ARM::VMOVv2i32);
5165 }
5166 }
5167 }
5168 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5169 }
5170
5171 if (!(imm & 0x20)) return MCDisassembler::Fail;
5172
5173 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
5174 return MCDisassembler::Fail;
5175 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5176 return MCDisassembler::Fail;
5177 Inst.addOperand(MCOperand::createImm(64 - imm));
5178
5179 return S;
5180 }
5181
DecodeVCVTQ(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)5182 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
5183 uint64_t Address, const void *Decoder) {
5184 const FeatureBitset &featureBits =
5185 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5186 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5187
5188 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5189 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5190 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5191 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5192 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5193 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5194 unsigned op = fieldFromInstruction(Insn, 5, 1);
5195
5196 DecodeStatus S = MCDisassembler::Success;
5197
5198 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5199 if (!(imm & 0x38)) {
5200 if (cmode == 0xF) {
5201 if (op == 1) return MCDisassembler::Fail;
5202 Inst.setOpcode(ARM::VMOVv4f32);
5203 }
5204 if (hasFullFP16) {
5205 if (cmode == 0xE) {
5206 if (op == 1) {
5207 Inst.setOpcode(ARM::VMOVv2i64);
5208 } else {
5209 Inst.setOpcode(ARM::VMOVv16i8);
5210 }
5211 }
5212 if (cmode == 0xD) {
5213 if (op == 1) {
5214 Inst.setOpcode(ARM::VMVNv4i32);
5215 } else {
5216 Inst.setOpcode(ARM::VMOVv4i32);
5217 }
5218 }
5219 if (cmode == 0xC) {
5220 if (op == 1) {
5221 Inst.setOpcode(ARM::VMVNv4i32);
5222 } else {
5223 Inst.setOpcode(ARM::VMOVv4i32);
5224 }
5225 }
5226 }
5227 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5228 }
5229
5230 if (!(imm & 0x20)) return MCDisassembler::Fail;
5231
5232 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
5233 return MCDisassembler::Fail;
5234 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
5235 return MCDisassembler::Fail;
5236 Inst.addOperand(MCOperand::createImm(64 - imm));
5237
5238 return S;
5239 }
5240
DecodeLDR(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)5241 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
5242 uint64_t Address, const void *Decoder) {
5243 DecodeStatus S = MCDisassembler::Success;
5244
5245 unsigned Rn = fieldFromInstruction(Val, 16, 4);
5246 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5247 unsigned Rm = fieldFromInstruction(Val, 0, 4);
5248 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
5249 unsigned Cond = fieldFromInstruction(Val, 28, 4);
5250
5251 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
5252 S = MCDisassembler::SoftFail;
5253
5254 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5255 return MCDisassembler::Fail;
5256 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5257 return MCDisassembler::Fail;
5258 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
5259 return MCDisassembler::Fail;
5260 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
5261 return MCDisassembler::Fail;
5262 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
5263 return MCDisassembler::Fail;
5264
5265 return S;
5266 }
5267
DecoderForMRRC2AndMCRR2(llvm::MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)5268 static DecodeStatus DecoderForMRRC2AndMCRR2(llvm::MCInst &Inst, unsigned Val,
5269 uint64_t Address, const void *Decoder) {
5270
5271 DecodeStatus S = MCDisassembler::Success;
5272
5273 unsigned CRm = fieldFromInstruction(Val, 0, 4);
5274 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
5275 unsigned cop = fieldFromInstruction(Val, 8, 4);
5276 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5277 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
5278
5279 if ((cop & ~0x1) == 0xa)
5280 return MCDisassembler::Fail;
5281
5282 if (Rt == Rt2)
5283 S = MCDisassembler::SoftFail;
5284
5285 // We have to check if the instruction is MRRC2
5286 // or MCRR2 when constructing the operands for
5287 // Inst. Reason is because MRRC2 stores to two
5288 // registers so it's tablegen desc has has two
5289 // outputs whereas MCRR doesn't store to any
5290 // registers so all of it's operands are listed
5291 // as inputs, therefore the operand order for
5292 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
5293 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]
5294
5295 if (Inst.getOpcode() == ARM::MRRC2) {
5296 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5297 return MCDisassembler::Fail;
5298 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5299 return MCDisassembler::Fail;
5300 }
5301 Inst.addOperand(MCOperand::createImm(cop));
5302 Inst.addOperand(MCOperand::createImm(opc1));
5303 if (Inst.getOpcode() == ARM::MCRR2) {
5304 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5305 return MCDisassembler::Fail;
5306 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5307 return MCDisassembler::Fail;
5308 }
5309 Inst.addOperand(MCOperand::createImm(CRm));
5310
5311 return S;
5312 }
5313
5314