/art/runtime/interpreter/mterp/arm/ |
D | op_shl_long_2addr.S | 12 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 13 mov r1, r1, asl r2 @ r1<- r1 << r2 15 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 18 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 21 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
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D | op_mul_long_2addr.S | 10 mov r1, rINST, lsr #12 @ r1<- B 12 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] 14 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 15 ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1 16 mul ip, r2, r1 @ ip<- ZxW 17 umull r1, lr, r2, r0 @ r1/lr <- ZxX 23 stmia r0, {r1-r2} @ vAA/vAA+1<- r1/r2
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D | op_shl_long.S | 14 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 18 mov r1, r1, asl r2 @ r1<- r1 << r2 20 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 22 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 26 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
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D | op_rem_int_lit16.S | 14 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) 18 cmp r1, #0 @ is second operand zero? 23 sdiv r2, r0, r1 24 mls r1, r1, r2, r0 @ r1<- op 26 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 29 SET_VREG r1, r9 @ vAA<- r1
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D | op_rem_int_2addr.S | 16 GET_VREG r1, r3 @ r1<- vB 18 cmp r1, #0 @ is second operand zero? 23 sdiv r2, r0, r1 24 mls r1, r1, r2, r0 @ r1<- op 26 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 29 SET_VREG r1, r9 @ vAA<- r1
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D | op_shr_long_2addr.S | 12 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 15 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 18 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 19 mov r1, r1, asr r2 @ r1<- r1 >> r2 21 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
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D | op_ushr_long_2addr.S | 12 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 15 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 18 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 19 mov r1, r1, lsr r2 @ r1<- r1 >>> r2 21 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
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D | op_rem_int.S | 18 GET_VREG r1, r3 @ r1<- vCC 20 cmp r1, #0 @ is second operand zero? 25 sdiv r2, r0, r1 26 mls r1, r1, r2, r0 @ r1<- op, r0-r2 changed 28 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 31 SET_VREG r1, r9 @ vAA<- r1
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D | op_rem_int_lit8.S | 18 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 19 @cmp r1, #0 @ is second operand zero? 24 sdiv r2, r0, r1 25 mls r1, r1, r2, r0 @ r1<- op 27 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 30 SET_VREG r1, r9 @ vAA<- r1
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D | op_shr_long.S | 14 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 20 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 22 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 24 mov r1, r1, asr r2 @ r1<- r1 >> r2 26 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
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D | op_ushr_long.S | 14 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 20 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 22 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 24 mov r1, r1, lsr r2 @ r1<- r1 >>> r2 26 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
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D | op_fill_array_data.S | 4 FETCH r1, 2 @ r1<- BBBB (hi) 6 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 8 add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.)
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D | op_double_to_long.S | 12 ubfx r2, r1, #20, #11 @ grab the exponent 22 adds r1, r1, r1 @ sign bit to carry 24 mov r1, #0x7fffffff @ assume maxlong for msw 26 adc r1, r1, #0 @ convert maxlong to minlong if exp negative 29 orrs r3, r0, r1, lsl #12
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D | op_const_wide_high16.S | 2 FETCH r1, 1 @ r1<- 0000BBBB (zero-extended) 5 mov r1, r1, lsl #16 @ r1<- BBBB0000 10 stmia r3, {r0-r1} @ vAA<- r0/r1
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D | op_instance_of.S | 10 mov r1, rINST, lsr #12 @ r1<- B 11 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &object 15 ldr r1, [rSELF, #THREAD_EXCEPTION_OFFSET] 18 cmp r1, #0 @ exception pending?
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D | binopWide2addr.S | 17 mov r1, rINST, lsr #12 @ r1<- B 19 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] 21 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 22 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
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D | op_const_wide.S | 3 FETCH r1, 2 @ r1<- BBBB (low middle) 5 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word) 8 orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) 13 stmia r9, {r0-r1} @ vAA<- r0/r1
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D | op_iget_wide.S | 8 mov r1, rINST, lsr #12 @ r1<- B 9 GET_VREG r1, r1 @ r1<- fp[B], the object pointer 20 stmia r3, {r0-r1} @ fp[A]<- r0/r1
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D | footer.S | 19 add r1, rFP, #OFF_FP_SHADOWFRAME 28 add r1, rFP, #OFF_FP_SHADOWFRAME 37 add r1, rFP, #OFF_FP_SHADOWFRAME 46 add r1, rFP, #OFF_FP_SHADOWFRAME 55 add r1, rFP, #OFF_FP_SHADOWFRAME 64 add r1, rFP, #OFF_FP_SHADOWFRAME 73 add r1, rFP, #OFF_FP_SHADOWFRAME 96 add r1, rFP, #OFF_FP_SHADOWFRAME 101 ldr r1, [rFP, #OFF_FP_DEX_PC] 103 add rPC, r0, r1, lsl #1 @ generate new dex_pc_ptr [all …]
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D | op_packed_switch.S | 13 FETCH r1, 2 @ r1<- BBBB (hi) 15 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 16 GET_VREG r1, r3 @ r1<- vAA
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D | op_mul_long.S | 25 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 27 mul ip, r2, r1 @ ip<- ZxW 28 umull r1, lr, r2, r0 @ r1/lr <- ZxX 35 stmia r0, {r1-r2 } @ vAA/vAA+1<- r1/r2
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D | op_check_cast.S | 7 mov r1, rINST, lsr #8 @ r1<- AA 8 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &object
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D | op_sput_wide.S | 9 mov r1, rINST, lsr #8 @ r1<- AA 10 VREG_INDEX_TO_ADDR r1, r1
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D | op_iput.S | 11 mov r1, rINST, lsr #12 @ r1<- B 12 GET_VREG r1, r1 @ r1<- fp[B], the object pointer
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/art/runtime/arch/arm/ |
D | memcmp16_arm.S | 33 pld [r1, #0] 36 cmp r0, r1 56 pld [r1, #32] 59 ldrh ip, [r1], #2 78 ldrh ip, [r1], #2 91 eor r0, r3, r1 101 ldr ip, [r1] 107 pld [r1, #64] 109 ldr lr, [r1, #4]! 112 ldreq ip, [r1, #4]! [all …]
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