| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZInstrFP.td | 29 def SelectF32 : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, i8imm:$cc),
33 def SelectF64 : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, i8imm:$cc),
44 def LD_Fp032 : Pseudo<(outs FP32:$dst), (ins),
47 def LD_Fp064 : Pseudo<(outs FP64:$dst), (ins),
53 def FMOV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
56 def FMOV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
62 def FMOV32rm : Pseudo<(outs FP32:$dst), (ins rriaddr12:$src),
65 def FMOV32rmy : Pseudo<(outs FP32:$dst), (ins rriaddr:$src),
68 def FMOV64rm : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src),
71 def FMOV64rmy : Pseudo<(outs FP64:$dst), (ins rriaddr:$src),
[all …]
|
| D | SystemZInstrInfo.td | 71 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
74 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
79 def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc),
83 def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc),
96 def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>;
101 def JMP : Pseudo<(outs), (ins brtarget:$dst), "j\t{$dst}", [(br bb:$dst)]>;
104 def JMPr : Pseudo<(outs), (ins GR64:$dst), "br\t{$dst}", [(brind GR64:$dst)]>;
108 def JO : Pseudo<(outs), (ins brtarget:$dst),
111 def JH : Pseudo<(outs), (ins brtarget:$dst),
114 def JNLE: Pseudo<(outs), (ins brtarget:$dst),
[all …]
|
| D | SystemZInstrFormats.td | 17 def Pseudo : Format<0>;
125 // Pseudo instructions
128 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
129 : InstSystemZ<0, Pseudo, outs, ins> {
|
| /external/llvm/test/Analysis/BlockFrequencyInfo/ |
| D | double_exit.ll | 16 ; Pseudo-edges = exit
17 ; Pseudo-mass = 1
29 ; Pseudo-edges = outer.inc @ 1/5, exit @ 1/5
30 ; Pseudo-mass = 2/3
89 ; Pseudo-edges = exit
90 ; Pseudo-mass = 1
102 ; Pseudo-edges = outer.inc
103 ; Pseudo-mass = 1/2
115 ; Pseudo-edges = middle.inc @ 1/5, outer.inc @ 1/5
116 ; Pseudo-mass = 2/3
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrCompiler.td | 30 // Random Pseudo Instructions.
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
62 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
66 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
76 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
89 def VAARG_64 : I<0, Pseudo,
106 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
116 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
[all …]
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrCompiler.td | 30 // Random Pseudo Instructions.
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
65 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
69 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
80 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
94 def VAARG_64 : I<0, Pseudo,
109 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
116 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
[all …]
|
| /external/llvm/lib/Target/AVR/ |
| D | AVRInstrInfo.td | 64 // Pseudo shift nodes for non-constant shift amounts.
301 def ADJCALLSTACKDOWN : Pseudo<(outs),
311 def ADJCALLSTACKUP : Pseudo<(outs),
335 // Pseudo instruction to add four 8-bit registers as two 16-bit values.
340 def ADDWRdRr : Pseudo<(outs DREGS:$rd),
358 // Pseudo instruction to add four 8-bit registers as two 16-bit values with
365 def ADCWRdRr : Pseudo<(outs DREGS:$rd),
404 def SUBWRdRr : Pseudo<(outs DREGS:$rd),
422 def SUBIWRdK : Pseudo<(outs DLDREGS:$rd),
452 def SBCWRdRr : Pseudo<(outs DREGS:$rd),
[all …]
|
| D | AVRInstrFormats.td | 51 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
551 : Pseudo<outs, ins, asmstr, pattern>
557 : Pseudo<outs, ins, asmstr, pattern>
563 : Pseudo<outs, ins, asmstr, pattern>
571 : Pseudo<outs, ins, asmstr, pattern>
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ValueTypes.td | 65 // Pseudo valuetype mapped to the current pointer size to any address space.
69 // Pseudo valuetype to represent "vector of any size"
72 // Pseudo valuetype to represent "float of any format"
75 // Pseudo valuetype to represent "integer of any bit width"
78 // Pseudo valuetype mapped to the current pointer size.
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.td | 102 // Pseudo valuetype mapped to the current pointer size to any address space.
106 // Pseudo valuetype to represent "vector of any size"
109 // Pseudo valuetype to represent "float of any format"
112 // Pseudo valuetype to represent "integer of any bit width"
115 // Pseudo valuetype mapped to the current pointer size.
118 // Pseudo valuetype to represent "any type of any size".
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstr64Bit.td | 107 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
209 def ATOMIC_LOAD_ADD_I64 : Pseudo<
212 def ATOMIC_LOAD_SUB_I64 : Pseudo<
215 def ATOMIC_LOAD_OR_I64 : Pseudo<
218 def ATOMIC_LOAD_XOR_I64 : Pseudo<
221 def ATOMIC_LOAD_AND_I64 : Pseudo<
224 def ATOMIC_LOAD_NAND_I64 : Pseudo<
228 def ATOMIC_CMP_SWAP_I64 : Pseudo<
232 def ATOMIC_SWAP_I64 : Pseudo<
265 def TCRETURNdi8 :Pseudo< (outs),
[all …]
|
| D | PPCInstrInfo.td | 1063 // Pseudo-instructions:
1067 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
1069 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt…
1073 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
1078 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
1081 def DYNAREAOFFSET : Pseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET",
1091 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
1095 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
1099 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
1102 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 360 // Pseudo-instructions:
364 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "",
366 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "",
370 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
375 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "",
383 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
386 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
389 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
392 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
395 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
[all …]
|
| D | PPCInstr64Bit.td | 63 def MovePCtoLR8 : Pseudo<(outs), (ins), "", []>,
134 def ATOMIC_LOAD_ADD_I64 : Pseudo<
137 def ATOMIC_LOAD_SUB_I64 : Pseudo<
140 def ATOMIC_LOAD_OR_I64 : Pseudo<
143 def ATOMIC_LOAD_XOR_I64 : Pseudo<
146 def ATOMIC_LOAD_AND_I64 : Pseudo<
149 def ATOMIC_LOAD_NAND_I64 : Pseudo<
153 def ATOMIC_CMP_SWAP_I64 : Pseudo<
158 def ATOMIC_SWAP_I64 : Pseudo<
176 def TCRETURNdi8 :Pseudo< (outs),
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | SparcInstrInfo.td | 207 // Pseudo instructions.
208 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
213 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
217 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
220 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
242 def FpMOVD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
244 def FpNEGD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
247 def FpABSD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
258 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
263 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
[all …]
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFInstrFormats.td | 28 // Pseudo instructions
29 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinInstrInfo.td | 132 // Pseudo instructions.
133 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
137 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
140 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
203 // Pseudo-instruction for loading a general 32-bit constant.
204 def LOAD32imm: Pseudo<(outs GR:$dst), (ins i32imm:$src),
208 def LOAD32sym: Pseudo<(outs GR:$dst), (ins i32imm:$src),
234 // Pseudo-instruction for loading a stack slot
235 def LOAD32fi: Pseudo<(outs DP:$dst), (ins MEMii:$mem),
240 def LOAD16fi: Pseudo<(outs D16:$dst), (ins MEMii:$mem),
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsInstrInfo.td | 349 Operand MemOpnd, bit Pseudo>:
353 let isPseudo = Pseudo;
357 Operand MemOpnd, bit Pseudo>:
361 let isPseudo = Pseudo;
366 bit Pseudo = 0> {
367 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
369 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
375 bit Pseudo = 0> {
376 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
378 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
[all …]
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 328 // Pseudo-registers representing odd-even pairs of D registers. The even-odd
346 // Pseudo-registers representing even-odd pairs of GPRs from R1 to R13/SP.
357 // Pseudo-registers representing 3 consecutive D registers.
368 // Pseudo 256-bit registers to represent pairs of Q registers. These should
373 // Pseudo 256-bit vector register class to model pairs of Q registers
392 // Pseudo 512-bit registers to represent four consecutive Q registers.
396 // Pseudo 512-bit vector register class to model 4 consecutive Q registers
405 // Pseudo-registers representing 2-spaced consecutive D registers.
|
| D | ARMScheduleSwift.td | 160 // Pseudo instructions.
885 (instregex "VLD2(d|q|b)(8|16|32)$", "VLD2q(8|16|32)Pseudo$")>;
921 (instregex "VLD1(LN|DUP)(d|q)(8|16|32)$", "VLD1(LN|DUP)(d|q)(8|16|32)Pseudo$")>;
928 "VLD2LN(d|q)(8|16|32)Pseudo$")>;
942 "VLD3(LN|DUP)(d|q)(8|16|32)Pseudo$")>;
953 "VLD4(LN|DUP)(d|q)(8|16|32)Pseudo$")>;
985 (instregex "VST2q(8|16|32)$", "VST2q(8|16|32)Pseudo$")>;
1003 (instregex "VST1LNd(8|16|32)$", "VST1LNq(8|16|32)Pseudo$")>;
1008 (instregex "VST2LN(d|q)(8|16|32)$", "VST2LN(d|q)(8|16|32)Pseudo$")>;
1014 (instregex "VST3LN(d|q)(8|16|32)$", "VST3LN(d|q)(8|16|32)Pseudo$")>;
[all …]
|
| /external/python/cpython2/Doc/library/ |
| D | pty.rst | 2 :mod:`pty` --- Pseudo-terminal utilities
7 :synopsis: Pseudo-Terminal Handling for Linux.
|
| /external/squashfs-tools/RELEASE-READMEs/ |
| D | README-4.1 | 147 Pseudo operations
153 Pseudo definition
210 Pseudo definition
234 Pseudo definition
251 Pseudo definition
|
| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| D | MCInstrDesc.h | 100 Pseudo, enumerator
283 return Flags & (1 << MCID::Pseudo); in isPseudo()
|
| /external/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 100 Pseudo, enumerator
208 bool isPseudo() const { return Flags & (1 << MCID::Pseudo); } in isPseudo()
|
| /external/python/cpython3/Doc/library/ |
| D | pty.rst | 1 :mod:`pty` --- Pseudo-terminal utilities
6 :synopsis: Pseudo-Terminal Handling for Linux.
|