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Searched refs:b11 (Results 1 – 25 of 86) sorted by relevance

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/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td317 def : ROSysReg<"PMCEID0_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b110>;
318 def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>;
319 def : ROSysReg<"MIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b000>;
320 def : ROSysReg<"CCSIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b000>;
321 def : ROSysReg<"CLIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b001>;
322 def : ROSysReg<"CTR_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b001>;
323 def : ROSysReg<"MPIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b101>;
324 def : ROSysReg<"REVIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b110>;
325 def : ROSysReg<"AIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b111>;
326 def : ROSysReg<"DCZID_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b111>;
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DAArch64InstrFormats.td1782 let Inst{14-13} = 0b11;
1856 let Inst{14-13} = 0b11;
3117 let Inst{11-10} = 0b11;
3569 def UWHr : BaseFPToIntegerUnscaled<0b11, rmode, opcode, FPR16, GPR32, asm,
3576 def UXHr : BaseFPToIntegerUnscaled<0b11, rmode, opcode, FPR16, GPR64, asm,
3610 def SWHri : BaseFPToInteger<0b11, rmode, opcode, FPR16, GPR32,
3620 def SXHri : BaseFPToInteger<0b11, rmode, opcode, FPR16, GPR64,
3706 let Inst{23-22} = 0b11; // 16-bit FPR flag
3722 let Inst{23-22} = 0b11; // 16-bit FPR flag
3742 let Inst{23-22} = 0b11; // 16-bit FPR flag
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DAArch64InstrInfo.td442 defm MOVK : InsertImmediate<0b11, "movk">;
705 defm RORV : Shift<0b11, "ror", rotr>;
804 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_aarch64_crc32x, "crc32x">;
809 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">;
885 defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">;
900 defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;
901 defm BICS : LogicalRegS<0b11, 1, "bics",
1278 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
1281 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
1336 defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>;
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrVFP.td200 def VADDD : ADbI<0b11100, 0b11, 0, 0,
205 def VADDS : ASbIn<0b11100, 0b11, 0, 0,
214 def VSUBD : ADbI<0b11100, 0b11, 1, 0,
219 def VSUBS : ASbIn<0b11100, 0b11, 1, 0,
274 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,
279 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
289 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
294 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
308 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
313 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
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DARMInstrNEON.td1881 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
1887 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
2670 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
2673 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
2778 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
2781 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2792 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
2795 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3670 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
3683 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
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/external/llvm/lib/Target/ARM/
DARMInstrVFP.td336 def VADDD : ADbI<0b11100, 0b11, 0, 0,
342 def VADDS : ASbIn<0b11100, 0b11, 0, 0,
352 def VADDH : AHbI<0b11100, 0b11, 0, 0,
358 def VSUBD : ADbI<0b11100, 0b11, 1, 0,
364 def VSUBS : ASbIn<0b11100, 0b11, 1, 0,
374 def VSUBH : AHbI<0b11100, 0b11, 1, 0,
462 defm VSELGT : vsel_inst<"gt", 0b11, 12>;
501 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,
506 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
515 def VCMPEH : AHuI<0b11101, 0b11, 0b0100, 0b11, 0,
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DARMInstrNEON.td2534 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
2540 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
3408 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
3411 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
3516 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
3519 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3530 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
3533 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
4536 def VMLShd : N3VDMulOp<0, 0, 0b11, 0b1101, 1, IIC_VMACD, "vmls", "f16",
4539 def VMLShq : N3VQMulOp<0, 0, 0b11, 0b1101, 1, IIC_VMACQ, "vmls", "f16",
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/external/skia/src/core/
DSkMatrix44.cpp465 double b11 = a22 * a33 - a23 * a32; in determinant() local
468 return b00 * b11 - b01 * b10 + b02 * b09 + b03 * b08 - b04 * b07 + b05 * b06; in determinant()
577 double b11 = a22; in invert() local
580 double det = b00 * b11 - b01 * b10 + b03 * b08; in invert()
598 b11 *= invdet; in invert()
600 inverse->fMat[0][0] = SkDoubleToMScalar(a11 * b11 - a12 * b10); in invert()
601 inverse->fMat[0][1] = SkDoubleToMScalar(a02 * b10 - a01 * b11); in invert()
604 inverse->fMat[1][0] = SkDoubleToMScalar(a12 * b08 - a10 * b11); in invert()
605 inverse->fMat[1][1] = SkDoubleToMScalar(a00 * b11 - a02 * b08); in invert()
638 double b11 = a22 * a33 - a23 * a32; in invert() local
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/external/skqp/src/core/
DSkMatrix44.cpp465 double b11 = a22 * a33 - a23 * a32; in determinant() local
468 return b00 * b11 - b01 * b10 + b02 * b09 + b03 * b08 - b04 * b07 + b05 * b06; in determinant()
577 double b11 = a22; in invert() local
580 double det = b00 * b11 - b01 * b10 + b03 * b08; in invert()
598 b11 *= invdet; in invert()
600 inverse->fMat[0][0] = SkDoubleToMScalar(a11 * b11 - a12 * b10); in invert()
601 inverse->fMat[0][1] = SkDoubleToMScalar(a02 * b10 - a01 * b11); in invert()
604 inverse->fMat[1][0] = SkDoubleToMScalar(a12 * b08 - a10 * b11); in invert()
605 inverse->fMat[1][1] = SkDoubleToMScalar(a00 * b11 - a02 * b08); in invert()
638 double b11 = a22 * a33 - a23 * a32; in invert() local
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/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td400 class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>;
405 class ADDS_A_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010000>;
410 class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>;
415 class ADDS_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010000>;
420 class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>;
425 class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>;
434 class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>;
439 class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>;
444 class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>;
449 class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>;
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/external/eigen/Eigen/src/Eigenvalues/
DRealQZ.h460 b11 = m_T.coeff(f,f), b12 = m_T.coeff(f,f+1), in step() local
466 …x = ( (a88/b88 - a11/b11)*(a99/b99 - a11/b11) - (a89/b99)*(a98/b88) + (a98/b88)*(b89/b99)*(a11/b11… in step()
467 + a12/b22 - (a11/b11)*(b12/b22); in step()
468 …y = (a22/b22-a11/b11) - (a21/b11)*(b12/b22) - (a88/b88-a11/b11) - (a99/b99-a11/b11) + (a98/b88)*(b… in step()
/external/clang/test/Modules/Inputs/PR27513/
Dmodule.modulemap5 module "b11.h" { header "b11.h" export *}
/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-armv7.txt442 # VST1 multi-element, type == 0b0111, align == 0b11 -> undefined
447 # VST1 multi-element, type == 0b1010, align == 0b11 -> undefined
457 # VST1 multi-element, type == 0b0110, align == 0b11 -> undefined
462 # VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
467 # VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
472 # VST3 multi-element, size = 0b11 -> undefined
482 # VST3 multi-element, align = 0b11 -> undefined
487 # VST4 multi-element, size = 0b11 -> undefined
Dinvalid-thumbv7.txt278 # VLD1 multi-element, type=0b1010 align=0b11
293 # VLD2 multi-element size=0b11
298 # VLD2 multi-element type=0b1111 align=0b11
303 # VLD2 multi-element type=0b1001 align=0b11
308 # VLD3 multi-element size=0b11
318 # VLD4 multi-element size=0b11
/external/libvpx/libvpx/vp8/encoder/x86/
Dfwalsh_sse2.asm81 pmaddwd xmm2, [GLOBAL(cn1)] ; c11 b11 c10 b10
87 pshufd xmm5, xmm2, 0xd8 ; c11 c10 b11 b10
92 punpcklqdq xmm0, xmm5 ; b11 b10 a11 a10
/external/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-undefined.txt27 # Only unallocated (int-register) variants are: opc=0b11, size=0b10, 0b11
/external/boringssl/src/ssl/test/runner/ed25519/internal/edwards25519/
Dedwards25519.go1048 b11 := (load4(b[28:]) >> 7)
1074 …s11 := c11 + a0*b11 + a1*b10 + a2*b9 + a3*b8 + a4*b7 + a5*b6 + a6*b5 + a7*b4 + a8*b3 + a9*b2 + a10…
1075 s12 := a1*b11 + a2*b10 + a3*b9 + a4*b8 + a5*b7 + a6*b6 + a7*b5 + a8*b4 + a9*b3 + a10*b2 + a11*b1
1076 s13 := a2*b11 + a3*b10 + a4*b9 + a5*b8 + a6*b7 + a7*b6 + a8*b5 + a9*b4 + a10*b3 + a11*b2
1077 s14 := a3*b11 + a4*b10 + a5*b9 + a6*b8 + a7*b7 + a8*b6 + a9*b5 + a10*b4 + a11*b3
1078 s15 := a4*b11 + a5*b10 + a6*b9 + a7*b8 + a8*b7 + a9*b6 + a10*b5 + a11*b4
1079 s16 := a5*b11 + a6*b10 + a7*b9 + a8*b8 + a9*b7 + a10*b6 + a11*b5
1080 s17 := a6*b11 + a7*b10 + a8*b9 + a9*b8 + a10*b7 + a11*b6
1081 s18 := a7*b11 + a8*b10 + a9*b9 + a10*b8 + a11*b7
1082 s19 := a8*b11 + a9*b10 + a10*b9 + a11*b8
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/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.td279 def C2_cmpgtu : T_ALU32_3op_cmp< "cmp.gtu", 0b11, 0, 0>;
1090 def A2_subh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 1>;
1096 def A2_addh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 0>;
1103 def A2_subh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 1>;
1109 def A2_addh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 0>;
2344 def M2_mpy_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 0>;
2345 def M2_mpy_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 0>;
2354 def M2_mpyu_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 1>;
2355 def M2_mpyu_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 1>;
2364 def M2_mpy_rnd_hh_s1: T_M2_mpy <0b11, 0, 1, 1, 0>;
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/external/clang/test/SemaCXX/
Duninitialized.cpp469 B* b11 = 0; in setupB() local
470 B* b12(b11); in setupB()
504 B* b11 = 0; variable
505 B* b12(b11);
1167 B b11 = { {0, b11.a1.i2} }; // expected-warning{{uninitialized}} variable
1225 B b11 = { {0, b11.a1.i2} }; // expected-warning{{uninitialized}} member
1254 b11{ {0, b11.a1.i2} }, // expected-warning{{uninitialized}}
/external/eigen/Eigen/src/SparseLU/
DSparseLU_gemm_kernel.h74 Packet b00, b10, b20, b30, b01, b11, b21, b31; in sparselu_gemm() local
80 { b11 = pset1<Packet>(Bc1[1]); } in sparselu_gemm()
115 KMADD(c1, a1, b11, t1) \ in sparselu_gemm()
/external/llvm/test/MC/Disassembler/SystemZ/
Dtrunc-03.txt2 # If the top bits are 0b11, the instruction must be 6 bytes long.
/external/Microsoft-GSL/tests/
Dbounds_tests.cpp83 static_bounds<dynamic_range> b11; variable
/external/capstone/suite/MC/AArch64/
Dneon-scalar-shift-imm.s.cs11 0x6b,0x76,0x0f,0x5f = sqshl b11, b19, #7
/external/llvm/test/MC/AArch64/
Dneon-scalar-shift-imm.s71 sqshl b11, b19, #7
/external/clang/test/CodeGenCXX/
Dmangle-ms-return-qualifiers.cpp51 const char** b11() { return 0; } in b11() function

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