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Searched refs:enabled_mask (Results 1 – 25 of 27) sorted by relevance

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/external/mesa3d/src/gallium/drivers/radeon/
Dr600_streamout.c80 unsigned num_bufs = util_bitcount(rctx->streamout.enabled_mask); in r600_streamout_buffers_dirty()
81 unsigned num_bufs_appended = util_bitcount(rctx->streamout.enabled_mask & in r600_streamout_buffers_dirty()
119 unsigned enabled_mask = 0, append_bitmask = 0; in r600_set_streamout_targets() local
133 enabled_mask |= 1 << i; in r600_set_streamout_targets()
141 rctx->streamout.enabled_mask = enabled_mask; in r600_set_streamout_targets()
345 rctx->streamout.hw_enabled_mask = rctx->streamout.enabled_mask | in r600_set_streamout_enable()
346 (rctx->streamout.enabled_mask << 4) | in r600_set_streamout_enable()
347 (rctx->streamout.enabled_mask << 8) | in r600_set_streamout_enable()
348 (rctx->streamout.enabled_mask << 12); in r600_set_streamout_enable()
Dr600_pipe_common.h471 unsigned enabled_mask; member
Dr600_pipe_common.c336 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask; in r600_postflush_resume_features()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_descriptors.c343 unsigned mask = views->enabled_mask; in si_sampler_views_begin_new_cs()
469 views->enabled_mask |= 1u << slot; in si_set_sampler_view()
486 views->enabled_mask &= ~(1u << slot); in si_set_sampler_view()
569 unsigned mask = samplers->views.enabled_mask; in si_samplers_update_compressed_colortex_mask()
617 uint mask = images->enabled_mask; in si_image_views_begin_new_cs()
636 if (images->enabled_mask & (1u << slot)) { in si_disable_shader_image()
643 images->enabled_mask &= ~(1u << slot); in si_disable_shader_image()
753 images->enabled_mask |= 1u << slot; in si_set_shader_image()
792 unsigned mask = images->enabled_mask; in si_images_update_compressed_colortex_mask()
885 unsigned mask = buffers->enabled_mask; in si_buffer_resources_begin_new_cs()
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Dsi_state.h248 unsigned enabled_mask; member
257 unsigned enabled_mask; member
Dsi_pipe.h162 unsigned enabled_mask; member
Dsi_blit.c530 uint32_t mask = textures->views.enabled_mask; in si_check_render_feedback_textures()
571 uint32_t mask = images->enabled_mask; in si_check_render_feedback_images()
/external/mesa3d/src/gallium/drivers/freedreno/a2xx/
Dfd2_emit.c57 uint32_t enabled_mask = constbuf->enabled_mask; in emit_constants() local
63 constbuf->dirty_mask = enabled_mask; in emit_constants()
66 while (enabled_mask) { in emit_constants()
67 unsigned index = ffs(enabled_mask) - 1; in emit_constants()
103 enabled_mask &= ~(1 << index); in emit_constants()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_state_common.c456 dst->states.enabled_mask &= ~disable_mask; in r600_bind_sampler_states()
457 dst->states.dirty_mask &= dst->states.enabled_mask; in r600_bind_sampler_states()
458 dst->states.enabled_mask |= new_mask; in r600_bind_sampler_states()
460 dst->states.has_bordercolor_mask &= dst->states.enabled_mask; in r600_bind_sampler_states()
582 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask; in r600_set_vertex_buffers()
583 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask; in r600_set_vertex_buffers()
584 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask; in r600_set_vertex_buffers()
625 remaining_mask = dst->views.enabled_mask & disable_mask; in r600_set_sampler_views()
660 (dst->states.enabled_mask & (1 << i)) && in r600_set_sampler_views()
675 dst->views.enabled_mask &= ~disable_mask; in r600_set_sampler_views()
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Dr600_hw_context.c350 ctx->vertex_buffer_state.dirty_mask = ctx->vertex_buffer_state.enabled_mask; in r600_begin_new_cs()
358 constbuf->dirty_mask = constbuf->enabled_mask; in r600_begin_new_cs()
359 samplers->views.dirty_mask = samplers->views.enabled_mask; in r600_begin_new_cs()
360 samplers->states.dirty_mask = samplers->states.enabled_mask; in r600_begin_new_cs()
Dr600_pipe.h352 uint32_t enabled_mask; member
362 uint32_t enabled_mask; member
386 uint32_t enabled_mask; member
394 uint32_t enabled_mask; /* non-NULL buffers */ member
Dr600_blit.c82 rctx->blitter, util_last_bit(rctx->samplers[PIPE_SHADER_FRAGMENT].states.enabled_mask), in r600_blitter_begin()
86 rctx->blitter, util_last_bit(rctx->samplers[PIPE_SHADER_FRAGMENT].views.enabled_mask), in r600_blitter_begin()
Devergreen_compute.c155 state->enabled_mask |= 1 << vb_index; in evergreen_cs_set_vertex_buffer()
/external/mesa3d/src/gallium/drivers/freedreno/
Dfreedreno_state.c104 so->enabled_mask &= ~(1 << index); in fd_set_constant_buffer()
109 so->enabled_mask |= 1 << index; in fd_set_constant_buffer()
223 util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, start_slot, count); in fd_set_vertex_buffers()
224 so->count = util_last_bit(so->enabled_mask); in fd_set_vertex_buffers()
Dfreedreno_context.h71 uint32_t enabled_mask; member
78 uint32_t enabled_mask; member
Dfreedreno_draw.c139 foreach_bit(i, ctx->constbuf[PIPE_SHADER_VERTEX].enabled_mask) in fd_draw_vbo()
141 foreach_bit(i, ctx->constbuf[PIPE_SHADER_FRAGMENT].enabled_mask) in fd_draw_vbo()
145 foreach_bit(i, ctx->vtx.vertexbuf.enabled_mask) { in fd_draw_vbo()
/external/mesa3d/src/gallium/drivers/ilo/
Dilo_state.h163 uint32_t enabled_mask; member
201 uint32_t enabled_mask; member
Dilo_state.c365 uint32_t upload_mask = cbuf->enabled_mask; in finalize_cbuf_state()
1573 cbuf->enabled_mask |= 1 << (index + i); in ilo_set_constant_buffer()
1579 cbuf->enabled_mask |= 1 << (index + i); in ilo_set_constant_buffer()
1585 cbuf->enabled_mask &= ~(1 << (index + i)); in ilo_set_constant_buffer()
1598 cbuf->enabled_mask &= ~(1 << (index + i)); in ilo_set_constant_buffer()
1907 &vec->vb.enabled_mask, buffers, start_slot, num_buffers); in ilo_set_vertex_buffers()
2414 if (vec->vb.enabled_mask & (1 << i)) in ilo_state_vector_cleanup()
2469 uint32_t vb_mask = vec->vb.enabled_mask; in ilo_state_vector_resource_renamed()
/external/mesa3d/src/gallium/drivers/vc4/
Dvc4_state.c297 util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, in vc4_set_vertex_buffers()
299 so->count = util_last_bit(so->enabled_mask); in vc4_set_vertex_buffers()
389 so->enabled_mask &= ~(1 << index); in vc4_set_constant_buffer()
399 so->enabled_mask |= 1 << index; in vc4_set_constant_buffer()
Dvc4_context.h193 uint32_t enabled_mask; member
200 uint32_t enabled_mask; member
/external/mesa3d/src/gallium/drivers/virgl/
Dvirgl_context.h48 uint32_t enabled_mask; member
Dvirgl_context.c107 uint32_t remaining_mask = tinfo->enabled_mask; in virgl_attach_res_sampler_views()
705 remaining_mask = tinfo->enabled_mask & disable_mask; in virgl_set_sampler_views()
729 tinfo->enabled_mask &= ~disable_mask; in virgl_set_sampler_views()
730 tinfo->enabled_mask |= new_mask; in virgl_set_sampler_views()
/external/mesa3d/src/gallium/drivers/etnaviv/
Detnaviv_context.h79 uint32_t enabled_mask; member
Detnaviv_state.c417 util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, start_slot, num_buffers); in etna_set_vertex_buffers()
418 so->count = util_last_bit(so->enabled_mask); in etna_set_vertex_buffers()
/external/mesa3d/src/gallium/drivers/freedreno/ir3/
Dir3_shader.c494 uint32_t dirty_mask = constbuf->enabled_mask; in emit_user_consts()
541 if ((constbuf->enabled_mask & (1 << index)) && cb->buffer) { in emit_ubos()

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