/external/llvm/lib/Target/AMDGPU/ |
D | SIFrameLowering.cpp | 106 unsigned FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1); in emitPrologue() 110 unsigned FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0); in emitPrologue() 227 unsigned Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1); in emitPrologue() 228 unsigned Rsrc23 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2_sub3); in emitPrologue() 230 unsigned Lo = TRI->getSubReg(PreloadedPrivateBufferReg, AMDGPU::sub0_sub1); in emitPrologue() 231 unsigned Hi = TRI->getSubReg(PreloadedPrivateBufferReg, AMDGPU::sub2_sub3); in emitPrologue() 240 unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0); in emitPrologue() 241 unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1); in emitPrologue() 242 unsigned Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2); in emitPrologue() 243 unsigned Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3); in emitPrologue()
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D | R600ExpandSpecialInstrs.cpp | 187 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg); in runOnMachineFunction() 287 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction() 288 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction() 293 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction() 294 Src0 = TRI.getSubReg(Src0, SubRegIndex0); in runOnMachineFunction() 302 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
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D | SIFoldOperands.cpp | 113 Old.substVirtReg(New->getReg(), New->getSubReg(), TRI); in updateOperand() 200 if (UseOp.isReg() && ((UseOp.getSubReg() && OpToFold.isReg()) || in foldOperand() 222 if (FoldRC->getSize() == 8 && UseOp.getSubReg()) { in foldOperand() 226 if (UseOp.getSubReg() == AMDGPU::sub0) { in foldOperand() 229 assert(UseOp.getSubReg() == AMDGPU::sub1); in foldOperand() 264 if (RSUse->getSubReg() != RegSeqDstSubReg) in foldOperand()
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D | SIInstrInfo.cpp | 490 get(Opcode), RI.getSubReg(DestReg, SubIdx)); in copyPhysReg() 492 Builder.addReg(RI.getSubReg(SrcReg, SubIdx)); in copyPhysReg() 858 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo() 859 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo() 875 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0)) in expandPostRAPseudo() 878 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1)) in expandPostRAPseudo() 887 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo() 888 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo() 894 .addReg(RI.getSubReg(Src0, AMDGPU::sub0)) in expandPostRAPseudo() 895 .addReg(RI.getSubReg(Src1, AMDGPU::sub0)) in expandPostRAPseudo() [all …]
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/external/llvm/lib/CodeGen/ |
D | PeepholeOptimizer.cpp | 465 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) in INITIALIZE_PASS_DEPENDENCY() 792 SrcSubReg = MOSrc.getSubReg(); in getNextRewritableSource() 796 TrackSubReg = MODef.getSubReg(); in getNextRewritableSource() 860 return TargetInstrInfo::RegSubRegPair(MODef.getReg(), MODef.getSubReg()); in getNewSource() 916 TrackSubReg = MODef.getSubReg(); in getNextRewritableSource() 992 SrcSubReg = MOInsertedReg.getSubReg(); in getNextRewritableSource() 998 if (MODef.getSubReg()) in getNextRewritableSource() 1041 if (MOExtractedReg.getSubReg()) in getNextRewritableSource() 1049 TrackSubReg = MODef.getSubReg(); in getNextRewritableSource() 1119 if ((SrcSubReg = MOInsertedReg.getSubReg())) in getNextRewritableSource() [all …]
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D | DetectDeadLanes.cpp | 165 unsigned SrcSubIdx = MO.getSubReg(); in isCrossCopy() 204 unsigned MOSubReg = MO.getSubReg(); in addUsedLanesOnOperand() 300 TRI->reverseComposeSubRegIndexLaneMask(Use.getSubReg(), DefinedLanes); in transferDefinedLanesStep() 349 assert(Def.getSubReg() == 0 && in transferDefinedLanes() 401 unsigned MOSubReg = MO.getSubReg(); in determineInitialDefinedLanes() 415 assert(Def.getSubReg() == 0 && in determineInitialDefinedLanes() 430 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes() 463 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput()
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D | CalcSpillWeights.cpp | 51 sub = mi->getOperand(0).getSubReg(); in copyHint() 53 hsub = mi->getOperand(1).getSubReg(); in copyHint() 55 sub = mi->getOperand(1).getSubReg(); in copyHint() 57 hsub = mi->getOperand(0).getSubReg(); in copyHint()
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D | TargetRegisterInfo.cpp | 218 if (RCI.getSubReg() == Idx) in getMatchingSuperRegClass() 257 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA); in getCommonSuperRegClass() 266 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB); in getCommonSuperRegClass() 276 *BestPreA = IA.getSubReg(); in getCommonSuperRegClass() 277 *BestPreB = IB.getSubReg(); in getCommonSuperRegClass()
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D | TargetInstrInfo.cpp | 146 unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0; in commuteInstructionImpl() 147 unsigned SubReg1 = MI.getOperand(Idx1).getSubReg(); in commuteInstructionImpl() 148 unsigned SubReg2 = MI.getOperand(Idx2).getSubReg(); in commuteInstructionImpl() 409 if (FoldOp.getSubReg() || LiveOp.getSubReg()) in canFoldCopy() 477 TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF); in foldPatchpoint() 839 MI.getOperand(0).getSubReg() && MI.readsVirtualRegister(DefReg)) in isReallyTriviallyReMaterializableGeneric() 1142 InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(), in getRegSequenceInputs() 1166 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregInputs() 1189 BaseReg.SubReg = MOBaseReg.getSubReg(); in getInsertSubregInputs() 1192 InsertedReg.SubReg = MOInsertedReg.getSubReg(); in getInsertSubregInputs()
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D | RegisterCoalescer.cpp | 283 DstSub = MI->getOperand(0).getSubReg(); in isMoveInstr() 285 SrcSub = MI->getOperand(1).getSubReg(); in isMoveInstr() 288 DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(), in isMoveInstr() 291 SrcSub = MI->getOperand(2).getSubReg(); in isMoveInstr() 338 Dst = TRI.getSubReg(Dst, DstSub); in setRegisters() 432 Dst = TRI.getSubReg(Dst, DstSub); in isCoalescable() 437 return TRI.getSubReg(DstReg, SrcSub) == Dst; in isCoalescable() 775 UseMI->getOperand(0).getSubReg()) in removeCopyByCommutingDef() 874 if (Op.getSubReg() == 0 || Op.isUndef()) in definesFullReg() 919 if (DstOperand.getSubReg() && !DstOperand.isUndef()) in reMaterializeTrivialDef() [all …]
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D | MachineInstr.cpp | 80 if (SubIdx && getSubReg()) in substVirtReg() 81 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); in substVirtReg() 89 if (getSubReg()) { in substPhysReg() 90 Reg = TRI.getSubReg(Reg, getSubReg()); in substPhysReg() 226 getSubReg() == Other.getSubReg(); in isIdenticalTo() 268 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef()); in hash_value() 317 OS << PrintReg(getReg(), TRI, getSubReg()); in print() 333 if (isUndef() && getSubReg()) in print() 1251 if (unsigned SubIdx = MO.getSubReg()) { in getRegClassConstraintEffect() 1325 else if (MO.getSubReg() && !MO.isUndef()) in readsWritesVirtualRegister() [all …]
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
D | ProcessImplicitDefs.cpp | 53 return MI->isCopy() && (MI->getOperand(0).getSubReg() == 0 || in CanTurnIntoImplicitDef() 56 return MI->isSubregToReg() && (MI->getOperand(0).getSubReg() == 0 || in CanTurnIntoImplicitDef() 69 if (!MO0.getSubReg() || ImpDefRegs.count(MO0.getReg())) in isUndefCopy() 108 if (MI->getOperand(0).getSubReg()) in runOnMachineFunction() 121 if (MI->isCopy() && MI->getOperand(0).getSubReg()) { in runOnMachineFunction() 143 if (!MO.isReg() || (MO.isDef() && !MO.getSubReg()) || MO.isUndef()) in runOnMachineFunction()
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D | CalcSpillWeights.cpp | 64 sub = mi->getOperand(0).getSubReg(); in copyHint() 66 hsub = mi->getOperand(1).getSubReg(); in copyHint() 68 sub = mi->getOperand(1).getSubReg(); in copyHint() 70 hsub = mi->getOperand(0).getSubReg(); in copyHint()
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonSplitDouble.cpp | 237 if (&MO == &Op || !MO.isReg() || MO.getSubReg()) in partitionRegisters() 306 if (!Op.getSubReg()) in profit() 310 if (MI->getOperand(1).getSubReg() != 0) in profit() 398 if (Op.getSubReg()) in isProfitable() 561 unsigned SR = Op.getSubReg(); in createHalfInstr() 608 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef() 611 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef() 617 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef() 621 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef() 633 assert(!UpdOp.getSubReg() && "Def operand with subreg"); in splitMemRef() [all …]
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D | HexagonAsmPrinter.cpp | 413 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::subreg_hireg); in HexagonProcessInstruction() 414 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::subreg_loreg); in HexagonProcessInstruction() 501 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::subreg_hireg); in HexagonProcessInstruction() 502 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::subreg_loreg); in HexagonProcessInstruction() 513 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::subreg_hireg); in HexagonProcessInstruction() 514 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::subreg_loreg); in HexagonProcessInstruction() 526 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::subreg_hireg); in HexagonProcessInstruction() 527 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::subreg_loreg); in HexagonProcessInstruction()
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D | HexagonRDFOpt.cpp | 108 assert(DstOp.getSubReg() == 0 && "Unexpected subregister"); in interpretAsCopy() 110 { HiOp.getReg(), HiOp.getSubReg() }); in interpretAsCopy() 112 { LoOp.getReg(), LoOp.getSubReg() }); in interpretAsCopy() 124 mapRegs({ DstOp.getReg(), DstOp.getSubReg() }, in interpretAsCopy() 125 { SrcOp.getReg(), SrcOp.getSubReg() }); in interpretAsCopy()
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D | HexagonInstrInfo.cpp | 115 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_loreg)) && in isDblRegForSubInst() 116 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_hireg)); in isDblRegForSubInst() 826 .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg), KillFlag) in copyPhysReg() 827 .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_loreg), KillFlag); in copyPhysReg() 847 unsigned DstHi = HRI.getSubReg(DestReg, Hexagon::subreg_hireg); in copyPhysReg() 849 .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg), KillFlag); in copyPhysReg() 850 unsigned DstLo = HRI.getSubReg(DestReg, Hexagon::subreg_loreg); in copyPhysReg() 852 .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_loreg), KillFlag); in copyPhysReg() 1027 unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::subreg_loreg); in expandPostRAPseudo() 1037 unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::subreg_hireg); in expandPostRAPseudo() [all …]
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D | HexagonRDF.cpp | 53 unsigned Lo = TRI.getSubReg(RR.Reg, Hexagon::subreg_loreg); in covers() 54 unsigned Hi = TRI.getSubReg(RR.Reg, Hexagon::subreg_hireg); in covers()
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D | HexagonExpandCondsets.cpp | 217 Sub(Op.getSubReg()) {} in RegisterRef() 353 LaneBitmask SLM = getLaneMask(Reg, Op.getSubReg()); in updateKillFlags() 414 unsigned DR = Op.getReg(), DSR = Op.getSubReg(); in updateDeadsInRange() 591 unsigned PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub); in getCondTfrOpcode() 655 unsigned DR = MD.getReg(), DSR = MD.getSubReg(); in split() 670 if ((MS1.isReg() && NewSR == MS1.getSubReg()) || in split() 671 (MS2.isReg() && NewSR == MS2.getSubReg())) in split() 885 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg()); in predicateAt() 887 PredOp.getSubReg()); in predicateAt() 963 if (MD.getSubReg() && !MRI->shouldTrackSubRegLiveness(MD.getReg())) in predicate()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64AdvSIMDScalarPass.cpp | 152 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy() 154 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) in getSrcFromCopy() 156 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy() 158 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), in getSrcFromCopy() 160 SubReg = MI->getOperand(1).getSubReg(); in getSrcFromCopy()
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/external/llvm/lib/Target/ARM/ |
D | ARMExpandPseudoInsts.cpp | 372 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs() 373 D1 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs() 374 D2 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs() 375 D3 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs() 377 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs() 378 D1 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs() 379 D2 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs() 380 D3 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs() 383 D0 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs() 384 D1 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs() [all …]
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/external/llvm/lib/Target/Sparc/ |
D | SparcRegisterInfo.cpp | 183 unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64); in eliminateFrameIndex() 184 unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64); in eliminateFrameIndex() 195 unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64); in eliminateFrameIndex() 196 unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64); in eliminateFrameIndex()
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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
D | MachineInstr.h | 288 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg(); 300 getOperand(0).getSubReg() == getOperand(1).getSubReg();
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMExpandPseudoInsts.cpp | 388 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs() 389 D1 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs() 390 D2 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs() 391 D3 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs() 393 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs() 394 D1 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs() 395 D2 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs() 396 D3 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs() 399 D0 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs() 400 D1 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs() [all …]
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/external/llvm/lib/MC/ |
D | MCRegisterInfo.cpp | 21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx)) in getMatchingSuperReg() 26 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const { in getSubReg() function in MCRegisterInfo
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