Home
last modified time | relevance | path

Searched refs:v16i1 (Results 1 – 25 of 26) sorted by relevance

12

/external/swiftshader/third_party/subzero/src/
DIceTypes.def49 X(v16i1, 4, 1, 16, i1, "<16 x i1>", "v16i1") \
77 X(v16i1, 1, 1, 0, 0, 1, 1, v16i1) \
78 X(v16i8, 1, 1, 0, 1, 0, 1, v16i1) \
DIceInstX8632.def226 X(v16i1, i8, "?", "", "", "", "b", "bw", "", "", "") \
DIceInstX8664.def322 X(v16i1, i8, "?", "", "", "", "b", "bw", "", "", "") \
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h62 v16i1 = 16, // 16 x i1 enumerator
229 SimpleTy == MVT::v16i1); in is16BitVector()
320 case v16i1: in getVectorElementType()
389 case v16i1: in getVectorNumElements()
456 case v16i1: in getSizeInBits()
596 if (NumElements == 16) return MVT::v16i1; in getVectorVT()
DValueTypes.td39 def v16i1 : ValueType<16, 16>; // 16 x i1 vector value
/external/swiftshader/third_party/subzero/crosstest/
Dtest_select_main.cpp145 testSelect<v16si8, v16i1>(TotalTests, Passes, Failures); in main()
146 testSelect<v16ui8, v16i1>(TotalTests, Passes, Failures); in main()
149 testSelectI1<v16i1>(TotalTests, Passes, Failures); in main()
Dtest_vector_ops_main.cpp175 testInsertElement<v16i1>(TotalTests, Passes, Failures); in main()
186 testExtractElement<v16i1>(TotalTests, Passes, Failures); in main()
197 testShuffleVector<v16i1>(TotalTests, Passes, Failures); in main()
Dtest_vector_ops.def31 X(v16i1, v16ui8, 16) \
Dvectors.def32 X(v16i1, v16si8, 16)
Dtest_icmp_main.cpp365 testsVecI1<v16i1>(TotalTests, Passes, Failures); in main()
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp446 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 16 }, in getCmpSelInstrCost()
448 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 16 }, in getCmpSelInstrCost()
451 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 16 * AmortizationCost } in getCmpSelInstrCost()
/external/llvm/lib/IR/
DValueTypes.cpp148 case MVT::v16i1: return "v16i1"; in getEVTString()
226 case MVT::v16i1: return VectorType::get(Type::getInt1Ty(Context), 16); in getTypeForEVT()
/external/llvm/test/CodeGen/SystemZ/
Dvec-move-16.ll5 ; Test a v16i1->v16i8 extension.
Dvec-move-15.ll5 ; Test a v16i1->v16i8 extension.
Dvec-and-03.ll5 ; Test a v16i1->v16i8 extension.
Dvec-move-17.ll5 ; Test a v16i8->v16i1 truncation.
Dvec-shift-07.ll5 ; Test a v16i1->v16i8 extension.
/external/llvm/lib/Target/X86/
DX86CallingConv.td49 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
326 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
599 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
786 CCIfType<[v16i1, v8i1], CCAssignToReg<[K1]>>,
DX86TargetTransformInfo.cpp564 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, in getCastInstrCost()
565 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, in getCastInstrCost()
576 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, in getCastInstrCost()
587 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, in getCastInstrCost()
DX86InstrAVX512.td1979 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
2006 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
2008 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
2010 def : Pat<(i32 (zext (i16 (bitconvert (v16i1 VK16:$src))))),
2012 def : Pat<(i32 (anyext (i16 (bitconvert (v16i1 VK16:$src))))),
2070 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
2074 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
2148 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
2224 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
2231 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
[all …]
DX86RegisterInfo.td515 def VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)> {let Size = 16;}
523 def VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)> {let Size = 16;}
DX86ISelLowering.cpp1136 addRegisterClass(MVT::v16i1, &X86::VK16RegClass); in X86TargetLowering()
1182 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom); in X86TargetLowering()
1220 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom); in X86TargetLowering()
1222 setOperationAction(ISD::VSELECT, MVT::v16i1, Expand); in X86TargetLowering()
1265 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom); in X86TargetLowering()
1292 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Custom); in X86TargetLowering()
1294 setOperationAction(ISD::SETCC, MVT::v16i1, Custom); in X86TargetLowering()
1300 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom); in X86TargetLowering()
1301 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v16i1, Custom); in X86TargetLowering()
1302 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom); in X86TargetLowering()
[all …]
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp76 case MVT::v16i1: return "MVT::v16i1"; in getEnumName()
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp303 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 100 } in getCmpSelInstrCost()
/external/llvm/include/llvm/IR/
DIntrinsics.td172 def llvm_v16i1_ty : LLVMType<v16i1>; // 16 x i1

12