1//===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the X86 Register file, defining the registers themselves, 11// aliases between the registers, and the register classes built out of the 12// registers. 13// 14//===----------------------------------------------------------------------===// 15 16class X86Reg<string n, bits<16> Enc, list<Register> subregs = []> : Register<n> { 17 let Namespace = "X86"; 18 let HWEncoding = Enc; 19 let SubRegs = subregs; 20} 21 22// Subregister indices. 23let Namespace = "X86" in { 24 def sub_8bit : SubRegIndex<8>; 25 def sub_8bit_hi : SubRegIndex<8, 8>; 26 def sub_16bit : SubRegIndex<16>; 27 def sub_32bit : SubRegIndex<32>; 28 def sub_xmm : SubRegIndex<128>; 29 def sub_ymm : SubRegIndex<256>; 30} 31 32//===----------------------------------------------------------------------===// 33// Register definitions... 34// 35 36// In the register alias definitions below, we define which registers alias 37// which others. We only specify which registers the small registers alias, 38// because the register file generator is smart enough to figure out that 39// AL aliases AX if we tell it that AX aliased AL (for example). 40 41// Dwarf numbering is different for 32-bit and 64-bit, and there are 42// variations by target as well. Currently the first entry is for X86-64, 43// second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux 44// and debug information on X86-32/Darwin) 45 46// 8-bit registers 47// Low registers 48def AL : X86Reg<"al", 0>; 49def DL : X86Reg<"dl", 2>; 50def CL : X86Reg<"cl", 1>; 51def BL : X86Reg<"bl", 3>; 52 53// High registers. On x86-64, these cannot be used in any instruction 54// with a REX prefix. 55def AH : X86Reg<"ah", 4>; 56def DH : X86Reg<"dh", 6>; 57def CH : X86Reg<"ch", 5>; 58def BH : X86Reg<"bh", 7>; 59 60// X86-64 only, requires REX. 61let CostPerUse = 1 in { 62def SIL : X86Reg<"sil", 6>; 63def DIL : X86Reg<"dil", 7>; 64def BPL : X86Reg<"bpl", 5>; 65def SPL : X86Reg<"spl", 4>; 66def R8B : X86Reg<"r8b", 8>; 67def R9B : X86Reg<"r9b", 9>; 68def R10B : X86Reg<"r10b", 10>; 69def R11B : X86Reg<"r11b", 11>; 70def R12B : X86Reg<"r12b", 12>; 71def R13B : X86Reg<"r13b", 13>; 72def R14B : X86Reg<"r14b", 14>; 73def R15B : X86Reg<"r15b", 15>; 74} 75 76// 16-bit registers 77let SubRegIndices = [sub_8bit, sub_8bit_hi], CoveredBySubRegs = 1 in { 78def AX : X86Reg<"ax", 0, [AL,AH]>; 79def DX : X86Reg<"dx", 2, [DL,DH]>; 80def CX : X86Reg<"cx", 1, [CL,CH]>; 81def BX : X86Reg<"bx", 3, [BL,BH]>; 82} 83let SubRegIndices = [sub_8bit] in { 84def SI : X86Reg<"si", 6, [SIL]>; 85def DI : X86Reg<"di", 7, [DIL]>; 86def BP : X86Reg<"bp", 5, [BPL]>; 87def SP : X86Reg<"sp", 4, [SPL]>; 88} 89def IP : X86Reg<"ip", 0>; 90 91// X86-64 only, requires REX. 92let SubRegIndices = [sub_8bit], CostPerUse = 1 in { 93def R8W : X86Reg<"r8w", 8, [R8B]>; 94def R9W : X86Reg<"r9w", 9, [R9B]>; 95def R10W : X86Reg<"r10w", 10, [R10B]>; 96def R11W : X86Reg<"r11w", 11, [R11B]>; 97def R12W : X86Reg<"r12w", 12, [R12B]>; 98def R13W : X86Reg<"r13w", 13, [R13B]>; 99def R14W : X86Reg<"r14w", 14, [R14B]>; 100def R15W : X86Reg<"r15w", 15, [R15B]>; 101} 102 103// 32-bit registers 104let SubRegIndices = [sub_16bit] in { 105def EAX : X86Reg<"eax", 0, [AX]>, DwarfRegNum<[-2, 0, 0]>; 106def EDX : X86Reg<"edx", 2, [DX]>, DwarfRegNum<[-2, 2, 2]>; 107def ECX : X86Reg<"ecx", 1, [CX]>, DwarfRegNum<[-2, 1, 1]>; 108def EBX : X86Reg<"ebx", 3, [BX]>, DwarfRegNum<[-2, 3, 3]>; 109def ESI : X86Reg<"esi", 6, [SI]>, DwarfRegNum<[-2, 6, 6]>; 110def EDI : X86Reg<"edi", 7, [DI]>, DwarfRegNum<[-2, 7, 7]>; 111def EBP : X86Reg<"ebp", 5, [BP]>, DwarfRegNum<[-2, 4, 5]>; 112def ESP : X86Reg<"esp", 4, [SP]>, DwarfRegNum<[-2, 5, 4]>; 113def EIP : X86Reg<"eip", 0, [IP]>, DwarfRegNum<[-2, 8, 8]>; 114 115// X86-64 only, requires REX 116let CostPerUse = 1 in { 117def R8D : X86Reg<"r8d", 8, [R8W]>; 118def R9D : X86Reg<"r9d", 9, [R9W]>; 119def R10D : X86Reg<"r10d", 10, [R10W]>; 120def R11D : X86Reg<"r11d", 11, [R11W]>; 121def R12D : X86Reg<"r12d", 12, [R12W]>; 122def R13D : X86Reg<"r13d", 13, [R13W]>; 123def R14D : X86Reg<"r14d", 14, [R14W]>; 124def R15D : X86Reg<"r15d", 15, [R15W]>; 125}} 126 127// 64-bit registers, X86-64 only 128let SubRegIndices = [sub_32bit] in { 129def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>; 130def RDX : X86Reg<"rdx", 2, [EDX]>, DwarfRegNum<[1, -2, -2]>; 131def RCX : X86Reg<"rcx", 1, [ECX]>, DwarfRegNum<[2, -2, -2]>; 132def RBX : X86Reg<"rbx", 3, [EBX]>, DwarfRegNum<[3, -2, -2]>; 133def RSI : X86Reg<"rsi", 6, [ESI]>, DwarfRegNum<[4, -2, -2]>; 134def RDI : X86Reg<"rdi", 7, [EDI]>, DwarfRegNum<[5, -2, -2]>; 135def RBP : X86Reg<"rbp", 5, [EBP]>, DwarfRegNum<[6, -2, -2]>; 136def RSP : X86Reg<"rsp", 4, [ESP]>, DwarfRegNum<[7, -2, -2]>; 137 138// These also require REX. 139let CostPerUse = 1 in { 140def R8 : X86Reg<"r8", 8, [R8D]>, DwarfRegNum<[ 8, -2, -2]>; 141def R9 : X86Reg<"r9", 9, [R9D]>, DwarfRegNum<[ 9, -2, -2]>; 142def R10 : X86Reg<"r10", 10, [R10D]>, DwarfRegNum<[10, -2, -2]>; 143def R11 : X86Reg<"r11", 11, [R11D]>, DwarfRegNum<[11, -2, -2]>; 144def R12 : X86Reg<"r12", 12, [R12D]>, DwarfRegNum<[12, -2, -2]>; 145def R13 : X86Reg<"r13", 13, [R13D]>, DwarfRegNum<[13, -2, -2]>; 146def R14 : X86Reg<"r14", 14, [R14D]>, DwarfRegNum<[14, -2, -2]>; 147def R15 : X86Reg<"r15", 15, [R15D]>, DwarfRegNum<[15, -2, -2]>; 148def RIP : X86Reg<"rip", 0, [EIP]>, DwarfRegNum<[16, -2, -2]>; 149}} 150 151// MMX Registers. These are actually aliased to ST0 .. ST7 152def MM0 : X86Reg<"mm0", 0>, DwarfRegNum<[41, 29, 29]>; 153def MM1 : X86Reg<"mm1", 1>, DwarfRegNum<[42, 30, 30]>; 154def MM2 : X86Reg<"mm2", 2>, DwarfRegNum<[43, 31, 31]>; 155def MM3 : X86Reg<"mm3", 3>, DwarfRegNum<[44, 32, 32]>; 156def MM4 : X86Reg<"mm4", 4>, DwarfRegNum<[45, 33, 33]>; 157def MM5 : X86Reg<"mm5", 5>, DwarfRegNum<[46, 34, 34]>; 158def MM6 : X86Reg<"mm6", 6>, DwarfRegNum<[47, 35, 35]>; 159def MM7 : X86Reg<"mm7", 7>, DwarfRegNum<[48, 36, 36]>; 160 161// Pseudo Floating Point registers 162def FP0 : X86Reg<"fp0", 0>; 163def FP1 : X86Reg<"fp1", 0>; 164def FP2 : X86Reg<"fp2", 0>; 165def FP3 : X86Reg<"fp3", 0>; 166def FP4 : X86Reg<"fp4", 0>; 167def FP5 : X86Reg<"fp5", 0>; 168def FP6 : X86Reg<"fp6", 0>; 169def FP7 : X86Reg<"fp7", 0>; 170 171// XMM Registers, used by the various SSE instruction set extensions. 172def XMM0: X86Reg<"xmm0", 0>, DwarfRegNum<[17, 21, 21]>; 173def XMM1: X86Reg<"xmm1", 1>, DwarfRegNum<[18, 22, 22]>; 174def XMM2: X86Reg<"xmm2", 2>, DwarfRegNum<[19, 23, 23]>; 175def XMM3: X86Reg<"xmm3", 3>, DwarfRegNum<[20, 24, 24]>; 176def XMM4: X86Reg<"xmm4", 4>, DwarfRegNum<[21, 25, 25]>; 177def XMM5: X86Reg<"xmm5", 5>, DwarfRegNum<[22, 26, 26]>; 178def XMM6: X86Reg<"xmm6", 6>, DwarfRegNum<[23, 27, 27]>; 179def XMM7: X86Reg<"xmm7", 7>, DwarfRegNum<[24, 28, 28]>; 180 181// X86-64 only 182let CostPerUse = 1 in { 183def XMM8: X86Reg<"xmm8", 8>, DwarfRegNum<[25, -2, -2]>; 184def XMM9: X86Reg<"xmm9", 9>, DwarfRegNum<[26, -2, -2]>; 185def XMM10: X86Reg<"xmm10", 10>, DwarfRegNum<[27, -2, -2]>; 186def XMM11: X86Reg<"xmm11", 11>, DwarfRegNum<[28, -2, -2]>; 187def XMM12: X86Reg<"xmm12", 12>, DwarfRegNum<[29, -2, -2]>; 188def XMM13: X86Reg<"xmm13", 13>, DwarfRegNum<[30, -2, -2]>; 189def XMM14: X86Reg<"xmm14", 14>, DwarfRegNum<[31, -2, -2]>; 190def XMM15: X86Reg<"xmm15", 15>, DwarfRegNum<[32, -2, -2]>; 191 192def XMM16: X86Reg<"xmm16", 16>, DwarfRegNum<[60, -2, -2]>; 193def XMM17: X86Reg<"xmm17", 17>, DwarfRegNum<[61, -2, -2]>; 194def XMM18: X86Reg<"xmm18", 18>, DwarfRegNum<[62, -2, -2]>; 195def XMM19: X86Reg<"xmm19", 19>, DwarfRegNum<[63, -2, -2]>; 196def XMM20: X86Reg<"xmm20", 20>, DwarfRegNum<[64, -2, -2]>; 197def XMM21: X86Reg<"xmm21", 21>, DwarfRegNum<[65, -2, -2]>; 198def XMM22: X86Reg<"xmm22", 22>, DwarfRegNum<[66, -2, -2]>; 199def XMM23: X86Reg<"xmm23", 23>, DwarfRegNum<[67, -2, -2]>; 200def XMM24: X86Reg<"xmm24", 24>, DwarfRegNum<[68, -2, -2]>; 201def XMM25: X86Reg<"xmm25", 25>, DwarfRegNum<[69, -2, -2]>; 202def XMM26: X86Reg<"xmm26", 26>, DwarfRegNum<[70, -2, -2]>; 203def XMM27: X86Reg<"xmm27", 27>, DwarfRegNum<[71, -2, -2]>; 204def XMM28: X86Reg<"xmm28", 28>, DwarfRegNum<[72, -2, -2]>; 205def XMM29: X86Reg<"xmm29", 29>, DwarfRegNum<[73, -2, -2]>; 206def XMM30: X86Reg<"xmm30", 30>, DwarfRegNum<[74, -2, -2]>; 207def XMM31: X86Reg<"xmm31", 31>, DwarfRegNum<[75, -2, -2]>; 208 209} // CostPerUse 210 211// YMM0-15 registers, used by AVX instructions and 212// YMM16-31 registers, used by AVX-512 instructions. 213let SubRegIndices = [sub_xmm] in { 214 foreach Index = 0-31 in { 215 def YMM#Index : X86Reg<"ymm"#Index, Index, [!cast<X86Reg>("XMM"#Index)]>, 216 DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>; 217 } 218} 219 220// ZMM Registers, used by AVX-512 instructions. 221let SubRegIndices = [sub_ymm] in { 222 foreach Index = 0-31 in { 223 def ZMM#Index : X86Reg<"zmm"#Index, Index, [!cast<X86Reg>("YMM"#Index)]>, 224 DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>; 225 } 226} 227 228// Mask Registers, used by AVX-512 instructions. 229def K0 : X86Reg<"k0", 0>, DwarfRegNum<[118, 93, 93]>; 230def K1 : X86Reg<"k1", 1>, DwarfRegNum<[119, 94, 94]>; 231def K2 : X86Reg<"k2", 2>, DwarfRegNum<[120, 95, 95]>; 232def K3 : X86Reg<"k3", 3>, DwarfRegNum<[121, 96, 96]>; 233def K4 : X86Reg<"k4", 4>, DwarfRegNum<[122, 97, 97]>; 234def K5 : X86Reg<"k5", 5>, DwarfRegNum<[123, 98, 98]>; 235def K6 : X86Reg<"k6", 6>, DwarfRegNum<[124, 99, 99]>; 236def K7 : X86Reg<"k7", 7>, DwarfRegNum<[125, 100, 100]>; 237 238// Floating point stack registers. These don't map one-to-one to the FP 239// pseudo registers, but we still mark them as aliasing FP registers. That 240// way both kinds can be live without exceeding the stack depth. ST registers 241// are only live around inline assembly. 242def ST0 : X86Reg<"st(0)", 0>, DwarfRegNum<[33, 12, 11]>; 243def ST1 : X86Reg<"st(1)", 1>, DwarfRegNum<[34, 13, 12]>; 244def ST2 : X86Reg<"st(2)", 2>, DwarfRegNum<[35, 14, 13]>; 245def ST3 : X86Reg<"st(3)", 3>, DwarfRegNum<[36, 15, 14]>; 246def ST4 : X86Reg<"st(4)", 4>, DwarfRegNum<[37, 16, 15]>; 247def ST5 : X86Reg<"st(5)", 5>, DwarfRegNum<[38, 17, 16]>; 248def ST6 : X86Reg<"st(6)", 6>, DwarfRegNum<[39, 18, 17]>; 249def ST7 : X86Reg<"st(7)", 7>, DwarfRegNum<[40, 19, 18]>; 250 251// Floating-point status word 252def FPSW : X86Reg<"fpsw", 0>; 253 254// Status flags register 255def EFLAGS : X86Reg<"flags", 0>; 256 257// Segment registers 258def CS : X86Reg<"cs", 1>; 259def DS : X86Reg<"ds", 3>; 260def SS : X86Reg<"ss", 2>; 261def ES : X86Reg<"es", 0>; 262def FS : X86Reg<"fs", 4>; 263def GS : X86Reg<"gs", 5>; 264 265// Debug registers 266def DR0 : X86Reg<"dr0", 0>; 267def DR1 : X86Reg<"dr1", 1>; 268def DR2 : X86Reg<"dr2", 2>; 269def DR3 : X86Reg<"dr3", 3>; 270def DR4 : X86Reg<"dr4", 4>; 271def DR5 : X86Reg<"dr5", 5>; 272def DR6 : X86Reg<"dr6", 6>; 273def DR7 : X86Reg<"dr7", 7>; 274def DR8 : X86Reg<"dr8", 8>; 275def DR9 : X86Reg<"dr9", 9>; 276def DR10 : X86Reg<"dr10", 10>; 277def DR11 : X86Reg<"dr11", 11>; 278def DR12 : X86Reg<"dr12", 12>; 279def DR13 : X86Reg<"dr13", 13>; 280def DR14 : X86Reg<"dr14", 14>; 281def DR15 : X86Reg<"dr15", 15>; 282 283// Control registers 284def CR0 : X86Reg<"cr0", 0>; 285def CR1 : X86Reg<"cr1", 1>; 286def CR2 : X86Reg<"cr2", 2>; 287def CR3 : X86Reg<"cr3", 3>; 288def CR4 : X86Reg<"cr4", 4>; 289def CR5 : X86Reg<"cr5", 5>; 290def CR6 : X86Reg<"cr6", 6>; 291def CR7 : X86Reg<"cr7", 7>; 292def CR8 : X86Reg<"cr8", 8>; 293def CR9 : X86Reg<"cr9", 9>; 294def CR10 : X86Reg<"cr10", 10>; 295def CR11 : X86Reg<"cr11", 11>; 296def CR12 : X86Reg<"cr12", 12>; 297def CR13 : X86Reg<"cr13", 13>; 298def CR14 : X86Reg<"cr14", 14>; 299def CR15 : X86Reg<"cr15", 15>; 300 301// Pseudo index registers 302def EIZ : X86Reg<"eiz", 4>; 303def RIZ : X86Reg<"riz", 4>; 304 305// Bound registers, used in MPX instructions 306def BND0 : X86Reg<"bnd0", 0>; 307def BND1 : X86Reg<"bnd1", 1>; 308def BND2 : X86Reg<"bnd2", 2>; 309def BND3 : X86Reg<"bnd3", 3>; 310 311//===----------------------------------------------------------------------===// 312// Register Class Definitions... now that we have all of the pieces, define the 313// top-level register classes. The order specified in the register list is 314// implicitly defined to be the register allocation order. 315// 316 317// List call-clobbered registers before callee-save registers. RBX, RBP, (and 318// R12, R13, R14, and R15 for X86-64) are callee-save registers. 319// In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and 320// R8B, ... R15B. 321// Allocate R12 and R13 last, as these require an extra byte when 322// encoded in x86_64 instructions. 323// FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in 324// 64-bit mode. The main complication is that they cannot be encoded in an 325// instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc. 326// require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d" 327// cannot be encoded. 328def GR8 : RegisterClass<"X86", [i8], 8, 329 (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL, 330 R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B)> { 331 let AltOrders = [(sub GR8, AH, BH, CH, DH)]; 332 let AltOrderSelect = [{ 333 return MF.getSubtarget<X86Subtarget>().is64Bit(); 334 }]; 335} 336 337def GR16 : RegisterClass<"X86", [i16], 16, 338 (add AX, CX, DX, SI, DI, BX, BP, SP, 339 R8W, R9W, R10W, R11W, R14W, R15W, R12W, R13W)>; 340 341def GR32 : RegisterClass<"X86", [i32], 32, 342 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP, 343 R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D)>; 344 345// GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since 346// RIP isn't really a register and it can't be used anywhere except in an 347// address, but it doesn't cause trouble. 348def GR64 : RegisterClass<"X86", [i64], 64, 349 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, 350 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>; 351 352// Segment registers for use by MOV instructions (and others) that have a 353// segment register as one operand. Always contain a 16-bit segment 354// descriptor. 355def SEGMENT_REG : RegisterClass<"X86", [i16], 16, (add CS, DS, SS, ES, FS, GS)>; 356 357// Debug registers. 358def DEBUG_REG : RegisterClass<"X86", [i32], 32, (sequence "DR%u", 0, 7)>; 359 360// Control registers. 361def CONTROL_REG : RegisterClass<"X86", [i64], 64, (sequence "CR%u", 0, 15)>; 362 363// GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of 364// GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d" 365// registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers 366// that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD, 367// and GR64_ABCD are classes for registers that support 8-bit h-register 368// operations. 369def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, (add AL, CL, DL, BL)>; 370def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>; 371def GR16_ABCD : RegisterClass<"X86", [i16], 16, (add AX, CX, DX, BX)>; 372def GR32_ABCD : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, EBX)>; 373def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>; 374def GR32_TC : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX)>; 375def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI, 376 R8, R9, R11, RIP)>; 377def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, 378 R8, R9, R10, R11, RIP)>; 379 380// GR8_NOREX - GR8 registers which do not require a REX prefix. 381def GR8_NOREX : RegisterClass<"X86", [i8], 8, 382 (add AL, CL, DL, AH, CH, DH, BL, BH)> { 383 let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)]; 384 let AltOrderSelect = [{ 385 return MF.getSubtarget<X86Subtarget>().is64Bit(); 386 }]; 387} 388// GR16_NOREX - GR16 registers which do not require a REX prefix. 389def GR16_NOREX : RegisterClass<"X86", [i16], 16, 390 (add AX, CX, DX, SI, DI, BX, BP, SP)>; 391// GR32_NOREX - GR32 registers which do not require a REX prefix. 392def GR32_NOREX : RegisterClass<"X86", [i32], 32, 393 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP)>; 394// GR64_NOREX - GR64 registers which do not require a REX prefix. 395def GR64_NOREX : RegisterClass<"X86", [i64], 64, 396 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>; 397 398// GR32_NOAX - GR32 registers except EAX. Used by AddRegFrm of XCHG32 in 64-bit 399// mode to prevent encoding using the 0x90 NOP encoding. xchg %eax, %eax needs 400// to clear upper 32-bits of RAX so is not a NOP. 401def GR32_NOAX : RegisterClass<"X86", [i32], 32, (sub GR32, EAX)>; 402 403// GR32_NOSP - GR32 registers except ESP. 404def GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)>; 405 406// GR64_NOSP - GR64 registers except RSP (and RIP). 407def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>; 408 409// GR32_NOREX_NOSP - GR32 registers which do not require a REX prefix except 410// ESP. 411def GR32_NOREX_NOSP : RegisterClass<"X86", [i32], 32, 412 (and GR32_NOREX, GR32_NOSP)>; 413 414// GR64_NOREX_NOSP - GR64_NOREX registers except RSP. 415def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64, 416 (and GR64_NOREX, GR64_NOSP)>; 417 418// Register classes used for ABIs that use 32-bit address accesses, 419// while using the whole x84_64 ISA. 420 421// In such cases, it is fine to use RIP as we are sure the 32 high 422// bits are not set. We do not need variants for NOSP as RIP is not 423// allowed there. 424// RIP is not spilled anywhere for now, so stick to 32-bit alignment 425// to save on memory space. 426// FIXME: We could allow all 64bit registers, but we would need 427// something to check that the 32 high bits are not set, 428// which we do not have right now. 429def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 32, (add GR32, RIP)>; 430 431// When RBP is used as a base pointer in a 32-bit addresses environement, 432// this is also safe to use the full register to access addresses. 433// Since RBP will never be spilled, stick to a 32 alignment to save 434// on memory consumption. 435def LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 32, 436 (add LOW32_ADDR_ACCESS, RBP)>; 437 438// A class to support the 'A' assembler constraint: EAX then EDX. 439def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>; 440 441// Scalar SSE2 floating point registers. 442def FR32 : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 15)>; 443 444def FR64 : RegisterClass<"X86", [f64], 64, (add FR32)>; 445 446def FR128 : RegisterClass<"X86", [i128, f128], 128, (add FR32)>; 447 448 449// FIXME: This sets up the floating point register files as though they are f64 450// values, though they really are f80 values. This will cause us to spill 451// values as 64-bit quantities instead of 80-bit quantities, which is much much 452// faster on common hardware. In reality, this should be controlled by a 453// command line option or something. 454 455def RFP32 : RegisterClass<"X86",[f32], 32, (sequence "FP%u", 0, 6)>; 456def RFP64 : RegisterClass<"X86",[f64], 32, (add RFP32)>; 457def RFP80 : RegisterClass<"X86",[f80], 32, (add RFP32)>; 458 459// Floating point stack registers (these are not allocatable by the 460// register allocator - the floating point stackifier is responsible 461// for transforming FPn allocations to STn registers) 462def RST : RegisterClass<"X86", [f80, f64, f32], 32, (sequence "ST%u", 0, 7)> { 463 let isAllocatable = 0; 464} 465 466// Generic vector registers: VR64 and VR128. 467// Ensure that float types are declared first - only float is legal on SSE1. 468def VR64: RegisterClass<"X86", [x86mmx], 64, (sequence "MM%u", 0, 7)>; 469def VR128 : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64], 470 128, (add FR32)>; 471def VR256 : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64], 472 256, (sequence "YMM%u", 0, 15)>; 473 474// Special classes that help the assembly parser choose some alternate 475// instructions to favor 2-byte VEX encodings. 476def VR128L : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64], 477 128, (sequence "XMM%u", 0, 7)>; 478def VR128H : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64], 479 128, (sequence "XMM%u", 8, 15)>; 480def VR256L : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64], 481 256, (sequence "YMM%u", 0, 7)>; 482def VR256H : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64], 483 256, (sequence "YMM%u", 8, 15)>; 484 485// Status flags registers. 486def CCR : RegisterClass<"X86", [i32], 32, (add EFLAGS)> { 487 let CopyCost = -1; // Don't allow copying of status registers. 488 let isAllocatable = 0; 489} 490def FPCCR : RegisterClass<"X86", [i16], 16, (add FPSW)> { 491 let CopyCost = -1; // Don't allow copying of status registers. 492 let isAllocatable = 0; 493} 494 495// AVX-512 vector/mask registers. 496def VR512 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64], 497 512, (sequence "ZMM%u", 0, 31)>; 498 499// Scalar AVX-512 floating point registers. 500def FR32X : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 31)>; 501 502def FR64X : RegisterClass<"X86", [f64], 64, (add FR32X)>; 503 504// Extended VR128 and VR256 for AVX-512 instructions 505def VR128X : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64], 506 128, (add FR32X)>; 507def VR256X : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64], 508 256, (sequence "YMM%u", 0, 31)>; 509 510// Mask registers 511def VK1 : RegisterClass<"X86", [i1], 16, (sequence "K%u", 0, 7)> {let Size = 16;} 512def VK2 : RegisterClass<"X86", [v2i1], 16, (add VK1)> {let Size = 16;} 513def VK4 : RegisterClass<"X86", [v4i1], 16, (add VK2)> {let Size = 16;} 514def VK8 : RegisterClass<"X86", [v8i1], 16, (add VK4)> {let Size = 16;} 515def VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)> {let Size = 16;} 516def VK32 : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let Size = 32;} 517def VK64 : RegisterClass<"X86", [v64i1], 64, (add VK32)> {let Size = 64;} 518 519def VK1WM : RegisterClass<"X86", [i1], 16, (sub VK1, K0)> {let Size = 16;} 520def VK2WM : RegisterClass<"X86", [v2i1], 16, (sub VK2, K0)> {let Size = 16;} 521def VK4WM : RegisterClass<"X86", [v4i1], 16, (sub VK4, K0)> {let Size = 16;} 522def VK8WM : RegisterClass<"X86", [v8i1], 16, (sub VK8, K0)> {let Size = 16;} 523def VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)> {let Size = 16;} 524def VK32WM : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;} 525def VK64WM : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;} 526 527// Bound registers 528def BNDR : RegisterClass<"X86", [v2i64], 128, (sequence "BND%u", 0, 3)>; 529