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/toolchain/binutils/binutils-2.27/gas/config/
Dtc-bfin.c1237 REG_T dst0, REG_T dst1, REG_T src0, REG_T src1) in bfin_gen_dsp32alu() argument
1246 ASSIGN_R (dst0); in bfin_gen_dsp32alu()
1255 bfin_gen_dsp32shift (int sopcde, REG_T dst0, REG_T src0, in bfin_gen_dsp32shift() argument
1264 ASSIGN_R (dst0); in bfin_gen_dsp32shift()
1272 bfin_gen_dsp32shiftimm (int sopcde, REG_T dst0, int immag, in bfin_gen_dsp32shiftimm() argument
1281 ASSIGN_R (dst0); in bfin_gen_dsp32shiftimm()
2360 int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask); in decode_dsp32alu_0() local
2370 return HL ? DREGH_MASK (dst0) : DREGL_MASK (dst0); in decode_dsp32alu_0()
2372 return DREGL_MASK (dst0); in decode_dsp32alu_0()
2374 return DREGH_MASK (dst0); in decode_dsp32alu_0()
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Dbfin-parse.y29 #define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \ argument
30 bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1)
40 #define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls) \ argument
41 bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls)
43 #define DSP32SHIFTIMM(sopcde, dst0, immag, src1, sop, hls) \ argument
44 bfin_gen_dsp32shiftimm (sopcde, dst0, immag, src1, sop, hls)
/toolchain/binutils/binutils-2.27/opcodes/
Dbfin-dis.c3083 int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask); in decode_dsp32alu_0() local
3110 OUTS (outf, dregs_hi (dst0)); in decode_dsp32alu_0()
3119 OUTS (outf, dregs_hi (dst0)); in decode_dsp32alu_0()
3128 OUTS (outf, dregs_lo (dst0)); in decode_dsp32alu_0()
3137 OUTS (outf, dregs_lo (dst0)); in decode_dsp32alu_0()
3146 OUTS (outf, dregs_lo (dst0)); in decode_dsp32alu_0()
3155 OUTS (outf, dregs_hi (dst0)); in decode_dsp32alu_0()
3164 OUTS (outf, dregs_lo (dst0)); in decode_dsp32alu_0()
3173 OUTS (outf, dregs_hi (dst0)); in decode_dsp32alu_0()
3182 OUTS (outf, dregs_hi (dst0)); in decode_dsp32alu_0()
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