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/toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/
Dneon-const.s7 vmov.f32 q0, 0.0
9 vmov.f32 q0, 2.0
10 vmov.f32 q0, 4.0
11 vmov.f32 q0, 8.0
12 vmov.f32 q0, 16.0
13 vmov.f32 q0, 0.125
14 vmov.f32 q0, 0.25
15 vmov.f32 q0, 0.5
16 vmov.f32 q0, 1.0
18 vmov.f32 q0, 2.125
[all …]
Dneon-const.d9 0[0-9a-f]+ <[^>]+> f2800f50 vmov\.f32 q0, #2 ; 0x40000000
10 0[0-9a-f]+ <[^>]+> f2810f50 vmov\.f32 q0, #4 ; 0x40800000
11 0[0-9a-f]+ <[^>]+> f2820f50 vmov\.f32 q0, #8 ; 0x41000000
12 0[0-9a-f]+ <[^>]+> f2830f50 vmov\.f32 q0, #16 ; 0x41800000
13 0[0-9a-f]+ <[^>]+> f2840f50 vmov\.f32 q0, #0\.125 ; 0x3e000000
14 0[0-9a-f]+ <[^>]+> f2850f50 vmov\.f32 q0, #0\.25 ; 0x3e800000
15 0[0-9a-f]+ <[^>]+> f2860f50 vmov\.f32 q0, #0\.5 ; 0x3f000000
16 0[0-9a-f]+ <[^>]+> f2870f50 vmov\.f32 q0, #1 ; 0x3f800000
17 0[0-9a-f]+ <[^>]+> f2800f51 vmov\.f32 q0, #2\.125 ; 0x40080000
18 0[0-9a-f]+ <[^>]+> f2810f51 vmov\.f32 q0, #4\.25 ; 0x40880000
[all …]
Darmv8-a+simd.s6 vmaxnm.f32 d0, d0, d0
7 vmaxnm.f32 d16, d16, d16
8 vmaxnm.f32 d15, d15, d15
9 vmaxnm.f32 d31, d31, d31
10 vmaxnm.f32 q0, q0, q0
11 vmaxnm.f32 q8, q8, q8
12 vmaxnm.f32 q7, q7, q7
13 vmaxnm.f32 q15, q15, q15
14 vminnm.f32 d0, d0, d0
15 vminnm.f32 d16, d16, d16
[all …]
Dhalf-prec-vfpv3.s2 vcvtt.f32.f16 s0, s1
3 vcvtteq.f32.f16 s2, s3
4 vcvttne.f32.f16 s2, s3
5 vcvttcs.f32.f16 s2, s3
6 vcvttcc.f32.f16 s2, s3
7 vcvttmi.f32.f16 s2, s3
8 vcvttpl.f32.f16 s2, s3
9 vcvttvs.f32.f16 s2, s3
10 vcvttvc.f32.f16 s2, s3
11 vcvtthi.f32.f16 s2, s3
[all …]
Dhalf-prec-vfpv3.d8 0+000 <[^>]*> eeb20ae0 vcvtt.f32.f16 s0, s1
9 0+004 <[^>]*> 0eb21ae1 vcvtteq.f32.f16 s2, s3
10 0+008 <[^>]*> 1eb21ae1 vcvttne.f32.f16 s2, s3
11 0+00c <[^>]*> 2eb21ae1 vcvttcs.f32.f16 s2, s3
12 0+010 <[^>]*> 3eb21ae1 vcvttcc.f32.f16 s2, s3
13 0+014 <[^>]*> 4eb21ae1 vcvttmi.f32.f16 s2, s3
14 0+018 <[^>]*> 5eb21ae1 vcvttpl.f32.f16 s2, s3
15 0+01c <[^>]*> 6eb21ae1 vcvttvs.f32.f16 s2, s3
16 0+020 <[^>]*> 7eb21ae1 vcvttvc.f32.f16 s2, s3
17 0+024 <[^>]*> 8eb21ae1 vcvtthi.f32.f16 s2, s3
[all …]
Darmv8-a+simd.d8 0[0-9a-f]+ <[^>]+> f3000f10 vmaxnm.f32 d0, d0, d0
9 0[0-9a-f]+ <[^>]+> f3400fb0 vmaxnm.f32 d16, d16, d16
10 0[0-9a-f]+ <[^>]+> f30fff1f vmaxnm.f32 d15, d15, d15
11 0[0-9a-f]+ <[^>]+> f34fffbf vmaxnm.f32 d31, d31, d31
12 0[0-9a-f]+ <[^>]+> f3000f50 vmaxnm.f32 q0, q0, q0
13 0[0-9a-f]+ <[^>]+> f3400ff0 vmaxnm.f32 q8, q8, q8
14 0[0-9a-f]+ <[^>]+> f30eef5e vmaxnm.f32 q7, q7, q7
15 0[0-9a-f]+ <[^>]+> f34eeffe vmaxnm.f32 q15, q15, q15
16 0[0-9a-f]+ <[^>]+> f3200f10 vminnm.f32 d0, d0, d0
17 0[0-9a-f]+ <[^>]+> f3600fb0 vminnm.f32 d16, d16, d16
[all …]
Darmv7e-m+fpv5-sp-d16.s7 vseleq.f32 s0, s0, s0
8 vselvs.f32 s1, s1, s1
9 vselge.f32 s30, s30, s30
10 vselgt.f32 s31, s31, s31
11 vmaxnm.f32 s0, s0, s0
12 vmaxnm.f32 s1, s1, s1
13 vmaxnm.f32 s30, s30, s30
14 vmaxnm.f32 s31, s31, s31
15 vminnm.f32 s0, s0, s0
16 vminnm.f32 s1, s1, s1
[all …]
Darmv8-a+fp.s7 vseleq.f32 s0, s0, s0
8 vselvs.f32 s1, s1, s1
9 vselge.f32 s30, s30, s30
10 vselgt.f32 s31, s31, s31
15 vmaxnm.f32 s0, s0, s0
16 vmaxnm.f32 s1, s1, s1
17 vmaxnm.f32 s30, s30, s30
18 vmaxnm.f32 s31, s31, s31
23 vminnm.f32 s0, s0, s0
24 vminnm.f32 s1, s1, s1
[all …]
Dvfp1xD.d11 0+004 <[^>]*> eeb40ac0 (vcmpe\.f32|fcmpes) s0, s0
12 0+008 <[^>]*> eeb50ac0 (vcmpe\.f32 s0, #0.0|fcmpezs s0)
13 0+00c <[^>]*> eeb40a40 (vcmp\.f32|fcmps) s0, s0
14 0+010 <[^>]*> eeb50a40 (vcmp\.f32 s0, #0.0|fcmpzs s0)
15 0+014 <[^>]*> eeb00ac0 (vabs\.f32|fabss) s0, s0
16 0+018 <[^>]*> eeb00a40 (vmov\.f32|fcpys) s0, s0
17 0+01c <[^>]*> eeb10a40 (vneg\.f32|fnegs) s0, s0
18 0+020 <[^>]*> eeb10ac0 (vsqrt\.f32|fsqrts) s0, s0
19 0+024 <[^>]*> ee300a00 (vadd\.f32|fadds) s0, s0, s0
20 0+028 <[^>]*> ee800a00 (vdiv\.f32|fdivs) s0, s0, s0
[all …]
Dvfp1xD_t2.d11 0+004 <[^>]*> eeb4 0ac0 (vcmpe\.f32|fcmpes) s0, s0
12 0+008 <[^>]*> eeb5 0ac0 (vcmpe\.f32 s0, #0.0|fcmpezs s0)
13 0+00c <[^>]*> eeb4 0a40 (vcmp\.f32|fcmps) s0, s0
14 0+010 <[^>]*> eeb5 0a40 (vcmp\.f32 s0, #0.0|fcmpzs s0)
15 0+014 <[^>]*> eeb0 0ac0 (vabs\.f32|fabss) s0, s0
16 0+018 <[^>]*> eeb0 0a40 (vmov\.f32|fcpys) s0, s0
17 0+01c <[^>]*> eeb1 0a40 (vneg\.f32|fnegs) s0, s0
18 0+020 <[^>]*> eeb1 0ac0 (vsqrt\.f32|fsqrts) s0, s0
19 0+024 <[^>]*> ee30 0a00 (vadd\.f32|fadds) s0, s0, s0
20 0+028 <[^>]*> ee80 0a00 (vdiv\.f32|fdivs) s0, s0, s0
[all …]
Darmv7e-m+fpv5-sp-d16.d7 0[0-9a-f]+ <[^>]+> fe00 0a00 vseleq.f32 s0, s0, s0
8 0[0-9a-f]+ <[^>]+> fe50 0aa0 vselvs.f32 s1, s1, s1
9 0[0-9a-f]+ <[^>]+> fe2f fa0f vselge.f32 s30, s30, s30
10 0[0-9a-f]+ <[^>]+> fe7f faaf vselgt.f32 s31, s31, s31
11 0[0-9a-f]+ <[^>]+> fe80 0a00 vmaxnm.f32 s0, s0, s0
12 0[0-9a-f]+ <[^>]+> fec0 0aa0 vmaxnm.f32 s1, s1, s1
13 0[0-9a-f]+ <[^>]+> fe8f fa0f vmaxnm.f32 s30, s30, s30
14 0[0-9a-f]+ <[^>]+> fecf faaf vmaxnm.f32 s31, s31, s31
15 0[0-9a-f]+ <[^>]+> fe80 0a40 vminnm.f32 s0, s0, s0
16 0[0-9a-f]+ <[^>]+> fec0 0ae0 vminnm.f32 s1, s1, s1
[all …]
Darmv7e-m+fpv5-d16.s7 vseleq.f32 s0, s0, s0
8 vselvs.f32 s1, s1, s1
9 vselge.f32 s30, s30, s30
10 vselgt.f32 s31, s31, s31
15 vmaxnm.f32 s0, s0, s0
16 vmaxnm.f32 s1, s1, s1
17 vmaxnm.f32 s30, s30, s30
18 vmaxnm.f32 s31, s31, s31
23 vminnm.f32 s0, s0, s0
24 vminnm.f32 s1, s1, s1
[all …]
Darmv8-a+fp.d8 0[0-9a-f]+ <[^>]+> fe000a00 vseleq.f32 s0, s0, s0
9 0[0-9a-f]+ <[^>]+> fe500aa0 vselvs.f32 s1, s1, s1
10 0[0-9a-f]+ <[^>]+> fe2ffa0f vselge.f32 s30, s30, s30
11 0[0-9a-f]+ <[^>]+> fe7ffaaf vselgt.f32 s31, s31, s31
16 0[0-9a-f]+ <[^>]+> fe800a00 vmaxnm.f32 s0, s0, s0
17 0[0-9a-f]+ <[^>]+> fec00aa0 vmaxnm.f32 s1, s1, s1
18 0[0-9a-f]+ <[^>]+> fe8ffa0f vmaxnm.f32 s30, s30, s30
19 0[0-9a-f]+ <[^>]+> fecffaaf vmaxnm.f32 s31, s31, s31
24 0[0-9a-f]+ <[^>]+> fe800a40 vminnm.f32 s0, s0, s0
25 0[0-9a-f]+ <[^>]+> fec00ae0 vminnm.f32 s1, s1, s1
[all …]
Dvfp-neon-syntax.d8 0[0-9a-f]+ <[^>]+> eeb00a60 (vmov\.f32|fcpys) s0, s1
10 0[0-9a-f]+ <[^>]+> eeb50a00 (vmov\.f32|fconsts) s0, #80.*
16 0[0-9a-f]+ <[^>]+> 0eb00a60 (vmoveq\.f32|fcpyseq) s0, s1
18 0[0-9a-f]+ <[^>]+> 0eb50a00 (vmoveq\.f32|fconstseq) s0, #80.*
24 0[0-9a-f]+ <[^>]+> eeb10ae0 (vsqrt\.f32|fsqrts) s0, s1
26 0[0-9a-f]+ <[^>]+> 0eb10ae0 (vsqrteq.f32|fsqrtseq) s0, s1
28 0[0-9a-f]+ <[^>]+> eeb00ae0 (vabs\.f32|fabss) s0, s1
30 0[0-9a-f]+ <[^>]+> 0eb00ae0 (vabseq\.f32|fabsseq) s0, s1
32 0[0-9a-f]+ <[^>]+> eeb10a60 (vneg\.f32|fnegs) s0, s1
34 0[0-9a-f]+ <[^>]+> 0eb10a60 (vnegeq\.f32|fnegseq) s0, s1
[all …]
Dvfma1.d13 00000000 <[^>]*> ee000a00 vmla.f32 s0, s0, s0
15 00000008 <[^>]*> f2000d10 vmla.f32 d0, d0, d0
16 0000000c <[^>]*> f2000d50 vmla.f32 q0, q0, q0
17 00000010 <[^>]*> eea00a00 vfma.f32 s0, s0, s0
19 00000018 <[^>]*> f2000c10 vfma.f32 d0, d0, d0
20 0000001c <[^>]*> f2000c50 vfma.f32 q0, q0, q0
21 00000020 <[^>]*> ee000a40 vmls.f32 s0, s0, s0
23 00000028 <[^>]*> f2200d10 vmls.f32 d0, d0, d0
24 0000002c <[^>]*> f2200d50 vmls.f32 q0, q0, q0
25 00000030 <[^>]*> eea00a40 vfms.f32 s0, s0, s0
[all …]
Dneon-cond-bad_t2.d19 0[0-9a-f]+ <[^>]+> ff01 0d12 vmuleq\.f32 d0, d1, d2
20 0[0-9a-f]+ <[^>]+> ff02 0d54 vmuleq\.f32 q0, q1, q2
22 0[0-9a-f]+ <[^>]+> ef01 0d12 vmlaeq\.f32 d0, d1, d2
23 0[0-9a-f]+ <[^>]+> ef02 0d54 vmlaeq\.f32 q0, q1, q2
25 0[0-9a-f]+ <[^>]+> ef21 0d12 vmlseq\.f32 d0, d1, d2
26 0[0-9a-f]+ <[^>]+> ef22 0d54 vmlseq\.f32 q0, q1, q2
28 0[0-9a-f]+ <[^>]+> ef01 0d02 vaddeq\.f32 d0, d1, d2
29 0[0-9a-f]+ <[^>]+> ef02 0d44 vaddeq\.f32 q0, q1, q2
31 0[0-9a-f]+ <[^>]+> ef21 0d02 vsubeq\.f32 d0, d1, d2
32 0[0-9a-f]+ <[^>]+> ef22 0d44 vsubeq\.f32 q0, q1, q2
[all …]
Dvfp-neon-syntax-inc.s8 .macro testvmov cond="" f32=".f32" f64=".f64"
10 vmov\cond\f32 s0,s1
12 vmov\cond\f32 s0,#0.25
25 .macro monadic op cond="" f32=".f32" f64=".f64"
27 \op\cond\f32 s0,s1
36 .macro dyadic op cond="" f32=".f32" f64=".f64"
38 \op\cond\f32 s0,s1,s2
47 .macro dyadicz op cond="" f32=".f32" f64=".f64"
49 \op\cond\f32 s0,#0
80 .macro cvtz cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64"
[all …]
Dvfp-neon-syntax_t2.d8 0[0-9a-f]+ <[^>]+> eeb0 0a60 (vmov\.f32|fcpys) s0, s1
10 0[0-9a-f]+ <[^>]+> eeb5 0a00 (vmov\.f32|fconsts) s0, #80.*
17 0[0-9a-f]+ <[^>]+> eeb0 0a60 (vmoveq\.f32|fcpyseq) s0, s1
19 0[0-9a-f]+ <[^>]+> eeb5 0a00 (vmoveq\.f32|fconstseq) s0, #80.*
26 0[0-9a-f]+ <[^>]+> eeb1 0ae0 (vsqrt\.f32|fsqrts) s0, s1
29 0[0-9a-f]+ <[^>]+> eeb1 0ae0 (vsqrteq\.f32|fsqrtseq) s0, s1
31 0[0-9a-f]+ <[^>]+> eeb0 0ae0 (vabs\.f32|fabss) s0, s1
34 0[0-9a-f]+ <[^>]+> eeb0 0ae0 (vabseq\.f32|fabsseq) s0, s1
36 0[0-9a-f]+ <[^>]+> eeb1 0a60 (vneg\.f32|fnegs) s0, s1
39 0[0-9a-f]+ <[^>]+> eeb1 0a60 (vnegeq\.f32|fnegseq) s0, s1
[all …]
Dual-vcmp.s5 vcmp.f32 s0, #0.0
6 vcmp.f32 s1, #0
7 vcmpe.f32 s3, #0.0
8 vcmpe.f32 s4, #0
9 vcmp.f32 s5, #0.0e2
10 vcmp.f32 s6, #0e-3
11 vcmpe.f32 s7, #0.0000
12 vcmpe.f32 s8, #.0
13 vcmp.f32 s9, #0x0
14 vcmpe.f32 s10, #0x0
Darmv7e-m+fpv5-d16.d8 0[0-9a-f]+ <[^>]+> fe00 0a00 vseleq.f32 s0, s0, s0
9 0[0-9a-f]+ <[^>]+> fe50 0aa0 vselvs.f32 s1, s1, s1
10 0[0-9a-f]+ <[^>]+> fe2f fa0f vselge.f32 s30, s30, s30
11 0[0-9a-f]+ <[^>]+> fe7f faaf vselgt.f32 s31, s31, s31
16 0[0-9a-f]+ <[^>]+> fe80 0a00 vmaxnm.f32 s0, s0, s0
17 0[0-9a-f]+ <[^>]+> fec0 0aa0 vmaxnm.f32 s1, s1, s1
18 0[0-9a-f]+ <[^>]+> fe8f fa0f vmaxnm.f32 s30, s30, s30
19 0[0-9a-f]+ <[^>]+> fecf faaf vmaxnm.f32 s31, s31, s31
24 0[0-9a-f]+ <[^>]+> fe80 0a40 vminnm.f32 s0, s0, s0
25 0[0-9a-f]+ <[^>]+> fec0 0ae0 vminnm.f32 s1, s1, s1
[all …]
Dneon-cond-bad.l6 [^:]*:27: Error: instruction cannot be conditional -- `vmuleq\.f32 d0,d1,d2'
8 [^:]*:28: Error: instruction cannot be conditional -- `vmlaeq\.f32 d0,d1,d2'
10 [^:]*:29: Error: instruction cannot be conditional -- `vmlseq\.f32 d0,d1,d2'
12 [^:]*:30: Error: instruction cannot be conditional -- `vaddeq\.f32 d0,d1,d2'
14 [^:]*:31: Error: instruction cannot be conditional -- `vsubeq\.f32 d0,d1,d2'
16 [^:]*:39: Error: instruction cannot be conditional -- `vabseq\.f32 d0,d1'
18 [^:]*:40: Error: instruction cannot be conditional -- `vnegeq\.f32 d0,d1'
20 [^:]*:48: Error: instruction cannot be conditional -- `vcvteq\.s32\.f32 d0,d1'
22 [^:]*:49: Error: instruction cannot be conditional -- `vcvteq\.u32\.f32 d0,d1'
24 [^:]*:50: Error: instruction cannot be conditional -- `vcvteq\.f32\.s32 d0,d1'
[all …]
Dual-vcmp.d9 0+000 <[^>]*> eeb50a40 vcmp.f32 s0, #0.0
10 0+004 <[^>]*> eef50a40 vcmp.f32 s1, #0.0
11 0+008 <[^>]*> eef51ac0 vcmpe.f32 s3, #0.0
12 0+00c <[^>]*> eeb52ac0 vcmpe.f32 s4, #0.0
13 0+010 <[^>]*> eef52a40 vcmp.f32 s5, #0.0
14 0+014 <[^>]*> eeb53a40 vcmp.f32 s6, #0.0
15 0+018 <[^>]*> eef53ac0 vcmpe.f32 s7, #0.0
16 0+01c <[^>]*> eeb54ac0 vcmpe.f32 s8, #0.0
17 0+020 <[^>]*> eef54a40 vcmp.f32 s9, #0.0
18 0+024 <[^>]*> eeb55ac0 vcmpe.f32 s10, #0.0
Dneon-cond-bad-inc.s21 .macro dyadic_eq op eq="eq" f32=".f32"
23 \op\eq\f32 d0,d1,d2
24 \op\eq\f32 q0,q1,q2
33 .macro monadic_eq op eq="eq" f32=".f32"
35 \op\eq\f32 d0,d1
36 \op\eq\f32 q0,q1
48 cvt s32 f32
49 cvt u32 f32
50 cvt f32 s32
51 cvt f32 u32
Dvfpv3-const-conv.d8 0[0-9a-f]+ <[^>]+> eef08a04 (vmov\.f32|fconsts) s17, #4.*
9 0[0-9a-f]+ <[^>]+> eeba9a05 (vmov\.f32|fconsts) s18, #165.*
10 0[0-9a-f]+ <[^>]+> eef49a00 (vmov\.f32|fconsts) s19, #64.*
14 0[0-9a-f]+ <[^>]+> eefa8a63 (vcvt\.f32\.s16 s17, s17, #9|fshtos s17, #9)
16 0[0-9a-f]+ <[^>]+> eefa8aeb (vcvt\.f32\.s32 s17, s17, #9|fsltos s17, #9)
18 0[0-9a-f]+ <[^>]+> eefb8a63 (vcvt\.f32\.u16 s17, s17, #9|fuhtos s17, #9)
20 0[0-9a-f]+ <[^>]+> eefb8aeb (vcvt\.f32\.u32 s17, s17, #9|fultos s17, #9)
22 0[0-9a-f]+ <[^>]+> eefe9a64 (vcvt\.s16\.f32 s19, s19, #7|ftoshs s19, #7)
24 0[0-9a-f]+ <[^>]+> eefe9aec (vcvt\.s32\.f32 s19, s19, #7|ftosls s19, #7)
26 0[0-9a-f]+ <[^>]+> eeff9a64 (vcvt\.u16\.f32 s19, s19, #7|ftouhs s19, #7)
[all …]
Dhalf-prec-psyntax.s2 vcvt d0.f16, q1.f32
3 vcvt q5.f32, d6.f16
4 vcvtt s2.f32, s5.f16
5 vcvtb s2.f32, s5.f16
6 vcvtt s2.f16, s5.f32
7 vcvtb s2.f16, s5.f32

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