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/toolchain/binutils/binutils-2.27/gas/config/
Dtc-i860.c261 struct i860_it pseudo[3]; in md_assemble() local
276 pseudo[i] = the_insn; in md_assemble()
294 pseudo[0].opcode = (the_insn.opcode & 0x001f0000) | 0xe4000000; in md_assemble()
295 pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_L); in md_assemble()
298 pseudo[1].opcode = (the_insn.opcode & 0x03ffffff) | 0xec000000 in md_assemble()
300 pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_H); in md_assemble()
313 pseudo[0].opcode = 0xec000000 | (the_insn.opcode & 0x03e00000) in md_assemble()
315 pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_HA); in md_assemble()
319 pseudo[1].opcode = (the_insn.opcode & ~0x03e00000) | (atmp << 21); in md_assemble()
320 pseudo[1].fi[0].fup = the_insn.fi[0].fup | OP_SEL_L; in md_assemble()
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/toolchain/binutils/binutils-2.27/gas/doc/
Dc-i860.texi64 Emit a warning message if any pseudo-instruction expansions occurred.
69 where @code{gcc} may emit these pseudo-instructions.
104 Change the temporary register used when expanding pseudo operations. The
123 @subsection Other instruction support (pseudo-instructions)
125 pseudo-instructions are supported. While these are supported, they are
128 are the pseudo-instructions that result in expansions.
132 The pseudo-instruction @code{mov imm,%rn} (where the immediate does
140 For example, the pseudo-instruction @code{ld.b addr_exp(%rx),%rn}
152 For instance, the pseudo-instruction @code{adds large_imm,%rx,%rn} expands to:
161 The pseudo-instruction @code{or large_imm,%rx,%rn} results in:
Dc-xstormy16.texi73 @cindex XStormy16 pseudo-opcodes
74 @cindex pseudo-opcodes for XStormy16
77 @code{@value{AS}} also implements the following pseudo ops:
81 @cindex @code{@@lo} pseudo-op, XStormy16
92 @cindex @code{@@hi} pseudo-op, XStormy16
Dc-mmix.texi256 @cindex pseudo-ops, MMIX
258 @cindex MMIX pseudo-ops
263 @cindex pseudo-op LOC, MMIX
265 @cindex MMIX pseudo-op LOC
292 @cindex pseudo-op LOCAL, MMIX
294 @cindex MMIX pseudo-op LOCAL
308 the use of this directive: the pseudo-directive must be placed in a
313 @cindex pseudo-op IS, MMIX
315 @cindex MMIX pseudo-op IS
331 @cindex pseudo-op GREG, MMIX
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Dc-v850.texi95 Enables relaxation. This allows the .longcall and .longjump pseudo
351 @code{@value{AS}} also implements the following pseudo ops:
355 @cindex @code{hi0} pseudo-op, V850
367 @cindex @code{lo} pseudo-op, V850
378 @cindex @code{hi} pseudo-op, V850
392 pseudo-op the movhi instruction would put 0xFFFF0000 into r6, then the
395 which is wrong (the fifth nibble is E). With the hi() pseudo op adding
396 in the top bit of the lo() pseudo op, the movhi instruction actually
400 @cindex @code{hilo} pseudo-op, V850
411 @cindex @code{sdaoff} pseudo-op, V850
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Dc-arm.texi963 An error occurs if the name is undefined. Note - this pseudo op can
1010 implements several pseudo opcodes, including several synthetic load
1015 @cindex @code{NOP} pseudo op, ARM
1021 This pseudo op will always evaluate to a legal ARM instruction that does
1024 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1036 @cindex @code{ADR reg,<label>} pseudo op, ARM
1049 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1114 pseudo ops to ensure that appropriate exception unwind information is
1120 To illustrate the use of these pseudo ops, we will examine the code
1173 instructions are not important since we are focusing on the pseudo ops
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Dc-cris.texi338 @cindex pseudo-ops, CRIS
340 @cindex CRIS pseudo-ops
342 There are a few CRIS-specific pseudo-directives in addition to
344 pseudo-directives are in little-endian order for CRIS. There is
350 @cindex pseudo-op .dword, CRIS
352 @cindex CRIS pseudo-op .dword
360 @cindex pseudo-op .syntax, CRIS
362 @cindex CRIS pseudo-op .syntax
399 @cindex pseudo-op .arch, CRIS
401 @cindex CRIS pseudo-op .arch
Dc-m68hc11.texi115 associated to the @samp{jbra}, @samp{jbsr} and @samp{jbXX} pseudo opcodes.
122 @samp{jbXX} pseudo opcodes.
410 @cindex pseudo-opcodes, M68HC11
411 @cindex M68HC11 pseudo-opcodes
415 Certain pseudo opcodes are permitted for branch instructions.
418 the start of Motorola mnemonic. These pseudo opcodes are not affected
421 The following table summarizes the pseudo-operations.
447 These are the simplest jump pseudo-operations; they always map to one
452 Here, @samp{jb@var{XX}} stands for an entire family of pseudo-operations,
454 list of pseudo-ops in this family is:
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/macros/
Ddot.l2 .*:[1-9][0-9]*: Warning: attempt to redefine pseudo-op .\.macro. ignored
3 .*:27: Error: unknown pseudo-op: .\.xyz.
/toolchain/binutils/binutils-2.27/gas/
DNEWS15 .extCoreRegister pseudo-ops that allow an user to define custom
144 pseudo op. It marks the symbol as being globally unique in the entire
147 * ARM assembler now supports .inst[.nw] pseudo-ops to insert opcodes specified
157 * The .type pseudo-op now accepts a type of STT_GNU_IFUNC which can be used to
168 * New pseudo op .cfi_val_encoded_addr, to record constant addresses in unwind
192 pseudo ops: .string16, .string32 and .string64.
202 * Added gas .reloc pseudo. This is a low-level interface for creating
266 * Added a pseudo-op (.secrel32) to generate 32 bit section relative relocations
276 * New command line option --alternate and pseudo-ops .altmacro and .noaltmacro
391 * x86 gas has a new .arch pseudo op to specify the target CPU architecture.
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/toolchain/binutils/binutils-2.27/gas/testsuite/gas/elf/
Dpseudo.d2 #error-output: pseudo.l
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/i386/
Drept.d3 # Test the .rept pseudo-op.
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/
Dadr.s1 @ test ADR pseudo-op
Dinst-po-2.d1 #name: .inst pseudo-opcode validations test
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/all/
Dstruct.d4 # Test the .struct pseudo-op.
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/sh/sh64/
Dsyntax-2.s4 ! pseudo-ops
Derr-abi-32.s1 ! Check .abi pseudo assertion.
Derr-abi-64.s1 ! Check .abi pseudo assertion.
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/mri/
Dfor.s1 ; Test MRI structured for pseudo-op.
Dwhile.s1 ; Test MRI structured while pseudo-op.
Drepeat.s1 ; Test MRI structured repeat pseudo-op.
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/pe/
Daligncomm-c.d4 # Test the aligned form of the .comm pseudo-op.
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/i386/ilp32/elf/
Dstruct.d5 # Test the .struct pseudo-op.
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/i860/
Dpseudo-ops01.s1 # Test some assembler pseudo-operations:
/toolchain/binutils/binutils-2.27/ld/testsuite/ld-mmix/
Dloc9.d4 # Setting file start through the LOC pseudo, see PR 6607.

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